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Rev 1560 Rev 1599
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;;                                                              ;;
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;;                                                              ;;
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;;  HT.inc                                                      ;;                                                    ;;
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;;  HT.inc                                                      ;;                                                    ;;
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;;                                                              ;;
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;;                                                              ;;
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;;  AMD HyperTransport bus control                              ;;
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;;  AMD HyperTransport bus control                              ;;
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;;                                                              ;;
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;;                                                              ;;
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;;                  art_zh                  ;;
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;;                  art_zh                ;;
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;;                                                              ;;
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;;                                                              ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision: 1554 $
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$Revision: 1554 $
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NB_MISC_INDEX	equ	0xF0000060	; NB Misc indirect access
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NB_MISC_DATA	equ	0xF0000064
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PCIEIND_INDEX	equ	0xF00000E0	; PCIe Core indirect config space access
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HTIU_NB_INDEX	equ	0xF0000094	; HyperTransport indirect config space access
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;=============================================================================
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;=============================================================================
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	out	dx,  eax
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	out	dx,  eax
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	ret
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	ret
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align 4
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;------------------------------------------
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;       params:   al = nbconfig register#
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align 4
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;                ebx = register content
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;
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rs7xx_nbconfig_write_pci:
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rs7xx_nbconfig_write_pci:
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	and	eax, 0x0FC		 ; leave register# only
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	and	eax, 0x0FC		 ; leave register# only
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	or	eax, 0x80000000 	 ; bdf = 0:0.0
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	or	eax, 0x80000000 	 ; bdf = 0:0.0
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	out	dx, eax
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	out	dx, eax
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	ret
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	ret
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 63 
 
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;***************************************************************************
 64 
;***************************************************************************
- 
 
 65 
;   Function
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;      rs7xx_unlock_bar3:     unlocks the BAR3 register of nbconfig that
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;                             makes pcie config address space visible
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;   -----------------------
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;   in: nothing      out: nothing      destroys:   eax ebx edx
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;
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;***************************************************************************
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align 4
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rs7xx_unlock_bar3:
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	mov	eax, NB_MISC_INDEX
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	mov	ebx, 0x080			; reg#0; write-enable
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	call	rs7xx_nbconfig_write_pci	; set index
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	mov	eax, NB_MISC_DATA
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	call	rs7xx_nbconfig_read_pci 	; read data
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	mov	ebx, eax
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	and	ebx, 0xFFFFFFF7 		; clear bit3
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	mov	eax, NB_MISC_DATA
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	call	rs7xx_nbconfig_write_pci	; write it back
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	mov	eax, NB_MISC_INDEX
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	xor	ebx, ebx			; reg#0; write-locked
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	call	rs7xx_nbconfig_write_pci	; set index
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	ret
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;--------------------------------------------------------------
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align 4
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rs780_read_misc:
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;  in: eax(al) - reg#           out: eax = NBMISCIND data
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	push	edx
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	mov	edx, NB_MISC_INDEX
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	and	eax, 0x07F
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	mov	[edx], eax
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	add	dl, 4
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	mov	eax, [edx]
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	pop	edx
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	ret
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;-------------------------------------------
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align 4
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rs780_write_misc:
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;  in: eax(al) - reg#     ebx = NBMISCIND data
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	push	edx
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	mov	edx, NB_MISC_INDEX
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	and	eax, 0x07F
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	or	eax, 0x080		; set WE
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	mov	[edx], eax
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	add	dl, 4
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	mov	[edx], ebx
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	sub	dl, 4
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	xor	eax,   eax
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	mov	[edx], eax		; safety last
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	pop	edx
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	ret
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;-------------------------------------------------------------
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align 4
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rs780_read_pcieind:
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;  in: ah = bridge#, al = reg#           out: eax = PCIEIND data
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	push	edx
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	xor	edx, edx
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	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
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	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
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	shl	edx, 15 		; device#
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	add	edx, PCIEIND_INDEX	; full bdf-address
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	and	eax, 0x30FF
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	or	al,  al
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	jnz	@f
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	shl	eax, 4			; set bits 17..16 for a Core bridge
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 132 
@@:
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	mov	[edx], eax
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	add	dl,  4
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 135 
	mov	eax, [edx]
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	pop	edx
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	ret
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;-------------------------------------------
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 140 
align 4
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rs780_write_pcieind:
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;  in: ah = bridge#, al = reg#,  ebx = PCIEIND data
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	push	edx
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	xor	edx, edx
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	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
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	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
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	shl	edx, 15 		; device#
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	add	edx, PCIEIND_INDEX	; full bdf-address
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	and	eax, 0x30FF
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	or	al,  al
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	jnz	@f
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	shl	eax, 4			; set bits 17..16 for a Core bridge
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@@:
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 154 
	mov	[edx], eax
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	add	dl,  4
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 156 
	mov	[edx], ebx
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	sub	dl,  4
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	xor	eax,   eax
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	mov	[edx], eax		; safety last
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	pop	edx
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	ret
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;------------------------------------------------
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align 4
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rs780_read_htiu:
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; in:  al = reg#  |  out: eax = HTIU data
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;------------------------------------------------
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	push	edx
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	mov	edx,  HTIU_NB_INDEX
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	and	eax, 0x07F
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	mov	[edx], eax
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	add	dl,  4
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	mov	eax, [edx]
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 174 
	pop	edx
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	ret
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;------------------------------------------------
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align 4
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rs780_write_htiu:
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; in:  al = reg#; ebx = data
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;------------------------------------------------
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	push	edx
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	mov	edx,  HTIU_NB_INDEX
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	and	eax, 0x07F
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	or	eax, 0x100
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	mov	[edx], eax
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	add	dl,  4
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	mov	[edx], ebx
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	sub	dl,  4
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	xor	eax,   eax
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	mov	[edx], eax
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	pop	edx
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	ret
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;***************************************************************************
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;   Function
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;   Function
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;      rs7xx_pcie_init:
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;      rs7xx_pcie_init:
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;
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;
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;   Description
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;   Description
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;       PCIe extended (memory-mapped) config space detection
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;       PCIe extended (memory-mapped) config space detection
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;
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;
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;***************************************************************************
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;***************************************************************************
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 204 
 
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align 4
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align 4
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rs7xx_pcie_init:
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rs7xx_pcie_init:
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	call	rs7xx_unlock_bar3
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	mov	al, 0x7C		       ; NB_IOC_CFG_CNTL
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	mov	al, 0x7C		       ; NB_IOC_CFG_CNTL
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	call	rs7xx_nbconfig_read_pci
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	call	rs7xx_nbconfig_read_pci
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	mov	byte[mmio_pcie_cfg_pdes], dl
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	mov	byte[mmio_pcie_cfg_pdes], dl
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@@:
 259 
@@:
120 
	xor	dx,  dx 			; PDEs counter
 260 
	xor	dx,  dx 			; PDEs counter
121 
@@:
 261 
@@:
122 
	mov	dword[ebx], eax 		; map 4 buses
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	mov	dword[ebx], eax 		; map 4 buses
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	invlpg	[ecx]				; next PgDir entry
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124 
	add	bx,  4				; new PDE
 263 
	add	bx,  4				; new PDE
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	add	eax, 0x400000			; +4M phys.
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	add	eax, 0x400000			; +4M phys.
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	add	ecx, 0x400000			; +4M lin.
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	add	ecx, 0x400000			; +4M lin.
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	cmp	dl, byte[mmio_pcie_cfg_pdes]
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	cmp	dl, byte[mmio_pcie_cfg_pdes]
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	jnc	.pcie_cfg_mapped
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	jnc	.pcie_cfg_mapped
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	inc	dl
 268 
	inc	dl
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	jmp	@b
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	jmp	@b
- 
 
 270 
	mov	eax, cr3
- 
 
 271 
	mov	cr3, eax			; flush TLB
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.pcie_cfg_mapped:
 272 
.pcie_cfg_mapped:
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	mov	esi, boot_pcie_ok
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	mov	esi, boot_pcie_ok
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	call	boot_log
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	call	boot_log
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	ret	; <<< OK >>>
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	ret	; <<< OK >>>
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.rs7xx_pcie_fail:
 276 
.rs7xx_pcie_fail:
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	mov	esi, boot_rs7xx_fail
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	mov	esi, boot_rs7xx_fail
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	call	boot_log
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	call	boot_log
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	ret
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	jmp	$
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.rs7xx_pcie_blocked:
 280 
.rs7xx_pcie_blocked:
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	mov	esi, boot_rs7xx_blkd
 281 
	mov	esi, boot_rs7xx_blkd
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	call	boot_log
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	call	boot_log
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	call	pci_ext_config
 - 
 
143 
	jmp	.addr_found
 - 
 
144 
	ret
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	jmp	$