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1
/**************************************************************************
1
/**************************************************************************
2
 *
2
 *
3
 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
3
 * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA
4
 * All Rights Reserved.
4
 * All Rights Reserved.
5
 *
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the
7
 * copy of this software and associated documentation files (the
8
 * "Software"), to deal in the Software without restriction, including
8
 * "Software"), to deal in the Software without restriction, including
9
 * without limitation the rights to use, copy, modify, merge, publish,
9
 * without limitation the rights to use, copy, modify, merge, publish,
10
 * distribute, sub license, and/or sell copies of the Software, and to
10
 * distribute, sub license, and/or sell copies of the Software, and to
11
 * permit persons to whom the Software is furnished to do so, subject to
11
 * permit persons to whom the Software is furnished to do so, subject to
12
 * the following conditions:
12
 * the following conditions:
13
 *
13
 *
14
 * The above copyright notice and this permission notice (including the
14
 * The above copyright notice and this permission notice (including the
15
 * next paragraph) shall be included in all copies or substantial portions
15
 * next paragraph) shall be included in all copies or substantial portions
16
 * of the Software.
16
 * of the Software.
17
 *
17
 *
18
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
21
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25
 *
25
 *
26
 **************************************************************************/
26
 **************************************************************************/
27
 
27
 
28
#include 
28
#include 
29
#include "vmwgfx_drv.h"
29
#include "vmwgfx_drv.h"
30
 
-
 
31
#define TASK_INTERRUPTIBLE      1
-
 
32
#define TASK_UNINTERRUPTIBLE    2
-
 
33
 
30
 
34
#define VMW_FENCE_WRAP (1 << 24)
31
#define VMW_FENCE_WRAP (1 << 24)
35
 
32
 
36
irqreturn_t vmw_irq_handler(int irq, void *arg)
33
irqreturn_t vmw_irq_handler(int irq, void *arg)
37
{
34
{
38
	struct drm_device *dev = (struct drm_device *)arg;
35
	struct drm_device *dev = (struct drm_device *)arg;
39
	struct vmw_private *dev_priv = vmw_priv(dev);
36
	struct vmw_private *dev_priv = vmw_priv(dev);
40
	uint32_t status, masked_status;
37
	uint32_t status, masked_status;
41
 
-
 
42
	spin_lock(&dev_priv->irq_lock);
38
 
43
	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
39
	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
44
	masked_status = status & dev_priv->irq_mask;
-
 
45
	spin_unlock(&dev_priv->irq_lock);
40
	masked_status = status & READ_ONCE(dev_priv->irq_mask);
46
 
41
 
47
	if (likely(status))
42
	if (likely(status))
48
		outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
43
		outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
49
 
44
 
50
	if (!masked_status)
45
	if (!status)
51
		return IRQ_NONE;
46
		return IRQ_NONE;
52
 
47
 
53
	if (masked_status & (SVGA_IRQFLAG_ANY_FENCE |
48
	if (masked_status & (SVGA_IRQFLAG_ANY_FENCE |
54
			     SVGA_IRQFLAG_FENCE_GOAL)) {
49
			     SVGA_IRQFLAG_FENCE_GOAL)) {
55
		vmw_fences_update(dev_priv->fman);
50
		vmw_fences_update(dev_priv->fman);
56
		wake_up_all(&dev_priv->fence_queue);
51
		wake_up_all(&dev_priv->fence_queue);
57
	}
52
	}
58
 
53
 
59
	if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS)
54
	if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS)
60
		wake_up_all(&dev_priv->fifo_queue);
55
		wake_up_all(&dev_priv->fifo_queue);
61
 
56
 
62
 
57
 
63
	return IRQ_HANDLED;
58
	return IRQ_HANDLED;
64
}
59
}
65
 
60
 
66
static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)
61
static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)
67
{
62
{
68
	uint32_t busy;
-
 
69
 
-
 
70
	mutex_lock(&dev_priv->hw_mutex);
-
 
71
	busy = vmw_read(dev_priv, SVGA_REG_BUSY);
-
 
72
	mutex_unlock(&dev_priv->hw_mutex);
-
 
73
 
63
 
74
	return (busy == 0);
64
	return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0);
75
}
65
}
76
 
66
 
77
void vmw_update_seqno(struct vmw_private *dev_priv,
67
void vmw_update_seqno(struct vmw_private *dev_priv,
78
			 struct vmw_fifo_state *fifo_state)
68
			 struct vmw_fifo_state *fifo_state)
79
{
69
{
80
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
70
	u32 *fifo_mem = dev_priv->mmio_virt;
81
	uint32_t seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
71
	uint32_t seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
82
 
72
 
83
	if (dev_priv->last_read_seqno != seqno) {
73
	if (dev_priv->last_read_seqno != seqno) {
84
		dev_priv->last_read_seqno = seqno;
74
		dev_priv->last_read_seqno = seqno;
85
		vmw_marker_pull(&fifo_state->marker_queue, seqno);
75
		vmw_marker_pull(&fifo_state->marker_queue, seqno);
86
		vmw_fences_update(dev_priv->fman);
76
		vmw_fences_update(dev_priv->fman);
87
	}
77
	}
88
}
78
}
89
 
79
 
90
bool vmw_seqno_passed(struct vmw_private *dev_priv,
80
bool vmw_seqno_passed(struct vmw_private *dev_priv,
91
			 uint32_t seqno)
81
			 uint32_t seqno)
92
{
82
{
93
	struct vmw_fifo_state *fifo_state;
83
	struct vmw_fifo_state *fifo_state;
94
	bool ret;
84
	bool ret;
95
 
85
 
96
	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
86
	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
97
		return true;
87
		return true;
98
 
88
 
99
	fifo_state = &dev_priv->fifo;
89
	fifo_state = &dev_priv->fifo;
100
	vmw_update_seqno(dev_priv, fifo_state);
90
	vmw_update_seqno(dev_priv, fifo_state);
101
	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
91
	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
102
		return true;
92
		return true;
103
 
93
 
104
	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
94
	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
105
	    vmw_fifo_idle(dev_priv, seqno))
95
	    vmw_fifo_idle(dev_priv, seqno))
106
		return true;
96
		return true;
107
 
97
 
108
	/**
98
	/**
109
	 * Then check if the seqno is higher than what we've actually
99
	 * Then check if the seqno is higher than what we've actually
110
	 * emitted. Then the fence is stale and signaled.
100
	 * emitted. Then the fence is stale and signaled.
111
	 */
101
	 */
112
 
102
 
113
	ret = ((atomic_read(&dev_priv->marker_seq) - seqno)
103
	ret = ((atomic_read(&dev_priv->marker_seq) - seqno)
114
	       > VMW_FENCE_WRAP);
104
	       > VMW_FENCE_WRAP);
115
 
105
 
116
	return ret;
106
	return ret;
117
}
107
}
118
 
108
 
119
int vmw_fallback_wait(struct vmw_private *dev_priv,
109
int vmw_fallback_wait(struct vmw_private *dev_priv,
120
		      bool lazy,
110
		      bool lazy,
121
		      bool fifo_idle,
111
		      bool fifo_idle,
122
		      uint32_t seqno,
112
		      uint32_t seqno,
123
		      bool interruptible,
113
		      bool interruptible,
124
		      unsigned long timeout)
114
		      unsigned long timeout)
125
{
115
{
126
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
116
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
127
 
117
 
128
	uint32_t count = 0;
118
	uint32_t count = 0;
129
	uint32_t signal_seq;
119
	uint32_t signal_seq;
130
	int ret;
120
	int ret;
131
	unsigned long end_jiffies = jiffies + timeout;
121
	unsigned long end_jiffies = jiffies + timeout;
132
	bool (*wait_condition)(struct vmw_private *, uint32_t);
122
	bool (*wait_condition)(struct vmw_private *, uint32_t);
133
	DEFINE_WAIT(__wait);
123
	DEFINE_WAIT(__wait);
134
 
124
 
135
	wait_condition = (fifo_idle) ? &vmw_fifo_idle :
125
	wait_condition = (fifo_idle) ? &vmw_fifo_idle :
136
		&vmw_seqno_passed;
126
		&vmw_seqno_passed;
137
 
127
 
138
	/**
128
	/**
139
	 * Block command submission while waiting for idle.
129
	 * Block command submission while waiting for idle.
140
	 */
130
	 */
141
 
131
 
142
//   if (fifo_idle)
132
//   if (fifo_idle)
143
//       down_read(&fifo_state->rwsem);
133
//       down_read(&fifo_state->rwsem);
144
	signal_seq = atomic_read(&dev_priv->marker_seq);
134
	signal_seq = atomic_read(&dev_priv->marker_seq);
145
	ret = 0;
135
	ret = 0;
146
 
136
 
147
	for (;;) {
137
	for (;;) {
148
//       prepare_to_wait(&dev_priv->fence_queue, &__wait,
138
//       prepare_to_wait(&dev_priv->fence_queue, &__wait,
149
//               (interruptible) ?
139
//               (interruptible) ?
150
//               TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
140
//               TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
151
		if (wait_condition(dev_priv, seqno))
141
		if (wait_condition(dev_priv, seqno))
152
			break;
142
			break;
153
		if (time_after_eq(jiffies, end_jiffies)) {
143
		if (time_after_eq(jiffies, end_jiffies)) {
154
			DRM_ERROR("SVGA device lockup.\n");
144
			DRM_ERROR("SVGA device lockup.\n");
155
			break;
145
			break;
156
		}
146
		}
157
		if (lazy)
147
		if (lazy)
158
            delay(1);
148
            delay(1);
159
		else if ((++count & 0x0F) == 0) {
149
		else if ((++count & 0x0F) == 0) {
160
			/**
150
			/**
161
			 * FIXME: Use schedule_hr_timeout here for
151
			 * FIXME: Use schedule_hr_timeout here for
162
			 * newer kernels and lower CPU utilization.
152
			 * newer kernels and lower CPU utilization.
163
			 */
153
			 */
164
 
154
 
165
            delay(1);
155
            delay(1);
166
		}
156
		}
167
	}
157
	}
168
//   finish_wait(&dev_priv->fence_queue, &__wait);
158
//   finish_wait(&dev_priv->fence_queue, &__wait);
169
	if (ret == 0 && fifo_idle) {
159
	if (ret == 0 && fifo_idle) {
170
		__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
160
		u32 *fifo_mem = dev_priv->mmio_virt;
-
 
161
 
171
		iowrite32(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
162
		vmw_mmio_write(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
172
	}
163
	}
173
	wake_up_all(&dev_priv->fence_queue);
164
	wake_up_all(&dev_priv->fence_queue);
174
//   if (fifo_idle)
165
//   if (fifo_idle)
175
//       up_read(&fifo_state->rwsem);
166
//       up_read(&fifo_state->rwsem);
176
 
167
 
177
	return ret;
168
	return ret;
178
}
169
}
179
 
170
 
-
 
171
void vmw_generic_waiter_add(struct vmw_private *dev_priv,
180
void vmw_seqno_waiter_add(struct vmw_private *dev_priv)
172
			    u32 flag, int *waiter_count)
181
{
173
{
182
	mutex_lock(&dev_priv->hw_mutex);
174
	spin_lock(&dev_priv->waiter_lock);
183
	if (dev_priv->fence_queue_waiters++ == 0) {
-
 
184
		unsigned long irq_flags;
-
 
185
 
-
 
186
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
-
 
187
		outl(SVGA_IRQFLAG_ANY_FENCE,
175
	if ((*waiter_count)++ == 0) {
188
		     dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
176
		outl(flag, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
189
		dev_priv->irq_mask |= SVGA_IRQFLAG_ANY_FENCE;
177
		dev_priv->irq_mask |= flag;
190
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
-
 
191
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
178
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
192
	}
179
	}
193
	mutex_unlock(&dev_priv->hw_mutex);
180
	spin_unlock(&dev_priv->waiter_lock);
194
}
181
}
-
 
182
 
195
 
183
void vmw_generic_waiter_remove(struct vmw_private *dev_priv,
196
void vmw_seqno_waiter_remove(struct vmw_private *dev_priv)
184
			       u32 flag, int *waiter_count)
197
{
185
{
198
	mutex_lock(&dev_priv->hw_mutex);
-
 
199
	if (--dev_priv->fence_queue_waiters == 0) {
-
 
200
		unsigned long irq_flags;
-
 
201
 
186
	spin_lock(&dev_priv->waiter_lock);
202
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
187
	if (--(*waiter_count) == 0) {
203
		dev_priv->irq_mask &= ~SVGA_IRQFLAG_ANY_FENCE;
-
 
204
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
188
		dev_priv->irq_mask &= ~flag;
205
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
189
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
206
	}
190
	}
-
 
191
	spin_unlock(&dev_priv->waiter_lock);
-
 
192
}
-
 
193
 
-
 
194
void vmw_seqno_waiter_add(struct vmw_private *dev_priv)
-
 
195
{
207
	mutex_unlock(&dev_priv->hw_mutex);
196
	vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ANY_FENCE,
208
}
197
			       &dev_priv->fence_queue_waiters);
209
 
198
}
210
 
199
 
211
void vmw_goal_waiter_add(struct vmw_private *dev_priv)
-
 
212
{
-
 
213
	mutex_lock(&dev_priv->hw_mutex);
-
 
214
	if (dev_priv->goal_queue_waiters++ == 0) {
-
 
215
		unsigned long irq_flags;
-
 
216
 
-
 
217
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
-
 
218
		outl(SVGA_IRQFLAG_FENCE_GOAL,
-
 
219
		     dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
200
void vmw_seqno_waiter_remove(struct vmw_private *dev_priv)
-
 
201
{
-
 
202
	vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_ANY_FENCE,
-
 
203
				  &dev_priv->fence_queue_waiters);
-
 
204
}
220
		dev_priv->irq_mask |= SVGA_IRQFLAG_FENCE_GOAL;
205
 
221
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
206
void vmw_goal_waiter_add(struct vmw_private *dev_priv)
222
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
207
{
223
	}
208
	vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
224
	mutex_unlock(&dev_priv->hw_mutex);
209
			       &dev_priv->goal_queue_waiters);
225
}
210
}
226
 
211
 
227
void vmw_goal_waiter_remove(struct vmw_private *dev_priv)
212
void vmw_goal_waiter_remove(struct vmw_private *dev_priv)
228
{
213
{
229
	mutex_lock(&dev_priv->hw_mutex);
214
	vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
230
	if (--dev_priv->goal_queue_waiters == 0) {
215
				  &dev_priv->goal_queue_waiters);
231
		unsigned long irq_flags;
-
 
232
 
-
 
233
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
-
 
234
		dev_priv->irq_mask &= ~SVGA_IRQFLAG_FENCE_GOAL;
-
 
235
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
-
 
236
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
-
 
237
	}
-
 
238
	mutex_unlock(&dev_priv->hw_mutex);
-
 
239
}
216
}
240
 
217
 
241
int vmw_wait_seqno(struct vmw_private *dev_priv,
218
int vmw_wait_seqno(struct vmw_private *dev_priv,
242
		      bool lazy, uint32_t seqno,
219
		      bool lazy, uint32_t seqno,
243
		      bool interruptible, unsigned long timeout)
220
		      bool interruptible, unsigned long timeout)
244
{
221
{
245
	long ret;
222
	long ret;
246
	struct vmw_fifo_state *fifo = &dev_priv->fifo;
223
	struct vmw_fifo_state *fifo = &dev_priv->fifo;
247
 
224
 
248
	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
225
	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
249
		return 0;
226
		return 0;
250
 
227
 
251
	if (likely(vmw_seqno_passed(dev_priv, seqno)))
228
	if (likely(vmw_seqno_passed(dev_priv, seqno)))
252
		return 0;
229
		return 0;
253
 
230
 
254
	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
231
	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
255
 
232
 
256
	if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE))
233
	if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE))
257
		return vmw_fallback_wait(dev_priv, lazy, true, seqno,
234
		return vmw_fallback_wait(dev_priv, lazy, true, seqno,
258
					 interruptible, timeout);
235
					 interruptible, timeout);
259
 
236
 
260
	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
237
	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
261
		return vmw_fallback_wait(dev_priv, lazy, false, seqno,
238
		return vmw_fallback_wait(dev_priv, lazy, false, seqno,
262
					 interruptible, timeout);
239
					 interruptible, timeout);
263
 
240
 
264
	vmw_seqno_waiter_add(dev_priv);
241
	vmw_seqno_waiter_add(dev_priv);
265
 
242
 
266
	if (interruptible)
243
	if (interruptible)
267
		ret = wait_event_interruptible_timeout
244
		ret = wait_event_interruptible_timeout
268
		    (dev_priv->fence_queue,
245
		    (dev_priv->fence_queue,
269
		     vmw_seqno_passed(dev_priv, seqno),
246
		     vmw_seqno_passed(dev_priv, seqno),
270
		     timeout);
247
		     timeout);
271
	else
248
	else
272
		ret = wait_event_timeout
249
		ret = wait_event_timeout
273
		    (dev_priv->fence_queue,
250
		    (dev_priv->fence_queue,
274
		     vmw_seqno_passed(dev_priv, seqno),
251
		     vmw_seqno_passed(dev_priv, seqno),
275
		     timeout);
252
		     timeout);
276
 
253
 
277
	vmw_seqno_waiter_remove(dev_priv);
254
	vmw_seqno_waiter_remove(dev_priv);
278
 
255
 
279
	if (unlikely(ret == 0))
256
	if (unlikely(ret == 0))
280
		ret = -EBUSY;
257
		ret = -EBUSY;
281
	else if (likely(ret > 0))
258
	else if (likely(ret > 0))
282
		ret = 0;
259
		ret = 0;
283
 
260
 
284
	return ret;
261
	return ret;
285
}
262
}
286
 
263
 
287
void vmw_irq_preinstall(struct drm_device *dev)
264
void vmw_irq_preinstall(struct drm_device *dev)
288
{
265
{
289
	struct vmw_private *dev_priv = vmw_priv(dev);
266
	struct vmw_private *dev_priv = vmw_priv(dev);
290
	uint32_t status;
267
	uint32_t status;
291
 
268
 
292
	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
269
	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
293
		return;
270
		return;
294
 
-
 
295
	spin_lock_init(&dev_priv->irq_lock);
271
 
296
	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
272
	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
297
	outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
273
	outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
298
}
274
}
299
 
275
 
300
int vmw_irq_postinstall(struct drm_device *dev)
276
int vmw_irq_postinstall(struct drm_device *dev)
301
{
277
{
302
	return 0;
278
	return 0;
303
}
279
}
304
 
280
 
305
void vmw_irq_uninstall(struct drm_device *dev)
281
void vmw_irq_uninstall(struct drm_device *dev)
306
{
282
{
307
	struct vmw_private *dev_priv = vmw_priv(dev);
283
	struct vmw_private *dev_priv = vmw_priv(dev);
308
	uint32_t status;
284
	uint32_t status;
309
 
285
 
310
	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
286
	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
311
		return;
287
		return;
312
 
-
 
313
	mutex_lock(&dev_priv->hw_mutex);
288
 
314
	vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
-
 
315
	mutex_unlock(&dev_priv->hw_mutex);
289
	vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
316
 
290
 
317
	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
291
	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
318
	outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
292
	outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
319
}
293
}
320
 
-
 
321
int autoremove_wake_function(wait_queue_t *wait, unsigned mode, int sync, void *key)
-
 
322
{
-
 
323
    list_del_init(&wait->task_list);
-
 
324
    return 1;
-
 
325
}
-
 
326
-