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1 | /************************************************************************** |
1 | /************************************************************************** |
2 | * |
2 | * |
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA |
3 | * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA |
4 | * All Rights Reserved. |
4 | * All Rights Reserved. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the |
7 | * copy of this software and associated documentation files (the |
8 | * "Software"), to deal in the Software without restriction, including |
8 | * "Software"), to deal in the Software without restriction, including |
Line 22... | Line 22... | ||
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
25 | * |
25 | * |
26 | **************************************************************************/ |
26 | **************************************************************************/ |
27 | #define mb() asm volatile("mfence" : : : "memory") |
- | |
28 | #define rmb() asm volatile("lfence" : : : "memory") |
- | |
29 | #define wmb() asm volatile("sfence" : : : "memory") |
- | |
Line 30... | Line 27... | ||
30 | 27 | ||
31 | #include "vmwgfx_drv.h" |
28 | #include "vmwgfx_drv.h" |
32 | #include |
29 | #include |
Line 33... | Line 30... | ||
33 | #include |
30 | #include |
- | 31 | ||
34 | 32 | struct vmw_temp_set_context { |
|
- | 33 | SVGA3dCmdHeader header; |
|
Line 35... | Line 34... | ||
35 | #define TASK_INTERRUPTIBLE 1 |
34 | SVGA3dCmdDXTempSetContext body; |
36 | #define TASK_UNINTERRUPTIBLE 2 |
35 | }; |
37 | 36 | ||
38 | bool vmw_fifo_have_3d(struct vmw_private *dev_priv) |
37 | bool vmw_fifo_have_3d(struct vmw_private *dev_priv) |
39 | { |
38 | { |
Line 40... | Line 39... | ||
40 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
39 | u32 *fifo_mem = dev_priv->mmio_virt; |
41 | uint32_t fifo_min, hwversion; |
40 | uint32_t fifo_min, hwversion; |
Line 48... | Line 47... | ||
48 | uint32_t result; |
47 | uint32_t result; |
Line 49... | Line 48... | ||
49 | 48 | ||
50 | if (!dev_priv->has_mob) |
49 | if (!dev_priv->has_mob) |
Line 51... | Line 50... | ||
51 | return false; |
50 | return false; |
52 | 51 | ||
53 | mutex_lock(&dev_priv->hw_mutex); |
52 | spin_lock(&dev_priv->cap_lock); |
54 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); |
53 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); |
Line 55... | Line 54... | ||
55 | result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); |
54 | result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); |
56 | mutex_unlock(&dev_priv->hw_mutex); |
55 | spin_unlock(&dev_priv->cap_lock); |
Line 57... | Line 56... | ||
57 | 56 | ||
58 | return (result != 0); |
57 | return (result != 0); |
Line 59... | Line 58... | ||
59 | } |
58 | } |
60 | 59 | ||
61 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
60 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
Line 62... | Line 61... | ||
62 | return false; |
61 | return false; |
63 | 62 | ||
64 | fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
63 | fifo_min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); |
65 | if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) |
64 | if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) |
66 | return false; |
65 | return false; |
Line 75... | Line 74... | ||
75 | return false; |
74 | return false; |
Line 76... | Line 75... | ||
76 | 75 | ||
77 | if (hwversion < SVGA3D_HWVERSION_WS8_B1) |
76 | if (hwversion < SVGA3D_HWVERSION_WS8_B1) |
Line 78... | Line 77... | ||
78 | return false; |
77 | return false; |
79 | 78 | ||
80 | /* Non-Screen Object path does not support surfaces */ |
79 | /* Legacy Display Unit does not support surfaces */ |
Line 81... | Line 80... | ||
81 | if (!dev_priv->sou_priv) |
80 | if (dev_priv->active_display_unit == vmw_du_legacy) |
82 | return false; |
81 | return false; |
Line 83... | Line 82... | ||
83 | 82 | ||
84 | return true; |
83 | return true; |
85 | } |
84 | } |
86 | 85 | ||
Line 87... | Line 86... | ||
87 | bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) |
86 | bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) |
88 | { |
87 | { |
Line 89... | Line 88... | ||
89 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
88 | u32 *fifo_mem = dev_priv->mmio_virt; |
90 | uint32_t caps; |
89 | uint32_t caps; |
91 | 90 | ||
Line 92... | Line 91... | ||
92 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
91 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
93 | return false; |
92 | return false; |
Line 94... | Line 93... | ||
94 | 93 | ||
95 | caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); |
94 | caps = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES); |
96 | if (caps & SVGA_FIFO_CAP_PITCHLOCK) |
95 | if (caps & SVGA_FIFO_CAP_PITCHLOCK) |
97 | return true; |
96 | return true; |
98 | 97 | ||
99 | return false; |
- | |
Line -... | Line 98... | ||
- | 98 | return false; |
|
100 | } |
99 | } |
101 | 100 | ||
102 | int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
101 | int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
103 | { |
102 | { |
Line 104... | Line 103... | ||
104 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
103 | u32 *fifo_mem = dev_priv->mmio_virt; |
105 | uint32_t max; |
104 | uint32_t max; |
106 | uint32_t min; |
105 | uint32_t min; |
Line 107... | Line 106... | ||
107 | uint32_t dummy; |
106 | |
108 | 107 | fifo->dx = false; |
|
109 | fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; |
- | |
110 | fifo->static_buffer = KernelAlloc(fifo->static_buffer_size); |
- | |
111 | if (unlikely(fifo->static_buffer == NULL)) |
- | |
112 | return -ENOMEM; |
- | |
Line 113... | Line 108... | ||
113 | 108 | fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; |
|
114 | fifo->dynamic_buffer = NULL; |
109 | fifo->static_buffer = vmalloc(fifo->static_buffer_size); |
115 | fifo->reserved_size = 0; |
110 | if (unlikely(fifo->static_buffer == NULL)) |
Line 116... | Line -... | ||
116 | fifo->using_bounce_buffer = false; |
- | |
117 | 111 | return -ENOMEM; |
|
118 | mutex_init(&fifo->fifo_mutex); |
112 | |
119 | // init_rwsem(&fifo->rwsem); |
113 | fifo->dynamic_buffer = NULL; |
- | 114 | fifo->reserved_size = 0; |
|
- | 115 | fifo->using_bounce_buffer = false; |
|
- | 116 | ||
120 | 117 | mutex_init(&fifo->fifo_mutex); |
|
Line 121... | Line 118... | ||
121 | /* |
118 | init_rwsem(&fifo->rwsem); |
122 | * Allow mapping the first page read-only to user-space. |
119 | |
123 | */ |
120 | DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); |
124 | 121 | DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); |
|
Line 125... | Line 122... | ||
125 | DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); |
122 | DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); |
126 | DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); |
123 | |
Line 127... | Line 124... | ||
127 | DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); |
124 | dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); |
128 | 125 | dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); |
|
129 | mutex_lock(&dev_priv->hw_mutex); |
126 | dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); |
130 | dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); |
127 | |
131 | dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); |
128 | vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | |
132 | dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); |
129 | SVGA_REG_ENABLE_HIDE); |
133 | vmw_write(dev_priv, SVGA_REG_ENABLE, 1); |
130 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); |
Line 134... | Line 131... | ||
134 | 131 | ||
135 | min = 4; |
- | |
Line 136... | Line 132... | ||
136 | if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO) |
132 | min = 4; |
137 | min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); |
133 | if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO) |
138 | min <<= 2; |
134 | min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); |
Line 139... | Line 135... | ||
139 | 135 | min <<= 2; |
|
140 | if (min < PAGE_SIZE) |
136 | |
141 | min = PAGE_SIZE; |
137 | if (min < PAGE_SIZE) |
142 | 138 | min = PAGE_SIZE; |
|
Line 143... | Line 139... | ||
143 | iowrite32(min, fifo_mem + SVGA_FIFO_MIN); |
139 | |
144 | iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); |
140 | vmw_mmio_write(min, fifo_mem + SVGA_FIFO_MIN); |
145 | wmb(); |
141 | vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); |
Line 146... | Line -... | ||
146 | iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD); |
- | |
147 | iowrite32(min, fifo_mem + SVGA_FIFO_STOP); |
142 | wmb(); |
148 | iowrite32(0, fifo_mem + SVGA_FIFO_BUSY); |
143 | vmw_mmio_write(min, fifo_mem + SVGA_FIFO_NEXT_CMD); |
Line 149... | Line 144... | ||
149 | mb(); |
144 | vmw_mmio_write(min, fifo_mem + SVGA_FIFO_STOP); |
150 | 145 | vmw_mmio_write(0, fifo_mem + SVGA_FIFO_BUSY); |
|
151 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); |
146 | mb(); |
Line 152... | Line 147... | ||
152 | mutex_unlock(&dev_priv->hw_mutex); |
147 | |
153 | - | ||
154 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
148 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); |
155 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
- | |
156 | fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); |
149 | |
157 | - | ||
158 | DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n", |
- | |
159 | (unsigned int) max, |
150 | max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); |
160 | (unsigned int) min, |
151 | min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); |
Line 161... | Line 152... | ||
161 | (unsigned int) fifo->capabilities); |
152 | fifo->capabilities = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES); |
162 | 153 | ||
163 | atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); |
154 | DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n", |
164 | iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); |
- | |
165 | vmw_marker_queue_init(&fifo->marker_queue); |
- | |
Line 166... | Line -... | ||
166 | - | ||
167 | int ret = 0; //vmw_fifo_send_fence(dev_priv, &dummy); |
155 | (unsigned int) max, |
- | 156 | (unsigned int) min, |
|
- | 157 | (unsigned int) fifo->capabilities); |
|
Line 168... | Line 158... | ||
168 | return ret; |
158 | |
Line 169... | Line 159... | ||
169 | } |
159 | atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); |
170 | 160 | vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); |
|
171 | void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) |
161 | vmw_marker_queue_init(&fifo->marker_queue); |
172 | { |
162 | |
173 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
163 | return 0; |
174 | 164 | } |
|
Line 175... | Line -... | ||
175 | mutex_lock(&dev_priv->hw_mutex); |
- | |
176 | 165 | ||
Line 177... | Line 166... | ||
177 | if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) { |
166 | void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) |
178 | iowrite32(1, fifo_mem + SVGA_FIFO_BUSY); |
167 | { |
179 | vmw_write(dev_priv, SVGA_REG_SYNC, reason); |
168 | u32 *fifo_mem = dev_priv->mmio_virt; |
Line 214... | Line 203... | ||
214 | } |
203 | } |
215 | } |
204 | } |
Line 216... | Line 205... | ||
216 | 205 | ||
217 | static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) |
206 | static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) |
218 | { |
207 | { |
219 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
208 | u32 *fifo_mem = dev_priv->mmio_virt; |
220 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
209 | uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); |
221 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
210 | uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); |
222 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
211 | uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); |
Line 223... | Line 212... | ||
223 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); |
212 | uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP); |
224 | 213 | ||
Line 225... | Line 214... | ||
225 | return ((max - next_cmd) + (stop - min) <= bytes); |
214 | return ((max - next_cmd) + (stop - min) <= bytes); |
Line 257... | Line 246... | ||
257 | static int vmw_fifo_wait(struct vmw_private *dev_priv, |
246 | static int vmw_fifo_wait(struct vmw_private *dev_priv, |
258 | uint32_t bytes, bool interruptible, |
247 | uint32_t bytes, bool interruptible, |
259 | unsigned long timeout) |
248 | unsigned long timeout) |
260 | { |
249 | { |
261 | long ret = 1L; |
250 | long ret = 1L; |
262 | unsigned long irq_flags; |
- | |
Line 263... | Line 251... | ||
263 | 251 | ||
264 | if (likely(!vmw_fifo_is_full(dev_priv, bytes))) |
252 | if (likely(!vmw_fifo_is_full(dev_priv, bytes))) |
Line 265... | Line 253... | ||
265 | return 0; |
253 | return 0; |
266 | 254 | ||
267 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL); |
255 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL); |
268 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) |
256 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) |
Line 269... | Line -... | ||
269 | return vmw_fifo_wait_noirq(dev_priv, bytes, |
- | |
270 | interruptible, timeout); |
- | |
271 | - | ||
272 | mutex_lock(&dev_priv->hw_mutex); |
- | |
273 | if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) { |
- | |
274 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
257 | return vmw_fifo_wait_noirq(dev_priv, bytes, |
275 | outl(SVGA_IRQFLAG_FIFO_PROGRESS, |
- | |
276 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
- | |
277 | dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS; |
- | |
278 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
258 | interruptible, timeout); |
Line 279... | Line 259... | ||
279 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
259 | |
280 | } |
260 | vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS, |
281 | mutex_unlock(&dev_priv->hw_mutex); |
261 | &dev_priv->fifo_queue_waiters); |
282 | 262 | ||
Line 292... | Line 272... | ||
292 | if (unlikely(ret == 0)) |
272 | if (unlikely(ret == 0)) |
293 | ret = -EBUSY; |
273 | ret = -EBUSY; |
294 | else if (likely(ret > 0)) |
274 | else if (likely(ret > 0)) |
295 | ret = 0; |
275 | ret = 0; |
Line 296... | Line -... | ||
296 | - | ||
297 | mutex_lock(&dev_priv->hw_mutex); |
- | |
298 | if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) { |
- | |
299 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
276 | |
300 | dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS; |
- | |
301 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
- | |
302 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
- | |
303 | } |
277 | vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS, |
Line 304... | Line 278... | ||
304 | mutex_unlock(&dev_priv->hw_mutex); |
278 | &dev_priv->fifo_queue_waiters); |
305 | 279 | ||
Line 306... | Line 280... | ||
306 | return ret; |
280 | return ret; |
Line 314... | Line 288... | ||
314 | * available fifo space. |
288 | * available fifo space. |
315 | * |
289 | * |
316 | * Returns: |
290 | * Returns: |
317 | * Pointer to the fifo, or null on error (possible hardware hang). |
291 | * Pointer to the fifo, or null on error (possible hardware hang). |
318 | */ |
292 | */ |
319 | void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) |
293 | static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv, |
- | 294 | uint32_t bytes) |
|
320 | { |
295 | { |
321 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
296 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
322 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
297 | u32 *fifo_mem = dev_priv->mmio_virt; |
323 | uint32_t max; |
298 | uint32_t max; |
324 | uint32_t min; |
299 | uint32_t min; |
325 | uint32_t next_cmd; |
300 | uint32_t next_cmd; |
326 | uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
301 | uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
327 | int ret; |
302 | int ret; |
Line 328... | Line 303... | ||
328 | 303 | ||
329 | mutex_lock(&fifo_state->fifo_mutex); |
304 | mutex_lock(&fifo_state->fifo_mutex); |
330 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
305 | max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); |
331 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
306 | min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); |
Line 332... | Line 307... | ||
332 | next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
307 | next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); |
333 | 308 | ||
Line 334... | Line 309... | ||
334 | if (unlikely(bytes >= (max - min))) |
309 | if (unlikely(bytes >= (max - min))) |
335 | goto out_err; |
310 | goto out_err; |
Line 336... | Line 311... | ||
336 | 311 | ||
Line 337... | Line 312... | ||
337 | BUG_ON(fifo_state->reserved_size != 0); |
312 | BUG_ON(fifo_state->reserved_size != 0); |
338 | BUG_ON(fifo_state->dynamic_buffer != NULL); |
313 | BUG_ON(fifo_state->dynamic_buffer != NULL); |
339 | 314 | ||
340 | fifo_state->reserved_size = bytes; |
315 | fifo_state->reserved_size = bytes; |
Line 341... | Line 316... | ||
341 | 316 | ||
342 | while (1) { |
317 | while (1) { |
Line 372... | Line 347... | ||
372 | if (reserve_in_place) { |
347 | if (reserve_in_place) { |
373 | if (reserveable || bytes <= sizeof(uint32_t)) { |
348 | if (reserveable || bytes <= sizeof(uint32_t)) { |
374 | fifo_state->using_bounce_buffer = false; |
349 | fifo_state->using_bounce_buffer = false; |
Line 375... | Line 350... | ||
375 | 350 | ||
376 | if (reserveable) |
351 | if (reserveable) |
377 | iowrite32(bytes, fifo_mem + |
352 | vmw_mmio_write(bytes, fifo_mem + |
- | 353 | SVGA_FIFO_RESERVED); |
|
378 | SVGA_FIFO_RESERVED); |
354 | return (void __force *) (fifo_mem + |
379 | return fifo_mem + (next_cmd >> 2); |
355 | (next_cmd >> 2)); |
380 | } else { |
356 | } else { |
381 | need_bounce = true; |
357 | need_bounce = true; |
382 | } |
358 | } |
Line 383... | Line 359... | ||
383 | } |
359 | } |
384 | 360 | ||
385 | if (need_bounce) { |
361 | if (need_bounce) { |
386 | fifo_state->using_bounce_buffer = true; |
362 | fifo_state->using_bounce_buffer = true; |
387 | if (bytes < fifo_state->static_buffer_size) |
363 | if (bytes < fifo_state->static_buffer_size) |
388 | return fifo_state->static_buffer; |
364 | return fifo_state->static_buffer; |
389 | else { |
365 | else { |
390 | fifo_state->dynamic_buffer = kmalloc(bytes,0); |
366 | fifo_state->dynamic_buffer = vmalloc(bytes); |
391 | return fifo_state->dynamic_buffer; |
367 | return fifo_state->dynamic_buffer; |
392 | } |
368 | } |
393 | } |
369 | } |
394 | } |
370 | } |
395 | out_err: |
371 | out_err: |
- | 372 | fifo_state->reserved_size = 0; |
|
- | 373 | mutex_unlock(&fifo_state->fifo_mutex); |
|
- | 374 | ||
- | 375 | return NULL; |
|
- | 376 | } |
|
- | 377 | ||
- | 378 | void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes, |
|
- | 379 | int ctx_id) |
|
- | 380 | { |
|
- | 381 | void *ret; |
|
- | 382 | ||
- | 383 | if (dev_priv->cman) |
|
- | 384 | ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes, |
|
- | 385 | ctx_id, false, NULL); |
|
- | 386 | else if (ctx_id == SVGA3D_INVALID_ID) |
|
- | 387 | ret = vmw_local_fifo_reserve(dev_priv, bytes); |
|
- | 388 | else { |
|
- | 389 | WARN(1, "Command buffer has not been allocated.\n"); |
|
- | 390 | ret = NULL; |
|
- | 391 | } |
|
- | 392 | if (IS_ERR_OR_NULL(ret)) { |
|
- | 393 | DRM_ERROR("Fifo reserve failure of %u bytes.\n", |
|
396 | fifo_state->reserved_size = 0; |
394 | (unsigned) bytes); |
397 | mutex_unlock(&fifo_state->fifo_mutex); |
395 | // dump_stack(); |
Line -... | Line 396... | ||
- | 396 | return NULL; |
|
- | 397 | } |
|
- | 398 | ||
398 | return NULL; |
399 | return ret; |
399 | } |
400 | } |
400 | 401 | ||
401 | static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, |
402 | static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, |
402 | __le32 __iomem *fifo_mem, |
403 | u32 *fifo_mem, |
403 | uint32_t next_cmd, |
404 | uint32_t next_cmd, |
404 | uint32_t max, uint32_t min, uint32_t bytes) |
405 | uint32_t max, uint32_t min, uint32_t bytes) |
Line 409... | Line 410... | ||
409 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
410 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
Line 410... | Line 411... | ||
410 | 411 | ||
411 | if (bytes < chunk_size) |
412 | if (bytes < chunk_size) |
Line 412... | Line 413... | ||
412 | chunk_size = bytes; |
413 | chunk_size = bytes; |
413 | 414 | ||
414 | iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED); |
415 | vmw_mmio_write(bytes, fifo_mem + SVGA_FIFO_RESERVED); |
415 | mb(); |
416 | mb(); |
416 | memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size); |
417 | memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size); |
417 | rest = bytes - chunk_size; |
418 | rest = bytes - chunk_size; |
418 | if (rest) |
- | |
419 | memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), |
419 | if (rest) |
Line 420... | Line 420... | ||
420 | rest); |
420 | memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), rest); |
421 | } |
421 | } |
422 | 422 | ||
423 | static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, |
423 | static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, |
424 | __le32 __iomem *fifo_mem, |
424 | u32 *fifo_mem, |
425 | uint32_t next_cmd, |
425 | uint32_t next_cmd, |
426 | uint32_t max, uint32_t min, uint32_t bytes) |
426 | uint32_t max, uint32_t min, uint32_t bytes) |
Line 427... | Line 427... | ||
427 | { |
427 | { |
428 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
428 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
429 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
429 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
430 | 430 | ||
431 | while (bytes > 0) { |
431 | while (bytes > 0) { |
432 | iowrite32(*buffer++, fifo_mem + (next_cmd >> 2)); |
432 | vmw_mmio_write(*buffer++, fifo_mem + (next_cmd >> 2)); |
433 | next_cmd += sizeof(uint32_t); |
433 | next_cmd += sizeof(uint32_t); |
434 | if (unlikely(next_cmd == max)) |
434 | if (unlikely(next_cmd == max)) |
435 | next_cmd = min; |
435 | next_cmd = min; |
436 | mb(); |
436 | mb(); |
437 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
437 | vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
Line 438... | Line 438... | ||
438 | mb(); |
438 | mb(); |
439 | bytes -= sizeof(uint32_t); |
439 | bytes -= sizeof(uint32_t); |
440 | } |
440 | } |
441 | } |
441 | } |
442 | 442 | ||
443 | void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
443 | static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
444 | { |
444 | { |
445 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
445 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
Line -... | Line 446... | ||
- | 446 | u32 *fifo_mem = dev_priv->mmio_virt; |
|
- | 447 | uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); |
|
- | 448 | uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); |
|
- | 449 | uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); |
|
446 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
450 | bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
447 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
451 | |
Line 448... | Line 452... | ||
448 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
452 | if (fifo_state->dx) |
Line 467... | Line 471... | ||
467 | fifo_state->dynamic_buffer = NULL; |
471 | fifo_state->dynamic_buffer = NULL; |
468 | } |
472 | } |
Line 469... | Line 473... | ||
469 | 473 | ||
Line 470... | Line 474... | ||
470 | } |
474 | } |
471 | 475 | ||
472 | // down_write(&fifo_state->rwsem); |
476 | down_write(&fifo_state->rwsem); |
473 | if (fifo_state->using_bounce_buffer || reserveable) { |
477 | if (fifo_state->using_bounce_buffer || reserveable) { |
474 | next_cmd += bytes; |
478 | next_cmd += bytes; |
475 | if (next_cmd >= max) |
479 | if (next_cmd >= max) |
476 | next_cmd -= max - min; |
480 | next_cmd -= max - min; |
477 | mb(); |
481 | mb(); |
Line 478... | Line 482... | ||
478 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
482 | vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
479 | } |
483 | } |
480 | 484 | ||
481 | if (reserveable) |
485 | if (reserveable) |
482 | iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); |
486 | vmw_mmio_write(0, fifo_mem + SVGA_FIFO_RESERVED); |
483 | mb(); |
487 | mb(); |
484 | // up_write(&fifo_state->rwsem); |
488 | up_write(&fifo_state->rwsem); |
Line -... | Line 489... | ||
- | 489 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
|
- | 490 | mutex_unlock(&fifo_state->fifo_mutex); |
|
- | 491 | } |
|
- | 492 | ||
- | 493 | void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
|
- | 494 | { |
|
- | 495 | if (dev_priv->cman) |
|
- | 496 | vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false); |
|
- | 497 | else |
|
- | 498 | vmw_local_fifo_commit(dev_priv, bytes); |
|
- | 499 | } |
|
- | 500 | ||
- | 501 | ||
- | 502 | /** |
|
- | 503 | * vmw_fifo_commit_flush - Commit fifo space and flush any buffered commands. |
|
- | 504 | * |
|
- | 505 | * @dev_priv: Pointer to device private structure. |
|
- | 506 | * @bytes: Number of bytes to commit. |
|
- | 507 | */ |
|
- | 508 | void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes) |
|
- | 509 | { |
|
- | 510 | if (dev_priv->cman) |
|
- | 511 | vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true); |
|
- | 512 | else |
|
- | 513 | vmw_local_fifo_commit(dev_priv, bytes); |
|
- | 514 | } |
|
- | 515 | ||
- | 516 | /** |
|
- | 517 | * vmw_fifo_flush - Flush any buffered commands and make sure command processing |
|
- | 518 | * starts. |
|
- | 519 | * |
|
- | 520 | * @dev_priv: Pointer to device private structure. |
|
- | 521 | * @interruptible: Whether to wait interruptible if function needs to sleep. |
|
- | 522 | */ |
|
- | 523 | int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible) |
|
- | 524 | { |
|
- | 525 | might_sleep(); |
|
- | 526 | ||
- | 527 | if (dev_priv->cman) |
|
- | 528 | return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible); |
|
485 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
529 | else |
486 | mutex_unlock(&fifo_state->fifo_mutex); |
530 | return 0; |
487 | } |
531 | } |
488 | 532 | ||
489 | int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) |
533 | int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) |
490 | { |
534 | { |
491 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
535 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
Line 492... | Line 536... | ||
492 | struct svga_fifo_cmd_fence *cmd_fence; |
536 | struct svga_fifo_cmd_fence *cmd_fence; |
493 | void *fm; |
537 | u32 *fm; |
494 | int ret = 0; |
538 | int ret = 0; |
495 | uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence); |
539 | uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence); |
Line 516... | Line 560... | ||
516 | 560 | ||
517 | vmw_fifo_commit(dev_priv, 0); |
561 | vmw_fifo_commit(dev_priv, 0); |
518 | return 0; |
562 | return 0; |
Line 519... | Line 563... | ||
519 | } |
563 | } |
520 | 564 | ||
521 | *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE); |
- | |
522 | cmd_fence = (struct svga_fifo_cmd_fence *) |
- | |
523 | ((unsigned long)fm + sizeof(__le32)); |
565 | *fm++ = SVGA_CMD_FENCE; |
524 | 566 | cmd_fence = (struct svga_fifo_cmd_fence *) fm; |
|
525 | iowrite32(*seqno, &cmd_fence->fence); |
567 | cmd_fence->fence = *seqno; |
526 | vmw_fifo_commit(dev_priv, bytes); |
568 | vmw_fifo_commit_flush(dev_priv, bytes); |
Line 527... | Line 569... | ||
527 | (void) vmw_marker_push(&fifo_state->marker_queue, *seqno); |
569 | (void) vmw_marker_push(&fifo_state->marker_queue, *seqno); |
528 | vmw_update_seqno(dev_priv, fifo_state); |
570 | vmw_update_seqno(dev_priv, fifo_state); |
Line 547... | Line 589... | ||
547 | * A query wait without a preceding query end will |
589 | * A query wait without a preceding query end will |
548 | * actually finish all queries for this cid |
590 | * actually finish all queries for this cid |
549 | * without writing to the query result structure. |
591 | * without writing to the query result structure. |
550 | */ |
592 | */ |
Line 551... | Line 593... | ||
551 | 593 | ||
552 | struct ttm_buffer_object *bo = dev_priv->dummy_query_bo; |
594 | struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; |
553 | struct { |
595 | struct { |
554 | SVGA3dCmdHeader header; |
596 | SVGA3dCmdHeader header; |
555 | SVGA3dCmdWaitForQuery body; |
597 | SVGA3dCmdWaitForQuery body; |
Line 596... | Line 638... | ||
596 | * A query wait without a preceding query end will |
638 | * A query wait without a preceding query end will |
597 | * actually finish all queries for this cid |
639 | * actually finish all queries for this cid |
598 | * without writing to the query result structure. |
640 | * without writing to the query result structure. |
599 | */ |
641 | */ |
Line 600... | Line 642... | ||
600 | 642 | ||
601 | struct ttm_buffer_object *bo = dev_priv->dummy_query_bo; |
643 | struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; |
602 | struct { |
644 | struct { |
603 | SVGA3dCmdHeader header; |
645 | SVGA3dCmdHeader header; |
604 | SVGA3dCmdWaitForGBQuery body; |
646 | SVGA3dCmdWaitForGBQuery body; |
Line 649... | Line 691... | ||
649 | if (dev_priv->has_mob) |
691 | if (dev_priv->has_mob) |
650 | return vmw_fifo_emit_dummy_gb_query(dev_priv, cid); |
692 | return vmw_fifo_emit_dummy_gb_query(dev_priv, cid); |
Line 651... | Line 693... | ||
651 | 693 | ||
652 | return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid); |
694 | return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid); |
- | 695 | } |
|
- | 696 | ||
- | 697 | void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) |
|
- | 698 | { |
|
- | 699 | return vmw_fifo_reserve_dx(dev_priv, bytes, SVGA3D_INVALID_ID); |