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Rev 4570 | Rev 5078 | ||
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Line 104... | Line 104... | ||
104 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
104 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
105 | uint32_t max; |
105 | uint32_t max; |
106 | uint32_t min; |
106 | uint32_t min; |
107 | uint32_t dummy; |
107 | uint32_t dummy; |
Line 108... | Line -... | ||
108 | - | ||
109 | ENTER(); |
- | |
110 | 108 | ||
111 | fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; |
109 | fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; |
112 | fifo->static_buffer = KernelAlloc(fifo->static_buffer_size); |
110 | fifo->static_buffer = KernelAlloc(fifo->static_buffer_size); |
113 | if (unlikely(fifo->static_buffer == NULL)) |
111 | if (unlikely(fifo->static_buffer == NULL)) |
Line 165... | Line 163... | ||
165 | atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); |
163 | atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); |
166 | iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); |
164 | iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); |
167 | vmw_marker_queue_init(&fifo->marker_queue); |
165 | vmw_marker_queue_init(&fifo->marker_queue); |
Line 168... | Line 166... | ||
168 | 166 | ||
169 | int ret = 0; //vmw_fifo_send_fence(dev_priv, &dummy); |
- | |
170 | LEAVE(); |
167 | int ret = 0; //vmw_fifo_send_fence(dev_priv, &dummy); |
171 | return ret; |
168 | return ret; |
Line 172... | Line 169... | ||
172 | } |
169 | } |
173 | 170 | ||
Line 231... | Line 228... | ||
231 | static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv, |
228 | static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv, |
232 | uint32_t bytes, bool interruptible, |
229 | uint32_t bytes, bool interruptible, |
233 | unsigned long timeout) |
230 | unsigned long timeout) |
234 | { |
231 | { |
235 | int ret = 0; |
232 | int ret = 0; |
236 | unsigned long end_jiffies = GetTimerTicks() + timeout; |
233 | unsigned long end_jiffies = jiffies + timeout; |
237 | // DEFINE_WAIT(__wait); |
234 | // DEFINE_WAIT(__wait); |
Line 238... | Line 235... | ||
238 | 235 | ||
Line 239... | Line 236... | ||
239 | DRM_INFO("Fifo wait noirq.\n"); |
236 | DRM_INFO("Fifo wait noirq.\n"); |
240 | 237 | ||
241 | for (;;) { |
238 | for (;;) { |
242 | // prepare_to_wait(&dev_priv->fifo_queue, &__wait, |
239 | // prepare_to_wait(&dev_priv->fifo_queue, &__wait, |
243 | // (interruptible) ? |
240 | // (interruptible) ? |
244 | // TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
241 | // TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
245 | if (!vmw_fifo_is_full(dev_priv, bytes)) |
242 | if (!vmw_fifo_is_full(dev_priv, bytes)) |
246 | break; |
243 | break; |
247 | if (time_after_eq(GetTimerTicks(), end_jiffies)) { |
244 | if (time_after_eq(jiffies, end_jiffies)) { |
248 | ret = -EBUSY; |
245 | ret = -EBUSY; |
249 | DRM_ERROR("SVGA device lockup.\n"); |
246 | DRM_ERROR("SVGA device lockup.\n"); |
250 | break; |
247 | break; |
Line 409... | Line 406... | ||
409 | uint32_t chunk_size = max - next_cmd; |
406 | uint32_t chunk_size = max - next_cmd; |
410 | uint32_t rest; |
407 | uint32_t rest; |
411 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
408 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
412 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
409 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
Line 413... | Line -... | ||
413 | - | ||
414 | ENTER(); |
- | |
415 | 410 | ||
416 | if (bytes < chunk_size) |
411 | if (bytes < chunk_size) |
Line 417... | Line 412... | ||
417 | chunk_size = bytes; |
412 | chunk_size = bytes; |
418 | 413 | ||
419 | iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED); |
414 | iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED); |
420 | mb(); |
415 | mb(); |
421 | memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size); |
416 | memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size); |
422 | rest = bytes - chunk_size; |
417 | rest = bytes - chunk_size; |
423 | if (rest) |
418 | if (rest) |
424 | memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), |
- | |
425 | rest); |
- | |
426 | LEAVE(); |
419 | memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), |
Line 427... | Line 420... | ||
427 | 420 | rest); |
|
428 | } |
421 | } |
429 | 422 | ||
430 | static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, |
423 | static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, |
431 | __le32 __iomem *fifo_mem, |
424 | __le32 __iomem *fifo_mem, |
432 | uint32_t next_cmd, |
425 | uint32_t next_cmd, |
433 | uint32_t max, uint32_t min, uint32_t bytes) |
426 | uint32_t max, uint32_t min, uint32_t bytes) |
434 | { |
- | |
Line 435... | Line 427... | ||
435 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
427 | { |
436 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
428 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
437 | ENTER(); |
429 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
438 | 430 | ||
Line 444... | Line 436... | ||
444 | mb(); |
436 | mb(); |
445 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
437 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
446 | mb(); |
438 | mb(); |
447 | bytes -= sizeof(uint32_t); |
439 | bytes -= sizeof(uint32_t); |
448 | } |
440 | } |
449 | LEAVE(); |
- | |
450 | } |
441 | } |
Line 451... | Line 442... | ||
451 | 442 | ||
452 | void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
443 | void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
453 | { |
444 | { |
Line 456... | Line 447... | ||
456 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
447 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
457 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
448 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
458 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
449 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
459 | bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
450 | bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
Line 460... | Line -... | ||
460 | - | ||
461 | // ENTER(); |
- | |
462 | 451 | ||
463 | BUG_ON((bytes & 3) != 0); |
452 | BUG_ON((bytes & 3) != 0); |
Line 464... | Line 453... | ||
464 | BUG_ON(bytes > fifo_state->reserved_size); |
453 | BUG_ON(bytes > fifo_state->reserved_size); |
Line 493... | Line 482... | ||
493 | iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); |
482 | iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); |
494 | mb(); |
483 | mb(); |
495 | // up_write(&fifo_state->rwsem); |
484 | // up_write(&fifo_state->rwsem); |
496 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
485 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
497 | mutex_unlock(&fifo_state->fifo_mutex); |
486 | mutex_unlock(&fifo_state->fifo_mutex); |
498 | - | ||
499 | // LEAVE(); |
- | |
500 | } |
487 | } |
Line 501... | Line 488... | ||
501 | 488 | ||
502 | int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) |
489 | int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) |
503 | { |
490 | { |