WebSVN – Kolibri OS – Diff – /drivers/video/drm/vmwgfx/vmwgfx_drv.c


/**************************************************************************
 *
 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 **************************************************************************/
#include 
 
#include 
#include "vmwgfx_drv.h"
#include 
#include 
#include 
//#include 
#include 
 
#define VMWGFX_DRIVER_NAME "vmwgfx"
#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
#define VMWGFX_CHIP_SVGAII 0
#define VMW_FB_RESERVATION 0
 
#define VMW_MIN_INITIAL_WIDTH 800
#define VMW_MIN_INITIAL_HEIGHT 600
 
#if 0
/**
 * Fully encoded drm commands. Might move to vmw_drm.h
 */
 
#define DRM_IOCTL_VMW_GET_PARAM					\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,		\
		 struct drm_vmw_getparam_arg)
#define DRM_IOCTL_VMW_ALLOC_DMABUF				\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,	\
		union drm_vmw_alloc_dmabuf_arg)
#define DRM_IOCTL_VMW_UNREF_DMABUF				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,	\
		struct drm_vmw_unref_dmabuf_arg)
#define DRM_IOCTL_VMW_CURSOR_BYPASS				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,	\
		 struct drm_vmw_cursor_bypass_arg)
 
#define DRM_IOCTL_VMW_CONTROL_STREAM				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,	\
		 struct drm_vmw_control_stream_arg)
#define DRM_IOCTL_VMW_CLAIM_STREAM				\
	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,	\
		 struct drm_vmw_stream_arg)
#define DRM_IOCTL_VMW_UNREF_STREAM				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,	\
		 struct drm_vmw_stream_arg)
 
#define DRM_IOCTL_VMW_CREATE_CONTEXT				\
	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,	\
		struct drm_vmw_context_arg)
#define DRM_IOCTL_VMW_UNREF_CONTEXT				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,	\
		struct drm_vmw_context_arg)
#define DRM_IOCTL_VMW_CREATE_SURFACE				\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,	\
		 union drm_vmw_surface_create_arg)
#define DRM_IOCTL_VMW_UNREF_SURFACE				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,	\
		 struct drm_vmw_surface_arg)
#define DRM_IOCTL_VMW_REF_SURFACE				\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,	\
		 union drm_vmw_surface_reference_arg)
#define DRM_IOCTL_VMW_EXECBUF					\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,		\
		struct drm_vmw_execbuf_arg)
#define DRM_IOCTL_VMW_GET_3D_CAP				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,		\
		 struct drm_vmw_get_3d_cap_arg)
#define DRM_IOCTL_VMW_FENCE_WAIT				\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,		\
		 struct drm_vmw_fence_wait_arg)
#define DRM_IOCTL_VMW_FENCE_SIGNALED				\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,	\
		 struct drm_vmw_fence_signaled_arg)
#define DRM_IOCTL_VMW_FENCE_UNREF				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,		\
		 struct drm_vmw_fence_arg)
#define DRM_IOCTL_VMW_FENCE_EVENT				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,		\
		 struct drm_vmw_fence_event_arg)
#define DRM_IOCTL_VMW_PRESENT					\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,		\
		 struct drm_vmw_present_arg)
#define DRM_IOCTL_VMW_PRESENT_READBACK				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,	\
		 struct drm_vmw_present_readback_arg)
#define DRM_IOCTL_VMW_UPDATE_LAYOUT				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,	\
		 struct drm_vmw_update_layout_arg)
#define DRM_IOCTL_VMW_CREATE_SHADER				\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,	\
		 struct drm_vmw_shader_create_arg)
#define DRM_IOCTL_VMW_UNREF_SHADER				\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,	\
		 struct drm_vmw_shader_arg)
#define DRM_IOCTL_VMW_GB_SURFACE_CREATE				\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,	\
		 union drm_vmw_gb_surface_create_arg)
#define DRM_IOCTL_VMW_GB_SURFACE_REF				\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,	\
		 union drm_vmw_gb_surface_reference_arg)
#define DRM_IOCTL_VMW_SYNCCPU					\
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,		\
		 struct drm_vmw_synccpu_arg)
 
/**
 * The core DRM version of this macro doesn't account for
 * DRM_COMMAND_BASE.
 */
 
#define VMW_IOCTL_DEF(ioctl, func, flags) \
  [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
 
/**
 * Ioctl definitions.
 */
 
static const struct drm_ioctl_desc vmw_ioctls[] = {
	VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
		      vmw_kms_cursor_bypass_ioctl,
		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 
	VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 
	VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
		      vmw_fence_obj_signaled_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_FENCE_EVENT,
		      vmw_fence_event_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
 
	/* these allow direct access to the framebuffers mark as master only */
	VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
		      DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
		      vmw_present_readback_ioctl,
		      DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
		      vmw_kms_update_layout_ioctl,
		      DRM_MASTER | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_CREATE_SHADER,
		      vmw_shader_define_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_UNREF_SHADER,
		      vmw_shader_destroy_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
		      vmw_gb_surface_define_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
		      vmw_gb_surface_reference_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
	VMW_IOCTL_DEF(VMW_SYNCCPU,
		      vmw_user_dmabuf_synccpu_ioctl,
		      DRM_AUTH | DRM_UNLOCKED),
};
#endif
 
static struct pci_device_id vmw_pci_id_list[] = {
	{0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
	{0, 0, 0}
};
 
static int enable_fbdev = 1;
static int vmw_force_iommu;
static int vmw_restrict_iommu;
static int vmw_force_coherent;
static int vmw_restrict_dma_mask;
 
static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
static void vmw_master_init(struct vmw_master *);
 
MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
module_param_named(enable_fbdev, enable_fbdev, int, 0600);
MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
module_param_named(force_coherent, vmw_force_coherent, int, 0600);
MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
 
 
static void vmw_print_capabilities(uint32_t capabilities)
{
	DRM_INFO("Capabilities:\n");
	if (capabilities & SVGA_CAP_RECT_COPY)
		DRM_INFO("  Rect copy.\n");
	if (capabilities & SVGA_CAP_CURSOR)
		DRM_INFO("  Cursor.\n");
	if (capabilities & SVGA_CAP_CURSOR_BYPASS)
		DRM_INFO("  Cursor bypass.\n");
	if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
		DRM_INFO("  Cursor bypass 2.\n");
	if (capabilities & SVGA_CAP_8BIT_EMULATION)
		DRM_INFO("  8bit emulation.\n");
	if (capabilities & SVGA_CAP_ALPHA_CURSOR)
		DRM_INFO("  Alpha cursor.\n");
	if (capabilities & SVGA_CAP_3D)
		DRM_INFO("  3D.\n");
	if (capabilities & SVGA_CAP_EXTENDED_FIFO)
		DRM_INFO("  Extended Fifo.\n");
	if (capabilities & SVGA_CAP_MULTIMON)
		DRM_INFO("  Multimon.\n");
	if (capabilities & SVGA_CAP_PITCHLOCK)
		DRM_INFO("  Pitchlock.\n");
	if (capabilities & SVGA_CAP_IRQMASK)
		DRM_INFO("  Irq mask.\n");
	if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
		DRM_INFO("  Display Topology.\n");
	if (capabilities & SVGA_CAP_GMR)
		DRM_INFO("  GMR.\n");
	if (capabilities & SVGA_CAP_TRACES)
		DRM_INFO("  Traces.\n");
	if (capabilities & SVGA_CAP_GMR2)
		DRM_INFO("  GMR2.\n");
	if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
		DRM_INFO("  Screen Object 2.\n");
	if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
		DRM_INFO("  Command Buffers.\n");
	if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
		DRM_INFO("  Command Buffers 2.\n");
	if (capabilities & SVGA_CAP_GBOBJECTS)
		DRM_INFO("  Guest Backed Resources.\n");
}
 
 
/**
 
 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 *
 * @dev_priv: A device private structure.
 *
 * This function creates a small buffer object that holds the query
 * result for dummy queries emitted as query barriers.
 * The function will then map the first page and initialize a pending
 * occlusion query result structure, Finally it will unmap the buffer.
 * No interruptible waits are done within this function.
 
 *
 * Returns an error if bo creation or initialization fails.
 */
static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
{
	int ret;
	struct ttm_buffer_object *bo;
	struct ttm_bo_kmap_obj map;
	volatile SVGA3dQueryResult *result;
	bool dummy;
 
 
 
 
 
 
 
 
 
 
 
	/*
	 * Create the bo as pinned, so that a tryreserve will
	 * immediately succeed. This is because we're the only
	 * user of the bo currently.
	 */
	ret = ttm_bo_create(&dev_priv->bdev,
			     PAGE_SIZE,
			     ttm_bo_type_device,
			    &vmw_sys_ne_placement,
			     0, false, NULL,
			    &bo);
 
	if (unlikely(ret != 0))
		return ret;
 
	ret = ttm_bo_reserve(bo, false, true, false, 0);
	BUG_ON(ret != 0);
 
	ret = ttm_bo_kmap(bo, 0, 1, &map);
	if (likely(ret == 0)) {
		result = ttm_kmap_obj_virtual(&map, &dummy);
		result->totalSize = sizeof(*result);
		result->state = SVGA3D_QUERYSTATE_PENDING;
		result->result32 = 0xff;
		ttm_bo_kunmap(&map);
 
 
 
 
	}
	vmw_bo_pin(bo, false);
	ttm_bo_unreserve(bo);
 
	if (unlikely(ret != 0)) {
		DRM_ERROR("Dummy query buffer map failed.\n");
		ttm_bo_unref(&bo);
	} else
 
 
 
 
 
 
 
 
 
 
 
 
 
 
		dev_priv->dummy_query_bo = bo;
 
 
 
 
 
 
	return ret;
}
 
static int vmw_request_device(struct vmw_private *dev_priv)
{
	int ret;
    ENTER();
 
	ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
	if (unlikely(ret != 0)) {
		DRM_ERROR("Unable to initialize FIFO.\n");
		return ret;
	}
//   vmw_fence_fifo_up(dev_priv->fman);
//   ret = vmw_dummy_query_bo_create(dev_priv);
//   if (unlikely(ret != 0))
//       goto out_no_query_bo;
//   vmw_dummy_query_bo_prepare(dev_priv);
 
    LEAVE();
 
	return 0;
 
out_no_query_bo:
	vmw_fence_fifo_down(dev_priv->fman);
	vmw_fifo_release(dev_priv, &dev_priv->fifo);
	return ret;
}
 
static void vmw_release_device(struct vmw_private *dev_priv)
{
	/*
	 * Previous destructions should've released
	 * the pinned bo.
	 */
 
	BUG_ON(dev_priv->pinned_bo != NULL);
 
	ttm_bo_unref(&dev_priv->dummy_query_bo);
	vmw_fence_fifo_down(dev_priv->fman);
	vmw_fifo_release(dev_priv, &dev_priv->fifo);
}
 
 
/**
 * Increase the 3d resource refcount.
 * If the count was prevously zero, initialize the fifo, switching to svga
 * mode. Note that the master holds a ref as well, and may request an
 * explicit switch to svga mode if fb is not running, using @unhide_svga.
 */
int vmw_3d_resource_inc(struct vmw_private *dev_priv,
			bool unhide_svga)
{
	int ret = 0;
 
    ENTER();
 
	mutex_lock(&dev_priv->release_mutex);
	if (unlikely(dev_priv->num_3d_resources++ == 0)) {
        ret = vmw_request_device(dev_priv);
		if (unlikely(ret != 0))
			--dev_priv->num_3d_resources;
	} else if (unhide_svga) {
		mutex_lock(&dev_priv->hw_mutex);
		vmw_write(dev_priv, SVGA_REG_ENABLE,
			  vmw_read(dev_priv, SVGA_REG_ENABLE) &
			  ~SVGA_REG_ENABLE_HIDE);
		mutex_unlock(&dev_priv->hw_mutex);
	}
 
	mutex_unlock(&dev_priv->release_mutex);
    LEAVE();
	return ret;
}
 
/**
 * Decrease the 3d resource refcount.
 * If the count reaches zero, disable the fifo, switching to vga mode.
 * Note that the master holds a refcount as well, and may request an
 * explicit switch to vga mode when it releases its refcount to account
 * for the situation of an X server vt switch to VGA with 3d resources
 * active.
 */
void vmw_3d_resource_dec(struct vmw_private *dev_priv,
			 bool hide_svga)
{
	int32_t n3d;
 
	mutex_lock(&dev_priv->release_mutex);
	if (unlikely(--dev_priv->num_3d_resources == 0))
		vmw_release_device(dev_priv);
	else if (hide_svga) {
		mutex_lock(&dev_priv->hw_mutex);
		vmw_write(dev_priv, SVGA_REG_ENABLE,
			  vmw_read(dev_priv, SVGA_REG_ENABLE) |
			  SVGA_REG_ENABLE_HIDE);
		mutex_unlock(&dev_priv->hw_mutex);
	}
 
	n3d = (int32_t) dev_priv->num_3d_resources;
	mutex_unlock(&dev_priv->release_mutex);
 
	BUG_ON(n3d < 0);
}
 
/**
 * Sets the initial_[width|height] fields on the given vmw_private.
 *
 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
 * clamping the value to fb_max_[width|height] fields and the
 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 * If the values appear to be invalid, set them to
 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 */
static void vmw_get_initial_size(struct vmw_private *dev_priv)
{
	uint32_t width;
	uint32_t height;
 
	width = vmw_read(dev_priv, SVGA_REG_WIDTH);
	height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
 
	width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
	height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
 
	if (width > dev_priv->fb_max_width ||
	    height > dev_priv->fb_max_height) {
 
		/*
		 * This is a host error and shouldn't occur.
		 */
 
		width = VMW_MIN_INITIAL_WIDTH;
		height = VMW_MIN_INITIAL_HEIGHT;
	}
 
	dev_priv->initial_width = width;
	dev_priv->initial_height = height;
}
 
/**
 * vmw_dma_masks - set required page- and dma masks
 *
 * @dev: Pointer to struct drm-device
 *
 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
 * restriction also for 64-bit systems.
 */
#ifdef CONFIG_INTEL_IOMMU
static int vmw_dma_masks(struct vmw_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
 
	if (intel_iommu_enabled &&
	    (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
		DRM_INFO("Restricting DMA addresses to 44 bits.\n");
		return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
	}
	return 0;
}
#else
static int vmw_dma_masks(struct vmw_private *dev_priv)
{
	return 0;
}
#endif
 
static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
{
	struct vmw_private *dev_priv;
	int ret;
	uint32_t svga_id;
	enum vmw_res_type i;
	bool refuse_dma = false;
 
 
    ENTER();
 
	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
	if (unlikely(dev_priv == NULL)) {
		DRM_ERROR("Failed allocating a device private struct.\n");
		return -ENOMEM;
	}
 
	pci_set_master(dev->pdev);
 
	dev_priv->dev = dev;
	dev_priv->vmw_chipset = chipset;
	dev_priv->last_read_seqno = (uint32_t) -100;
	mutex_init(&dev_priv->hw_mutex);
	mutex_init(&dev_priv->cmdbuf_mutex);
	mutex_init(&dev_priv->release_mutex);
	mutex_init(&dev_priv->binding_mutex);
	rwlock_init(&dev_priv->resource_lock);
 
	for (i = vmw_res_context; i < vmw_res_max; ++i) {
		idr_init(&dev_priv->res_idr[i]);
		INIT_LIST_HEAD(&dev_priv->res_lru[i]);
	}
 
	mutex_init(&dev_priv->init_mutex);
	init_waitqueue_head(&dev_priv->fence_queue);
	init_waitqueue_head(&dev_priv->fifo_queue);
	dev_priv->fence_queue_waiters = 0;
	atomic_set(&dev_priv->fifo_queue_waiters, 0);
 
	dev_priv->used_memory_size = 0;
 
	dev_priv->io_start = pci_resource_start(dev->pdev, 0);
	dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
	dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 
    printk("io: %x vram: %x mmio: %x\n",dev_priv->io_start,
            dev_priv->vram_start,dev_priv->mmio_start);
 
	dev_priv->enable_fb = enable_fbdev;
 
	mutex_lock(&dev_priv->hw_mutex);
 
    vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
	svga_id = vmw_read(dev_priv, SVGA_REG_ID);
	if (svga_id != SVGA_ID_2) {
		ret = -ENOSYS;
		DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
		mutex_unlock(&dev_priv->hw_mutex);
		goto out_err0;
	}
 
	dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
//   ret = vmw_dma_select_mode(dev_priv);
//   if (unlikely(ret != 0)) {
//       DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
//       refuse_dma = true;
//   }
 
	dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
	dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
	dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
	dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 
	vmw_get_initial_size(dev_priv);
 
 
 
 
	if (dev_priv->capabilities & SVGA_CAP_GMR2) {
		dev_priv->max_gmr_ids =
 
 
			vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
		dev_priv->max_gmr_pages =
			vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
		dev_priv->memory_size =
			vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
		dev_priv->memory_size -= dev_priv->vram_size;
	} else {
		/*
		 * An arbitrary limit of 512MiB on surface
		 * memory. But all HWV8 hardware supports GMR2.
		 */
		dev_priv->memory_size = 512*1024*1024;
	}
	dev_priv->max_mob_pages = 0;
	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
		uint64_t mem_size =
			vmw_read(dev_priv,
				 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
 
		dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
		dev_priv->prim_bb_mem =
			vmw_read(dev_priv,
				 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
	} else
		dev_priv->prim_bb_mem = dev_priv->vram_size;
 
	ret = vmw_dma_masks(dev_priv);
	if (unlikely(ret != 0)) {
		mutex_unlock(&dev_priv->hw_mutex);
		goto out_err0;
	}
 
	if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
		dev_priv->prim_bb_mem = dev_priv->vram_size;
 
	mutex_unlock(&dev_priv->hw_mutex);
 
	vmw_print_capabilities(dev_priv->capabilities);
 
	if (dev_priv->capabilities & SVGA_CAP_GMR2) {
		DRM_INFO("Max GMR ids is %u\n",
 
 
 
 
			 (unsigned)dev_priv->max_gmr_ids);
		DRM_INFO("Max number of GMR pages is %u\n",
			 (unsigned)dev_priv->max_gmr_pages);
		DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
			 (unsigned)dev_priv->memory_size / 1024);
	}
	DRM_INFO("Maximum display memory size is %u kiB\n",
		 dev_priv->prim_bb_mem / 1024);
	DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
		 dev_priv->vram_start, dev_priv->vram_size / 1024);
	DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
		 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 
	ret = vmw_ttm_global_init(dev_priv);
	if (unlikely(ret != 0))
		goto out_err0;
 
 
	vmw_master_init(&dev_priv->fbdev_master);
	dev_priv->active_master = &dev_priv->fbdev_master;
 
 
	ret = ttm_bo_device_init(&dev_priv->bdev,
				 dev_priv->bo_global_ref.ref.object,
				 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
				 false);
	if (unlikely(ret != 0)) {
		DRM_ERROR("Failed initializing TTM buffer object driver.\n");
		goto out_err1;
	}
 
	ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
			     (dev_priv->vram_size >> PAGE_SHIFT));
	if (unlikely(ret != 0)) {
		DRM_ERROR("Failed initializing memory manager for VRAM.\n");
		goto out_err2;
	}
 
	dev_priv->has_gmr = true;
	if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
	    refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
					 VMW_PL_GMR) != 0) {
		DRM_INFO("No GMR memory available. "
			 "Graphics memory resources are very limited.\n");
		dev_priv->has_gmr = false;
	}
 
	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
		dev_priv->has_mob = true;
		if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
				   VMW_PL_MOB) != 0) {
			DRM_INFO("No MOB memory available. "
				 "3D will be disabled.\n");
			dev_priv->has_mob = false;
		}
	}
	dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
					 dev_priv->mmio_size);
 
	if (unlikely(dev_priv->mmio_virt == NULL)) {
		ret = -ENOMEM;
		DRM_ERROR("Failed mapping MMIO.\n");
		goto out_err3;
	}
 
	/* Need mmio memory to check for fifo pitchlock cap. */
	if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
	    !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
	    !vmw_fifo_have_pitchlock(dev_priv)) {
		ret = -ENOSYS;
		DRM_ERROR("Hardware has no pitchlock\n");
		goto out_err4;
	}
 
//   dev_priv->tdev = ttm_object_device_init
//       (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
 
//   if (unlikely(dev_priv->tdev == NULL)) {
//       DRM_ERROR("Unable to initialize TTM object management.\n");
//       ret = -ENOMEM;
//       goto out_err4;
//   }
 
	dev->dev_private = dev_priv;
 
#if 0
 
	if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
		ret = drm_irq_install(dev);
		if (ret != 0) {
			DRM_ERROR("Failed installing irq: %d\n", ret);
			goto out_no_irq;
		}
	}
 
	dev_priv->fman = vmw_fence_manager_init(dev_priv);
	if (unlikely(dev_priv->fman == NULL)) {
		ret = -ENOMEM;
		goto out_no_fman;
	}
 
	vmw_kms_save_vga(dev_priv);
#endif
 
	/* Start kms and overlay systems, needs fifo. */
	ret = vmw_kms_init(dev_priv);
	if (unlikely(ret != 0))
		goto out_no_kms;
 
    if (dev_priv->enable_fb) {
       ret = vmw_3d_resource_inc(dev_priv, true);
       if (unlikely(ret != 0))
           goto out_no_fifo;
//       vmw_fb_init(dev_priv);
    }
 
    main_device = dev;
 
    LEAVE();
	return 0;
 
out_no_fifo:
//   vmw_overlay_close(dev_priv);
//   vmw_kms_close(dev_priv);
out_no_kms:
//   vmw_kms_restore_vga(dev_priv);
//   vmw_fence_manager_takedown(dev_priv->fman);
out_no_fman:
//   if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
//       drm_irq_uninstall(dev_priv->dev);
out_no_irq:
//   if (dev_priv->stealth)
//       pci_release_region(dev->pdev, 2);
//   else
//       pci_release_regions(dev->pdev);
out_no_device:
//   ttm_object_device_release(&dev_priv->tdev);
out_err4:
//   iounmap(dev_priv->mmio_virt);
out_err3:
//   arch_phys_wc_del(dev_priv->mmio_mtrr);
//   if (dev_priv->has_gmr)
//       (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
//   (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
out_err2:
//   (void)ttm_bo_device_release(&dev_priv->bdev);
out_err1:
//   vmw_ttm_global_release(dev_priv);
out_err0:
//   for (i = vmw_res_context; i < vmw_res_max; ++i)
//       idr_destroy(&dev_priv->res_idr[i]);
 
	kfree(dev_priv);
	return ret;
}
 
#if 0
static int vmw_driver_unload(struct drm_device *dev)
{
	struct vmw_private *dev_priv = vmw_priv(dev);
	enum vmw_res_type i;
 
	unregister_pm_notifier(&dev_priv->pm_nb);
 
	if (dev_priv->ctx.res_ht_initialized)
		drm_ht_remove(&dev_priv->ctx.res_ht);
	if (dev_priv->ctx.cmd_bounce)
		vfree(dev_priv->ctx.cmd_bounce);
	if (dev_priv->enable_fb) {
		vmw_fb_close(dev_priv);
		vmw_kms_restore_vga(dev_priv);
		vmw_3d_resource_dec(dev_priv, false);
	}
	vmw_kms_close(dev_priv);
	vmw_overlay_close(dev_priv);
	vmw_fence_manager_takedown(dev_priv->fman);
	if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
		drm_irq_uninstall(dev_priv->dev);
	if (dev_priv->stealth)
		pci_release_region(dev->pdev, 2);
	else
		pci_release_regions(dev->pdev);
 
	ttm_object_device_release(&dev_priv->tdev);
	iounmap(dev_priv->mmio_virt);
	arch_phys_wc_del(dev_priv->mmio_mtrr);
	if (dev_priv->has_mob)
		(void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
	if (dev_priv->has_gmr)
		(void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
	(void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
	(void)ttm_bo_device_release(&dev_priv->bdev);
	vmw_ttm_global_release(dev_priv);
 
	for (i = vmw_res_context; i < vmw_res_max; ++i)
		idr_destroy(&dev_priv->res_idr[i]);
 
	kfree(dev_priv);
 
	return 0;
}
 
static void vmw_preclose(struct drm_device *dev,
			 struct drm_file *file_priv)
{
	struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
	struct vmw_private *dev_priv = vmw_priv(dev);
 
	vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
}
 
static void vmw_postclose(struct drm_device *dev,
			 struct drm_file *file_priv)
{
	struct vmw_fpriv *vmw_fp;
 
	vmw_fp = vmw_fpriv(file_priv);
 
	if (vmw_fp->locked_master) {
		struct vmw_master *vmaster =
			vmw_master(vmw_fp->locked_master);
 
		ttm_vt_unlock(&vmaster->lock);
		drm_master_put(&vmw_fp->locked_master);
	}
 
	ttm_object_file_release(&vmw_fp->tfile);
	kfree(vmw_fp);
}
#endif
 
static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
{
	struct vmw_private *dev_priv = vmw_priv(dev);
	struct vmw_fpriv *vmw_fp;
	int ret = -ENOMEM;
 
	vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
	if (unlikely(vmw_fp == NULL))
		return ret;
 
	INIT_LIST_HEAD(&vmw_fp->fence_events);
//   vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
//   if (unlikely(vmw_fp->tfile == NULL))
//       goto out_no_tfile;
 
	file_priv->driver_priv = vmw_fp;
//   dev_priv->bdev.dev_mapping = dev->dev_mapping;
 
	return 0;
 
out_no_tfile:
	kfree(vmw_fp);
	return ret;
}
 
#if 0
static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
			       unsigned long arg)
{
	struct drm_file *file_priv = filp->private_data;
	struct drm_device *dev = file_priv->minor->dev;
	unsigned int nr = DRM_IOCTL_NR(cmd);
 
	/*
	 * Do extra checking on driver private ioctls.
	 */
 
	if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
	    && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
		const struct drm_ioctl_desc *ioctl =
		    &vmw_ioctls[nr - DRM_COMMAND_BASE];
 
		if (unlikely(ioctl->cmd_drv != cmd)) {
			DRM_ERROR("Invalid command format, ioctl %d\n",
				  nr - DRM_COMMAND_BASE);
			return -EINVAL;
		}
	}
 
	return drm_ioctl(filp, cmd, arg);
}
 
static void vmw_lastclose(struct drm_device *dev)
{
	struct drm_crtc *crtc;
	struct drm_mode_set set;
	int ret;
 
	set.x = 0;
	set.y = 0;
	set.fb = NULL;
	set.mode = NULL;
	set.connectors = NULL;
	set.num_connectors = 0;
 
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		set.crtc = crtc;
		ret = drm_mode_set_config_internal(&set);
		WARN_ON(ret != 0);
	}
 
}
#endif
 
static void vmw_master_init(struct vmw_master *vmaster)
{
//	ttm_lock_init(&vmaster->lock);
	INIT_LIST_HEAD(&vmaster->fb_surf);
	mutex_init(&vmaster->fb_surf_mutex);
}
 
static int vmw_master_create(struct drm_device *dev,
			     struct drm_master *master)
{
	struct vmw_master *vmaster;
 
	vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
	if (unlikely(vmaster == NULL))
		return -ENOMEM;
 
	vmw_master_init(vmaster);
//	ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
	master->driver_priv = vmaster;
 
	return 0;
}
 
static void vmw_master_destroy(struct drm_device *dev,
			       struct drm_master *master)
{
	struct vmw_master *vmaster = vmw_master(master);
 
	master->driver_priv = NULL;
	kfree(vmaster);
}
 
#if 0
static int vmw_master_set(struct drm_device *dev,
			  struct drm_file *file_priv,
			  bool from_open)
{
	struct vmw_private *dev_priv = vmw_priv(dev);
	struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
	struct vmw_master *active = dev_priv->active_master;
	struct vmw_master *vmaster = vmw_master(file_priv->master);
	int ret = 0;
 
	if (!dev_priv->enable_fb) {
		ret = vmw_3d_resource_inc(dev_priv, true);
		if (unlikely(ret != 0))
			return ret;
		vmw_kms_save_vga(dev_priv);
		mutex_lock(&dev_priv->hw_mutex);
		vmw_write(dev_priv, SVGA_REG_TRACES, 0);
		mutex_unlock(&dev_priv->hw_mutex);
	}
 
	if (active) {
		BUG_ON(active != &dev_priv->fbdev_master);
		ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
		if (unlikely(ret != 0))
			goto out_no_active_lock;
 
		ttm_lock_set_kill(&active->lock, true, SIGTERM);
		ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
		if (unlikely(ret != 0)) {
			DRM_ERROR("Unable to clean VRAM on "
				  "master drop.\n");
		}
 
		dev_priv->active_master = NULL;
	}
 
	ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
	if (!from_open) {
		ttm_vt_unlock(&vmaster->lock);
		BUG_ON(vmw_fp->locked_master != file_priv->master);
		drm_master_put(&vmw_fp->locked_master);
	}
 
	dev_priv->active_master = vmaster;
 
	return 0;
 
out_no_active_lock:
	if (!dev_priv->enable_fb) {
		vmw_kms_restore_vga(dev_priv);
		vmw_3d_resource_dec(dev_priv, true);
		mutex_lock(&dev_priv->hw_mutex);
		vmw_write(dev_priv, SVGA_REG_TRACES, 1);
		mutex_unlock(&dev_priv->hw_mutex);
	}
	return ret;
}
 
static void vmw_master_drop(struct drm_device *dev,
			    struct drm_file *file_priv,
			    bool from_release)
{
	struct vmw_private *dev_priv = vmw_priv(dev);
	struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
	struct vmw_master *vmaster = vmw_master(file_priv->master);
	int ret;
 
	/**
	 * Make sure the master doesn't disappear while we have
	 * it locked.
	 */
 
	vmw_fp->locked_master = drm_master_get(file_priv->master);
	ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
 
 
	if (unlikely((ret != 0))) {
		DRM_ERROR("Unable to lock TTM at VT switch.\n");
		drm_master_put(&vmw_fp->locked_master);
	}
 
	vmw_execbuf_release_pinned_bo(dev_priv);
 
	if (!dev_priv->enable_fb) {
		ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
		if (unlikely(ret != 0))
			DRM_ERROR("Unable to clean VRAM on master drop.\n");
		vmw_kms_restore_vga(dev_priv);
		vmw_3d_resource_dec(dev_priv, true);
		mutex_lock(&dev_priv->hw_mutex);
		vmw_write(dev_priv, SVGA_REG_TRACES, 1);
		mutex_unlock(&dev_priv->hw_mutex);
	}
 
	dev_priv->active_master = &dev_priv->fbdev_master;
	ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
	ttm_vt_unlock(&dev_priv->fbdev_master.lock);
 
	if (dev_priv->enable_fb)
		vmw_fb_on(dev_priv);
}
 
 
static void vmw_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
 
	drm_put_dev(dev);
}
 
static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
			      void *ptr)
{
	struct vmw_private *dev_priv =
		container_of(nb, struct vmw_private, pm_nb);
	struct vmw_master *vmaster = dev_priv->active_master;
 
	switch (val) {
	case PM_HIBERNATION_PREPARE:
	case PM_SUSPEND_PREPARE:
		ttm_suspend_lock(&vmaster->lock);
 
		/**
		 * This empties VRAM and unbinds all GMR bindings.
		 * Buffer contents is moved to swappable memory.
		 */
		vmw_execbuf_release_pinned_bo(dev_priv);
		vmw_resource_evict_all(dev_priv);
		ttm_bo_swapout_all(&dev_priv->bdev);
 
		break;
	case PM_POST_HIBERNATION:
	case PM_POST_SUSPEND:
	case PM_POST_RESTORE:
		ttm_suspend_unlock(&vmaster->lock);
 
		break;
	case PM_RESTORE_PREPARE:
		break;
	default:
		break;
	}
	return 0;
}
 
/**
 * These might not be needed with the virtual SVGA device.
 */
 
static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct vmw_private *dev_priv = vmw_priv(dev);
 
	if (dev_priv->num_3d_resources != 0) {
		DRM_INFO("Can't suspend or hibernate "
			 "while 3D resources are active.\n");
		return -EBUSY;
	}
 
	pci_save_state(pdev);
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D3hot);
	return 0;
}
 
static int vmw_pci_resume(struct pci_dev *pdev)
{
	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
	return pci_enable_device(pdev);
}
 
static int vmw_pm_suspend(struct device *kdev)
{
	struct pci_dev *pdev = to_pci_dev(kdev);
	struct pm_message dummy;
 
	dummy.event = 0;
 
	return vmw_pci_suspend(pdev, dummy);
}
 
static int vmw_pm_resume(struct device *kdev)
{
	struct pci_dev *pdev = to_pci_dev(kdev);
 
	return vmw_pci_resume(pdev);
}
 
static int vmw_pm_prepare(struct device *kdev)
{
	struct pci_dev *pdev = to_pci_dev(kdev);
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct vmw_private *dev_priv = vmw_priv(dev);
 
	/**
	 * Release 3d reference held by fbdev and potentially
	 * stop fifo.
	 */
	dev_priv->suspended = true;
	if (dev_priv->enable_fb)
			vmw_3d_resource_dec(dev_priv, true);
 
	if (dev_priv->num_3d_resources != 0) {
 
		DRM_INFO("Can't suspend or hibernate "
			 "while 3D resources are active.\n");
 
		if (dev_priv->enable_fb)
			vmw_3d_resource_inc(dev_priv, true);
		dev_priv->suspended = false;
		return -EBUSY;
	}
 
	return 0;
}
 
#endif
 
 
static struct drm_driver driver = {
	.driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
	DRIVER_MODESET,
   .load = vmw_driver_load,
//   .unload = vmw_driver_unload,
//   .firstopen = vmw_firstopen,
//   .lastclose = vmw_lastclose,
   .irq_preinstall = vmw_irq_preinstall,
   .irq_postinstall = vmw_irq_postinstall,
//   .irq_uninstall = vmw_irq_uninstall,
   .irq_handler = vmw_irq_handler,
//   .get_vblank_counter = vmw_get_vblank_counter,
//   .enable_vblank = vmw_enable_vblank,
//   .disable_vblank = vmw_disable_vblank,
//   .ioctls = vmw_ioctls,
//   .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
//   .dma_quiescent = NULL,  /*vmw_dma_quiescent, */
//   .master_create = vmw_master_create,
//   .master_destroy = vmw_master_destroy,
//   .master_set = vmw_master_set,
//   .master_drop = vmw_master_drop,
     .open = vmw_driver_open,
//   .preclose = vmw_preclose,
//   .postclose = vmw_postclose,
 
//   .dumb_create = vmw_dumb_create,
//   .dumb_map_offset = vmw_dumb_map_offset,
//   .dumb_destroy = vmw_dumb_destroy,
 
//   .fops = &vmwgfx_driver_fops,
//   .name = VMWGFX_DRIVER_NAME,
//   .desc = VMWGFX_DRIVER_DESC,
//   .date = VMWGFX_DRIVER_DATE,
//   .major = VMWGFX_DRIVER_MAJOR,
//   .minor = VMWGFX_DRIVER_MINOR,
//   .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
};
 
#if 0
static struct pci_driver vmw_pci_driver = {
	.name = VMWGFX_DRIVER_NAME,
	.id_table = vmw_pci_id_list,
	.probe = vmw_probe,
	.remove = vmw_remove,
	.driver = {
		.pm = &vmw_pm_ops
	}
};
 
static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	return drm_get_pci_dev(pdev, ent, &driver);
}
#endif
 
int vmw_init(void)
{
    static pci_dev_t device;
    const struct pci_device_id  *ent;
    int  err;
 
    ENTER();
 
    ent = find_pci_device(&device, vmw_pci_id_list);
    if( unlikely(ent == NULL) )
    {
        dbgprintf("device not found\n");
        return -ENODEV;
    };
 
    drm_core_init();
 
    DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
                                device.pci_dev.device);
 
    err = drm_get_pci_dev(&device.pci_dev, ent, &driver);
    LEAVE();
 
    return err;
}
 
 
MODULE_AUTHOR("VMware Inc. and others");
MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
MODULE_LICENSE("GPL and additional rights");
 
 
void *kmemdup(const void *src, size_t len, gfp_t gfp)
{
    void *p;
 
    p = kmalloc(len, gfp);
    if (p)
        memcpy(p, src, len);
    return p;
}


Rev 4111	Rev 4569
1	/**************************************************************************	1	/**************************************************************************
2	*	2	*
3	* Copyright © 2009 VMware, Inc., Palo Alto, CA., USA	3	* Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4	* All Rights Reserved.	4	* All Rights Reserved.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the	7	* copy of this software and associated documentation files (the
8	* "Software"), to deal in the Software without restriction, including	8	* "Software"), to deal in the Software without restriction, including
9	* without limitation the rights to use, copy, modify, merge, publish,	9	* without limitation the rights to use, copy, modify, merge, publish,
10	* distribute, sub license, and/or sell copies of the Software, and to	10	* distribute, sub license, and/or sell copies of the Software, and to
11	* permit persons to whom the Software is furnished to do so, subject to	11	* permit persons to whom the Software is furnished to do so, subject to
12	* the following conditions:	12	* the following conditions:
13	*	13	*
14	* The above copyright notice and this permission notice (including the	14	* The above copyright notice and this permission notice (including the
15	* next paragraph) shall be included in all copies or substantial portions	15	* next paragraph) shall be included in all copies or substantial portions
16	* of the Software.	16	* of the Software.
17	*	17	*
18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL	20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,	21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR	22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE	23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24	* USE OR OTHER DEALINGS IN THE SOFTWARE.	24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
25	*	25	*
26	**************************************************************************/	26	**************************************************************************/
27	#include	27	#include
28		28
29	#include	29	#include
30	#include "vmwgfx_drv.h"	30	#include "vmwgfx_drv.h"
31	#include	31	#include
32	#include	32	#include
33	#include	33	#include
34	//#include	34	//#include
-		35	#include
35		36
36	#define VMWGFX_DRIVER_NAME "vmwgfx"	37	#define VMWGFX_DRIVER_NAME "vmwgfx"
37	#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"	38	#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
38	#define VMWGFX_CHIP_SVGAII 0	39	#define VMWGFX_CHIP_SVGAII 0
39	#define VMW_FB_RESERVATION 0	40	#define VMW_FB_RESERVATION 0
40		41
41	#define VMW_MIN_INITIAL_WIDTH 800	42	#define VMW_MIN_INITIAL_WIDTH 800
42	#define VMW_MIN_INITIAL_HEIGHT 600	43	#define VMW_MIN_INITIAL_HEIGHT 600
43		44
44	#if 0	45	#if 0
45	/**	46	/**
46	* Fully encoded drm commands. Might move to vmw_drm.h	47	* Fully encoded drm commands. Might move to vmw_drm.h
47	*/	48	*/
48		49
49	#define DRM_IOCTL_VMW_GET_PARAM \	50	#define DRM_IOCTL_VMW_GET_PARAM \
50	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \	51	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
51	struct drm_vmw_getparam_arg)	52	struct drm_vmw_getparam_arg)
52	#define DRM_IOCTL_VMW_ALLOC_DMABUF \	53	#define DRM_IOCTL_VMW_ALLOC_DMABUF \
53	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \	54	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
54	union drm_vmw_alloc_dmabuf_arg)	55	union drm_vmw_alloc_dmabuf_arg)
55	#define DRM_IOCTL_VMW_UNREF_DMABUF \	56	#define DRM_IOCTL_VMW_UNREF_DMABUF \
56	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \	57	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
57	struct drm_vmw_unref_dmabuf_arg)	58	struct drm_vmw_unref_dmabuf_arg)
58	#define DRM_IOCTL_VMW_CURSOR_BYPASS \	59	#define DRM_IOCTL_VMW_CURSOR_BYPASS \
59	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \	60	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
60	struct drm_vmw_cursor_bypass_arg)	61	struct drm_vmw_cursor_bypass_arg)
61		62
62	#define DRM_IOCTL_VMW_CONTROL_STREAM \	63	#define DRM_IOCTL_VMW_CONTROL_STREAM \
63	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \	64	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
64	struct drm_vmw_control_stream_arg)	65	struct drm_vmw_control_stream_arg)
65	#define DRM_IOCTL_VMW_CLAIM_STREAM \	66	#define DRM_IOCTL_VMW_CLAIM_STREAM \
66	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \	67	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
67	struct drm_vmw_stream_arg)	68	struct drm_vmw_stream_arg)
68	#define DRM_IOCTL_VMW_UNREF_STREAM \	69	#define DRM_IOCTL_VMW_UNREF_STREAM \
69	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \	70	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
70	struct drm_vmw_stream_arg)	71	struct drm_vmw_stream_arg)
71		72
72	#define DRM_IOCTL_VMW_CREATE_CONTEXT \	73	#define DRM_IOCTL_VMW_CREATE_CONTEXT \
73	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \	74	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
74	struct drm_vmw_context_arg)	75	struct drm_vmw_context_arg)
75	#define DRM_IOCTL_VMW_UNREF_CONTEXT \	76	#define DRM_IOCTL_VMW_UNREF_CONTEXT \
76	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \	77	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
77	struct drm_vmw_context_arg)	78	struct drm_vmw_context_arg)
78	#define DRM_IOCTL_VMW_CREATE_SURFACE \	79	#define DRM_IOCTL_VMW_CREATE_SURFACE \
79	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \	80	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
80	union drm_vmw_surface_create_arg)	81	union drm_vmw_surface_create_arg)
81	#define DRM_IOCTL_VMW_UNREF_SURFACE \	82	#define DRM_IOCTL_VMW_UNREF_SURFACE \
82	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \	83	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
83	struct drm_vmw_surface_arg)	84	struct drm_vmw_surface_arg)
84	#define DRM_IOCTL_VMW_REF_SURFACE \	85	#define DRM_IOCTL_VMW_REF_SURFACE \
85	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \	86	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
86	union drm_vmw_surface_reference_arg)	87	union drm_vmw_surface_reference_arg)
87	#define DRM_IOCTL_VMW_EXECBUF \	88	#define DRM_IOCTL_VMW_EXECBUF \
88	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \	89	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
89	struct drm_vmw_execbuf_arg)	90	struct drm_vmw_execbuf_arg)
90	#define DRM_IOCTL_VMW_GET_3D_CAP \	91	#define DRM_IOCTL_VMW_GET_3D_CAP \
91	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \	92	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
92	struct drm_vmw_get_3d_cap_arg)	93	struct drm_vmw_get_3d_cap_arg)
93	#define DRM_IOCTL_VMW_FENCE_WAIT \	94	#define DRM_IOCTL_VMW_FENCE_WAIT \
94	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \	95	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
95	struct drm_vmw_fence_wait_arg)	96	struct drm_vmw_fence_wait_arg)
96	#define DRM_IOCTL_VMW_FENCE_SIGNALED \	97	#define DRM_IOCTL_VMW_FENCE_SIGNALED \
97	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \	98	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
98	struct drm_vmw_fence_signaled_arg)	99	struct drm_vmw_fence_signaled_arg)
99	#define DRM_IOCTL_VMW_FENCE_UNREF \	100	#define DRM_IOCTL_VMW_FENCE_UNREF \
100	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \	101	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
101	struct drm_vmw_fence_arg)	102	struct drm_vmw_fence_arg)
102	#define DRM_IOCTL_VMW_FENCE_EVENT \	103	#define DRM_IOCTL_VMW_FENCE_EVENT \
103	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \	104	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
104	struct drm_vmw_fence_event_arg)	105	struct drm_vmw_fence_event_arg)
105	#define DRM_IOCTL_VMW_PRESENT \	106	#define DRM_IOCTL_VMW_PRESENT \
106	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \	107	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
107	struct drm_vmw_present_arg)	108	struct drm_vmw_present_arg)
108	#define DRM_IOCTL_VMW_PRESENT_READBACK \	109	#define DRM_IOCTL_VMW_PRESENT_READBACK \
109	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \	110	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
110	struct drm_vmw_present_readback_arg)	111	struct drm_vmw_present_readback_arg)
111	#define DRM_IOCTL_VMW_UPDATE_LAYOUT \	112	#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
112	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \	113	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
113	struct drm_vmw_update_layout_arg)	114	struct drm_vmw_update_layout_arg)
-		115	#define DRM_IOCTL_VMW_CREATE_SHADER \
-		116	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
-		117	struct drm_vmw_shader_create_arg)
-		118	#define DRM_IOCTL_VMW_UNREF_SHADER \
-		119	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
-		120	struct drm_vmw_shader_arg)
-		121	#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
-		122	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
-		123	union drm_vmw_gb_surface_create_arg)
-		124	#define DRM_IOCTL_VMW_GB_SURFACE_REF \
-		125	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
-		126	union drm_vmw_gb_surface_reference_arg)
-		127	#define DRM_IOCTL_VMW_SYNCCPU \
-		128	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
-		129	struct drm_vmw_synccpu_arg)
114		130
115	/**	131	/**
116	* The core DRM version of this macro doesn't account for	132	* The core DRM version of this macro doesn't account for
117	* DRM_COMMAND_BASE.	133	* DRM_COMMAND_BASE.
118	*/	134	*/
119		135
120	#define VMW_IOCTL_DEF(ioctl, func, flags) \	136	#define VMW_IOCTL_DEF(ioctl, func, flags) \
121	[DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}	137	[DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
122		138
123	/**	139	/**
124	* Ioctl definitions.	140	* Ioctl definitions.
125	*/	141	*/
126		142
127	static const struct drm_ioctl_desc vmw_ioctls[] = {	143	static const struct drm_ioctl_desc vmw_ioctls[] = {
128	VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,	144	VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
129	DRM_AUTH \| DRM_UNLOCKED),	145	DRM_AUTH \| DRM_UNLOCKED),
130	VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,	146	VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
131	DRM_AUTH \| DRM_UNLOCKED),	147	DRM_AUTH \| DRM_UNLOCKED),
132	VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,	148	VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
133	DRM_AUTH \| DRM_UNLOCKED),	149	DRM_AUTH \| DRM_UNLOCKED),
134	VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,	150	VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
135	vmw_kms_cursor_bypass_ioctl,	151	vmw_kms_cursor_bypass_ioctl,
136	DRM_MASTER \| DRM_CONTROL_ALLOW \| DRM_UNLOCKED),	152	DRM_MASTER \| DRM_CONTROL_ALLOW \| DRM_UNLOCKED),
137		153
138	VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,	154	VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
139	DRM_MASTER \| DRM_CONTROL_ALLOW \| DRM_UNLOCKED),	155	DRM_MASTER \| DRM_CONTROL_ALLOW \| DRM_UNLOCKED),
140	VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,	156	VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
141	DRM_MASTER \| DRM_CONTROL_ALLOW \| DRM_UNLOCKED),	157	DRM_MASTER \| DRM_CONTROL_ALLOW \| DRM_UNLOCKED),
142	VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,	158	VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
143	DRM_MASTER \| DRM_CONTROL_ALLOW \| DRM_UNLOCKED),	159	DRM_MASTER \| DRM_CONTROL_ALLOW \| DRM_UNLOCKED),
144		160
145	VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,	161	VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
146	DRM_AUTH \| DRM_UNLOCKED),	162	DRM_AUTH \| DRM_UNLOCKED),
147	VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,	163	VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
148	DRM_AUTH \| DRM_UNLOCKED),	164	DRM_AUTH \| DRM_UNLOCKED),
149	VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,	165	VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
150	DRM_AUTH \| DRM_UNLOCKED),	166	DRM_AUTH \| DRM_UNLOCKED),
151	VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,	167	VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
152	DRM_AUTH \| DRM_UNLOCKED),	168	DRM_AUTH \| DRM_UNLOCKED),
153	VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,	169	VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
154	DRM_AUTH \| DRM_UNLOCKED),	170	DRM_AUTH \| DRM_UNLOCKED),
155	VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,	171	VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
156	DRM_AUTH \| DRM_UNLOCKED),	172	DRM_AUTH \| DRM_UNLOCKED),
157	VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,	173	VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
158	DRM_AUTH \| DRM_UNLOCKED),	174	DRM_AUTH \| DRM_UNLOCKED),
159	VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,	175	VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
160	vmw_fence_obj_signaled_ioctl,	176	vmw_fence_obj_signaled_ioctl,
161	DRM_AUTH \| DRM_UNLOCKED),	177	DRM_AUTH \| DRM_UNLOCKED),
162	VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,	178	VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
163	DRM_AUTH \| DRM_UNLOCKED),	179	DRM_AUTH \| DRM_UNLOCKED),
164	VMW_IOCTL_DEF(VMW_FENCE_EVENT,	180	VMW_IOCTL_DEF(VMW_FENCE_EVENT,
165	vmw_fence_event_ioctl,	181	vmw_fence_event_ioctl,
166	DRM_AUTH \| DRM_UNLOCKED),	182	DRM_AUTH \| DRM_UNLOCKED),
167	VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,	183	VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
168	DRM_AUTH \| DRM_UNLOCKED),	184	DRM_AUTH \| DRM_UNLOCKED),
169		185
170	/* these allow direct access to the framebuffers mark as master only */	186	/* these allow direct access to the framebuffers mark as master only */
171	VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,	187	VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
172	DRM_MASTER \| DRM_AUTH \| DRM_UNLOCKED),	188	DRM_MASTER \| DRM_AUTH \| DRM_UNLOCKED),
173	VMW_IOCTL_DEF(VMW_PRESENT_READBACK,	189	VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
174	vmw_present_readback_ioctl,	190	vmw_present_readback_ioctl,
175	DRM_MASTER \| DRM_AUTH \| DRM_UNLOCKED),	191	DRM_MASTER \| DRM_AUTH \| DRM_UNLOCKED),
176	VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,	192	VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
177	vmw_kms_update_layout_ioctl,	193	vmw_kms_update_layout_ioctl,
178	DRM_MASTER \| DRM_UNLOCKED),	194	DRM_MASTER \| DRM_UNLOCKED),
-		195	VMW_IOCTL_DEF(VMW_CREATE_SHADER,
-		196	vmw_shader_define_ioctl,
-		197	DRM_AUTH \| DRM_UNLOCKED),
-		198	VMW_IOCTL_DEF(VMW_UNREF_SHADER,
-		199	vmw_shader_destroy_ioctl,
-		200	DRM_AUTH \| DRM_UNLOCKED),
-		201	VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
-		202	vmw_gb_surface_define_ioctl,
-		203	DRM_AUTH \| DRM_UNLOCKED),
-		204	VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
-		205	vmw_gb_surface_reference_ioctl,
-		206	DRM_AUTH \| DRM_UNLOCKED),
-		207	VMW_IOCTL_DEF(VMW_SYNCCPU,
-		208	vmw_user_dmabuf_synccpu_ioctl,
-		209	DRM_AUTH \| DRM_UNLOCKED),
179	};	210	};
180	#endif	211	#endif
181		212
182	static struct pci_device_id vmw_pci_id_list[] = {	213	static struct pci_device_id vmw_pci_id_list[] = {
183	{0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},	214	{0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
184	{0, 0, 0}	215	{0, 0, 0}
185	};	216	};
186		217
187	static int enable_fbdev = 1;	218	static int enable_fbdev = 1;
-		219	static int vmw_force_iommu;
-		220	static int vmw_restrict_iommu;
-		221	static int vmw_force_coherent;
-		222	static int vmw_restrict_dma_mask;
188		223
189	static int vmw_probe(struct pci_dev , const struct pci_device_id );	224	static int vmw_probe(struct pci_dev , const struct pci_device_id );
190	static void vmw_master_init(struct vmw_master *);	225	static void vmw_master_init(struct vmw_master *);
191		226
192	MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");	227	MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
193	module_param_named(enable_fbdev, enable_fbdev, int, 0600);	228	module_param_named(enable_fbdev, enable_fbdev, int, 0600);
-		229	MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
-		230	module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
-		231	MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
-		232	module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
-		233	MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
-		234	module_param_named(force_coherent, vmw_force_coherent, int, 0600);
-		235	MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
-		236	module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
-		237
194		238
195	static void vmw_print_capabilities(uint32_t capabilities)	239	static void vmw_print_capabilities(uint32_t capabilities)
196	{	240	{
197	DRM_INFO("Capabilities:\n");	241	DRM_INFO("Capabilities:\n");
198	if (capabilities & SVGA_CAP_RECT_COPY)	242	if (capabilities & SVGA_CAP_RECT_COPY)
199	DRM_INFO(" Rect copy.\n");	243	DRM_INFO(" Rect copy.\n");
200	if (capabilities & SVGA_CAP_CURSOR)	244	if (capabilities & SVGA_CAP_CURSOR)
201	DRM_INFO(" Cursor.\n");	245	DRM_INFO(" Cursor.\n");
202	if (capabilities & SVGA_CAP_CURSOR_BYPASS)	246	if (capabilities & SVGA_CAP_CURSOR_BYPASS)
203	DRM_INFO(" Cursor bypass.\n");	247	DRM_INFO(" Cursor bypass.\n");
204	if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)	248	if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
205	DRM_INFO(" Cursor bypass 2.\n");	249	DRM_INFO(" Cursor bypass 2.\n");
206	if (capabilities & SVGA_CAP_8BIT_EMULATION)	250	if (capabilities & SVGA_CAP_8BIT_EMULATION)
207	DRM_INFO(" 8bit emulation.\n");	251	DRM_INFO(" 8bit emulation.\n");
208	if (capabilities & SVGA_CAP_ALPHA_CURSOR)	252	if (capabilities & SVGA_CAP_ALPHA_CURSOR)
209	DRM_INFO(" Alpha cursor.\n");	253	DRM_INFO(" Alpha cursor.\n");
210	if (capabilities & SVGA_CAP_3D)	254	if (capabilities & SVGA_CAP_3D)
211	DRM_INFO(" 3D.\n");	255	DRM_INFO(" 3D.\n");
212	if (capabilities & SVGA_CAP_EXTENDED_FIFO)	256	if (capabilities & SVGA_CAP_EXTENDED_FIFO)
213	DRM_INFO(" Extended Fifo.\n");	257	DRM_INFO(" Extended Fifo.\n");
214	if (capabilities & SVGA_CAP_MULTIMON)	258	if (capabilities & SVGA_CAP_MULTIMON)
215	DRM_INFO(" Multimon.\n");	259	DRM_INFO(" Multimon.\n");
216	if (capabilities & SVGA_CAP_PITCHLOCK)	260	if (capabilities & SVGA_CAP_PITCHLOCK)
217	DRM_INFO(" Pitchlock.\n");	261	DRM_INFO(" Pitchlock.\n");
218	if (capabilities & SVGA_CAP_IRQMASK)	262	if (capabilities & SVGA_CAP_IRQMASK)
219	DRM_INFO(" Irq mask.\n");	263	DRM_INFO(" Irq mask.\n");
220	if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)	264	if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
221	DRM_INFO(" Display Topology.\n");	265	DRM_INFO(" Display Topology.\n");
222	if (capabilities & SVGA_CAP_GMR)	266	if (capabilities & SVGA_CAP_GMR)
223	DRM_INFO(" GMR.\n");	267	DRM_INFO(" GMR.\n");
224	if (capabilities & SVGA_CAP_TRACES)	268	if (capabilities & SVGA_CAP_TRACES)
225	DRM_INFO(" Traces.\n");	269	DRM_INFO(" Traces.\n");
226	if (capabilities & SVGA_CAP_GMR2)	270	if (capabilities & SVGA_CAP_GMR2)
227	DRM_INFO(" GMR2.\n");	271	DRM_INFO(" GMR2.\n");
228	if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)	272	if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
229	DRM_INFO(" Screen Object 2.\n");	273	DRM_INFO(" Screen Object 2.\n");
-		274	if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
-		275	DRM_INFO(" Command Buffers.\n");
-		276	if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
-		277	DRM_INFO(" Command Buffers 2.\n");
-		278	if (capabilities & SVGA_CAP_GBOBJECTS)
-		279	DRM_INFO(" Guest Backed Resources.\n");
230	}	280	}
231		-
232		281
233	/**	282	/**
234	* vmw_execbuf_prepare_dummy_query - Initialize a query result structure at	-
235	* the start of a buffer object.	283	* vmw_dummy_query_bo_create - create a bo to hold a dummy query result
236	*	284	*
237	* @dev_priv: The device private structure.	285	* @dev_priv: A device private structure.
238	*	286	*
-		287	* This function creates a small buffer object that holds the query
239	* This function will idle the buffer using an uninterruptible wait, then	288	* result for dummy queries emitted as query barriers.
240	* map the first page and initialize a pending occlusion query result structure,	289	* The function will then map the first page and initialize a pending
-		290	* occlusion query result structure, Finally it will unmap the buffer.
241	* Finally it will unmap the buffer.	291	* No interruptible waits are done within this function.
242	*	-
243	* TODO: Since we're only mapping a single page, we should optimize the map	292	*
244	* to use kmap_atomic / iomap_atomic.	293	* Returns an error if bo creation or initialization fails.
245	*/	294	*/
246	static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)	295	static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
-		296	{
-		297	int ret;
247	{	298	struct ttm_buffer_object *bo;
248	struct ttm_bo_kmap_obj map;	299	struct ttm_bo_kmap_obj map;
249	volatile SVGA3dQueryResult *result;	300	volatile SVGA3dQueryResult *result;
250	bool dummy;	301	bool dummy;
251	int ret;	-
252	struct ttm_bo_device *bdev = &dev_priv->bdev;	-
253	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;	-
254		-
255	ttm_bo_reserve(bo, false, false, false, 0);	-
256	spin_lock(&bdev->fence_lock);	-
257	ret = 0; //ttm_bo_wait(bo, false, false, false);	-
258	spin_unlock(&bdev->fence_lock);	-
259	if (unlikely(ret != 0))	-
260	(void) vmw_fallback_wait(dev_priv, false, true, 0, false,	-
261	10*HZ);	302
-		303	/*
-		304	* Create the bo as pinned, so that a tryreserve will
-		305	* immediately succeed. This is because we're the only
-		306	* user of the bo currently.
-		307	*/
-		308	ret = ttm_bo_create(&dev_priv->bdev,
-		309	PAGE_SIZE,
-		310	ttm_bo_type_device,
-		311	&vmw_sys_ne_placement,
-		312	0, false, NULL,
-		313	&bo);
-		314
-		315	if (unlikely(ret != 0))
-		316	return ret;
-		317
-		318	ret = ttm_bo_reserve(bo, false, true, false, 0);
-		319	BUG_ON(ret != 0);
262	/*	320
263	ret = ttm_bo_kmap(bo, 0, 1, &map);	321	ret = ttm_bo_kmap(bo, 0, 1, &map);
264	if (likely(ret == 0)) {	322	if (likely(ret == 0)) {
265	result = ttm_kmap_obj_virtual(&map, &dummy);	323	result = ttm_kmap_obj_virtual(&map, &dummy);
266	result->totalSize = sizeof(*result);	324	result->totalSize = sizeof(*result);
267	result->state = SVGA3D_QUERYSTATE_PENDING;	325	result->state = SVGA3D_QUERYSTATE_PENDING;
268	result->result32 = 0xff;	326	result->result32 = 0xff;
269	ttm_bo_kunmap(&map);	327	ttm_bo_kunmap(&map);
270	} else	-
271	DRM_ERROR("Dummy query buffer map failed.\n");	-
272	*/	-
273	ttm_bo_unreserve(bo);	-
274	}	328	}
-		329	vmw_bo_pin(bo, false);
-		330	ttm_bo_unreserve(bo);
-		331
-		332	if (unlikely(ret != 0)) {
-		333	DRM_ERROR("Dummy query buffer map failed.\n");
-		334	ttm_bo_unref(&bo);
-		335	} else
275		-
276		-
277	/**	-
278	* vmw_dummy_query_bo_create - create a bo to hold a dummy query result	-
279	*	-
280	* @dev_priv: A device private structure.	-
281	*	-
282	* This function creates a small buffer object that holds the query	-
283	* result for dummy queries emitted as query barriers.	-
284	* No interruptible waits are done within this function.	-
285	*	-
286	* Returns an error if bo creation fails.	-
287	*/	-
288	static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)	-
289	{	336	dev_priv->dummy_query_bo = bo;
290	return ttm_bo_create(&dev_priv->bdev,	-
291	PAGE_SIZE,	-
292	ttm_bo_type_device,	-
293	&vmw_vram_sys_placement,	-
294	0, false, NULL,	337
295	&dev_priv->dummy_query_bo);	-
296	}	338	return ret;
297		339	}
298		340
299	static int vmw_request_device(struct vmw_private *dev_priv)	341	static int vmw_request_device(struct vmw_private *dev_priv)
300	{	342	{
301	int ret;	343	int ret;
302	ENTER();	344	ENTER();
303		345
304	ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);	346	ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
305	if (unlikely(ret != 0)) {	347	if (unlikely(ret != 0)) {
306	DRM_ERROR("Unable to initialize FIFO.\n");	348	DRM_ERROR("Unable to initialize FIFO.\n");
307	return ret;	349	return ret;
308	}	350	}
309	// vmw_fence_fifo_up(dev_priv->fman);	351	// vmw_fence_fifo_up(dev_priv->fman);
310	// ret = vmw_dummy_query_bo_create(dev_priv);	352	// ret = vmw_dummy_query_bo_create(dev_priv);
311	// if (unlikely(ret != 0))	353	// if (unlikely(ret != 0))
312	// goto out_no_query_bo;	354	// goto out_no_query_bo;
313	// vmw_dummy_query_bo_prepare(dev_priv);	355	// vmw_dummy_query_bo_prepare(dev_priv);
314		356
315	LEAVE();	357	LEAVE();
316		358
317	return 0;	359	return 0;
318		360
319	out_no_query_bo:	361	out_no_query_bo:
320	vmw_fence_fifo_down(dev_priv->fman);	362	vmw_fence_fifo_down(dev_priv->fman);
321	vmw_fifo_release(dev_priv, &dev_priv->fifo);	363	vmw_fifo_release(dev_priv, &dev_priv->fifo);
322	return ret;	364	return ret;
323	}	365	}
324		366
325	static void vmw_release_device(struct vmw_private *dev_priv)	367	static void vmw_release_device(struct vmw_private *dev_priv)
326	{	368	{
327	/*	369	/*
328	* Previous destructions should've released	370	* Previous destructions should've released
329	* the pinned bo.	371	* the pinned bo.
330	*/	372	*/
331		373
332	BUG_ON(dev_priv->pinned_bo != NULL);	374	BUG_ON(dev_priv->pinned_bo != NULL);
333		375
334	ttm_bo_unref(&dev_priv->dummy_query_bo);	376	ttm_bo_unref(&dev_priv->dummy_query_bo);
335	vmw_fence_fifo_down(dev_priv->fman);	377	vmw_fence_fifo_down(dev_priv->fman);
336	vmw_fifo_release(dev_priv, &dev_priv->fifo);	378	vmw_fifo_release(dev_priv, &dev_priv->fifo);
337	}	379	}
-		380
338		381
339	/**	382	/**
340	* Increase the 3d resource refcount.	383	* Increase the 3d resource refcount.
341	* If the count was prevously zero, initialize the fifo, switching to svga	384	* If the count was prevously zero, initialize the fifo, switching to svga
342	* mode. Note that the master holds a ref as well, and may request an	385	* mode. Note that the master holds a ref as well, and may request an
343	* explicit switch to svga mode if fb is not running, using @unhide_svga.	386	* explicit switch to svga mode if fb is not running, using @unhide_svga.
344	*/	387	*/
345	int vmw_3d_resource_inc(struct vmw_private *dev_priv,	388	int vmw_3d_resource_inc(struct vmw_private *dev_priv,
346	bool unhide_svga)	389	bool unhide_svga)
347	{	390	{
348	int ret = 0;	391	int ret = 0;
349		392
350	ENTER();	393	ENTER();
351		394
352	mutex_lock(&dev_priv->release_mutex);	395	mutex_lock(&dev_priv->release_mutex);
353	if (unlikely(dev_priv->num_3d_resources++ == 0)) {	396	if (unlikely(dev_priv->num_3d_resources++ == 0)) {
354	ret = vmw_request_device(dev_priv);	397	ret = vmw_request_device(dev_priv);
355	if (unlikely(ret != 0))	398	if (unlikely(ret != 0))
356	--dev_priv->num_3d_resources;	399	--dev_priv->num_3d_resources;
357	} else if (unhide_svga) {	400	} else if (unhide_svga) {
358	mutex_lock(&dev_priv->hw_mutex);	401	mutex_lock(&dev_priv->hw_mutex);
359	vmw_write(dev_priv, SVGA_REG_ENABLE,	402	vmw_write(dev_priv, SVGA_REG_ENABLE,
360	vmw_read(dev_priv, SVGA_REG_ENABLE) &	403	vmw_read(dev_priv, SVGA_REG_ENABLE) &
361	~SVGA_REG_ENABLE_HIDE);	404	~SVGA_REG_ENABLE_HIDE);
362	mutex_unlock(&dev_priv->hw_mutex);	405	mutex_unlock(&dev_priv->hw_mutex);
363	}	406	}
364		407
365	mutex_unlock(&dev_priv->release_mutex);	408	mutex_unlock(&dev_priv->release_mutex);
366	LEAVE();	409	LEAVE();
367	return ret;	410	return ret;
368	}	411	}
369		412
370	/**	413	/**
371	* Decrease the 3d resource refcount.	414	* Decrease the 3d resource refcount.
372	* If the count reaches zero, disable the fifo, switching to vga mode.	415	* If the count reaches zero, disable the fifo, switching to vga mode.
373	* Note that the master holds a refcount as well, and may request an	416	* Note that the master holds a refcount as well, and may request an
374	* explicit switch to vga mode when it releases its refcount to account	417	* explicit switch to vga mode when it releases its refcount to account
375	* for the situation of an X server vt switch to VGA with 3d resources	418	* for the situation of an X server vt switch to VGA with 3d resources
376	* active.	419	* active.
377	*/	420	*/
378	void vmw_3d_resource_dec(struct vmw_private *dev_priv,	421	void vmw_3d_resource_dec(struct vmw_private *dev_priv,
379	bool hide_svga)	422	bool hide_svga)
380	{	423	{
381	int32_t n3d;	424	int32_t n3d;
382		425
383	mutex_lock(&dev_priv->release_mutex);	426	mutex_lock(&dev_priv->release_mutex);
384	if (unlikely(--dev_priv->num_3d_resources == 0))	427	if (unlikely(--dev_priv->num_3d_resources == 0))
385	vmw_release_device(dev_priv);	428	vmw_release_device(dev_priv);
386	else if (hide_svga) {	429	else if (hide_svga) {
387	mutex_lock(&dev_priv->hw_mutex);	430	mutex_lock(&dev_priv->hw_mutex);
388	vmw_write(dev_priv, SVGA_REG_ENABLE,	431	vmw_write(dev_priv, SVGA_REG_ENABLE,
389	vmw_read(dev_priv, SVGA_REG_ENABLE) \|	432	vmw_read(dev_priv, SVGA_REG_ENABLE) \|
390	SVGA_REG_ENABLE_HIDE);	433	SVGA_REG_ENABLE_HIDE);
391	mutex_unlock(&dev_priv->hw_mutex);	434	mutex_unlock(&dev_priv->hw_mutex);
392	}	435	}
393		436
394	n3d = (int32_t) dev_priv->num_3d_resources;	437	n3d = (int32_t) dev_priv->num_3d_resources;
395	mutex_unlock(&dev_priv->release_mutex);	438	mutex_unlock(&dev_priv->release_mutex);
396		439
397	BUG_ON(n3d < 0);	440	BUG_ON(n3d < 0);
398	}	441	}
399		442
400	/**	443	/**
401	* Sets the initial_[width\|height] fields on the given vmw_private.	444	* Sets the initial_[width\|height] fields on the given vmw_private.
402	*	445	*
403	* It does so by reading SVGA_REG_[WIDTH\|HEIGHT] regs and then	446	* It does so by reading SVGA_REG_[WIDTH\|HEIGHT] regs and then
404	* clamping the value to fb_max_[width\|height] fields and the	447	* clamping the value to fb_max_[width\|height] fields and the
405	* VMW_MIN_INITIAL_[WIDTH\|HEIGHT].	448	* VMW_MIN_INITIAL_[WIDTH\|HEIGHT].
406	* If the values appear to be invalid, set them to	449	* If the values appear to be invalid, set them to
407	* VMW_MIN_INITIAL_[WIDTH\|HEIGHT].	450	* VMW_MIN_INITIAL_[WIDTH\|HEIGHT].
408	*/	451	*/
409	static void vmw_get_initial_size(struct vmw_private *dev_priv)	452	static void vmw_get_initial_size(struct vmw_private *dev_priv)
410	{	453	{
411	uint32_t width;	454	uint32_t width;
412	uint32_t height;	455	uint32_t height;
413		456
414	width = vmw_read(dev_priv, SVGA_REG_WIDTH);	457	width = vmw_read(dev_priv, SVGA_REG_WIDTH);
415	height = vmw_read(dev_priv, SVGA_REG_HEIGHT);	458	height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
416		459
417	width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);	460	width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
418	height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);	461	height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
419		462
420	if (width > dev_priv->fb_max_width \|\|	463	if (width > dev_priv->fb_max_width \|\|
421	height > dev_priv->fb_max_height) {	464	height > dev_priv->fb_max_height) {

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/vmwgfx/vmwgfx_drv.c – Rev 4111 → 4569