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| - | 1 | #include |
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| Line 1... | Line 2... | ||
| 1 | #include |
2 | |
| 2 | #include |
3 | #include |
| 3 | #include |
4 | #include |
| 4 | #include |
5 | #include |
| 5 | #include |
- | |
| 6 | #include |
6 | #include |
| Line -... | Line 7... | ||
| - | 7 | #include |
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| - | 8 | ||
| 7 | 9 | #include |
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| Line 8... | Line 10... | ||
| 8 | extern int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn); |
10 | |
| Line 9... | Line 11... | ||
| 9 | 11 | extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn); |
|
| 10 | static LIST_HEAD(devices); |
12 | |
| Line 29... | Line 31... | ||
| 29 | return IORESOURCE_MEM; |
31 | |
| 30 | } |
32 | return IORESOURCE_MEM; |
| Line 31... | Line 33... | ||
| 31 | 33 | } |
|
| 32 | 34 | ||
| 33 | static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask) |
35 | |
| Line 34... | Line 36... | ||
| 34 | { |
36 | static u32 pci_size(u32 base, u32 maxbase, u32 mask) |
| 35 | u32_t size = mask & maxbase; /* Find the significant bits */ |
37 | { |
| Line 36... | Line 38... | ||
| 36 | 38 | u32 size = mask & maxbase; /* Find the significant bits */ |
|
| Line 48... | Line 50... | ||
| 48 | 50 | return 0; |
|
| Line 49... | Line 51... | ||
| 49 | return size; |
51 | |
| 50 | } |
52 | return size; |
| Line 51... | Line 53... | ||
| 51 | 53 | } |
|
| 52 | static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask) |
54 | |
| 53 | { |
55 | static u64 pci_size64(u64 base, u64 maxbase, u64 mask) |
| Line 54... | Line 56... | ||
| 54 | u64_t size = mask & maxbase; /* Find the significant bits */ |
56 | { |
| 55 | 57 | u64 size = mask & maxbase; /* Find the significant bits */ |
|
| Line 56... | Line 58... | ||
| 56 | if (!size) |
58 | |
| Line 67... | Line 69... | ||
| 67 | 69 | return 0; |
|
| Line 68... | Line 70... | ||
| 68 | return size; |
70 | |
| 69 | } |
71 | return size; |
| Line 70... | Line 72... | ||
| 70 | 72 | } |
|
| 71 | static inline int is_64bit_memory(u32_t mask) |
73 | |
| 72 | { |
74 | static inline int is_64bit_memory(u32 mask) |
| 73 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
75 | { |
| 74 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
76 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
| 75 | return 1; |
77 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
| 76 | return 0; |
78 | return 1; |
| Line 77... | Line 79... | ||
| 77 | } |
79 | return 0; |
| 78 | 80 | } |
|
| 79 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
81 | |
| 80 | { |
82 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
| 81 | u32_t pos, reg, next; |
83 | { |
| Line 82... | Line 84... | ||
| 82 | u32_t l, sz; |
84 | u32 pos, reg, next; |
| 83 | struct resource *res; |
85 | u32 l, sz; |
| 84 | 86 | struct resource *res; |
|
| 85 | for(pos=0; pos < howmany; pos = next) |
87 | |
| 86 | { |
88 | for(pos=0; pos < howmany; pos = next) |
| Line 87... | Line 89... | ||
| 87 | u64_t l64; |
89 | { |
| Line 88... | Line 90... | ||
| 88 | u64_t sz64; |
90 | u64 l64; |
| Line 107... | Line 109... | ||
| 107 | raw_sz = sz; |
109 | |
| 108 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
110 | raw_sz = sz; |
| 109 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
111 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
| 110 | { |
112 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
| 111 | sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
113 | { |
| 112 | /* |
114 | sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK); |
| 113 | * For 64bit prefetchable memory sz could be 0, if the |
115 | /* |
| 114 | * real size is bigger than 4G, so we need to check |
116 | * For 64bit prefetchable memory sz could be 0, if the |
| 115 | * szhi for that. |
117 | * real size is bigger than 4G, so we need to check |
| 116 | */ |
118 | * szhi for that. |
| Line 129... | Line 131... | ||
| 129 | res->end = res->start + (unsigned long) sz; |
131 | } |
| 130 | res->flags |= pci_calc_resource_flags(l); |
132 | res->end = res->start + (unsigned long) sz; |
| 131 | if (is_64bit_memory(l)) |
133 | res->flags |= pci_calc_resource_flags(l); |
| 132 | { |
134 | if (is_64bit_memory(l)) |
| 133 | u32_t szhi, lhi; |
135 | { |
| 134 | 136 | u32 szhi, lhi; |
|
| Line 135... | Line 137... | ||
| 135 | lhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
137 | |
| 136 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
138 | lhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
| 137 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
139 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
| 138 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
140 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
| 139 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
141 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
| 140 | l64 = ((u64_t)lhi << 32) | l; |
142 | sz64 = ((u64)szhi << 32) | raw_sz; |
| 141 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
143 | l64 = ((u64)lhi << 32) | l; |
| 142 | next++; |
144 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
| Line 143... | Line 145... | ||
| 143 | 145 | next++; |
|
| 144 | #if BITS_PER_LONG == 64 |
146 | |
| Line 160... | Line 162... | ||
| 160 | else if (lhi) |
162 | } |
| 161 | { |
163 | else if (lhi) |
| 162 | /* 64-bit wide address, treat as disabled */ |
164 | { |
| 163 | PciWrite32(dev->busnr, dev->devfn, reg, |
165 | /* 64-bit wide address, treat as disabled */ |
| 164 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
166 | PciWrite32(dev->busnr, dev->devfn, reg, |
| 165 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
167 | l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK); |
| 166 | res->start = 0; |
168 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
| 167 | res->end = sz; |
169 | res->start = 0; |
| 168 | } |
170 | res->end = sz; |
| 169 | #endif |
171 | } |
| 170 | } |
172 | #endif |
| Line 184... | Line 186... | ||
| 184 | l = 0; |
186 | if (l == 0xffffffff) |
| 185 | 187 | l = 0; |
|
| Line 186... | Line 188... | ||
| 186 | if (sz && sz != 0xffffffff) |
188 | |
| 187 | { |
189 | if (sz && sz != 0xffffffff) |
| 188 | sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK); |
190 | { |
| Line 189... | Line 191... | ||
| 189 | 191 | sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK); |
|
| 190 | if (sz) |
192 | |
| 191 | { |
193 | if (sz) |
| 192 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
194 | { |
| Line 200... | Line 202... | ||
| 200 | } |
202 | } |
| 201 | 203 | } |
|
| Line 202... | Line 204... | ||
| 202 | static void pci_read_irq(struct pci_dev *dev) |
204 | |
| 203 | { |
205 | static void pci_read_irq(struct pci_dev *dev) |
| 204 | u8_t irq; |
206 | { |
| Line 205... | Line 207... | ||
| 205 | 207 | u8 irq; |
|
| 206 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN); |
208 | |
| 207 | dev->pin = irq; |
209 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN); |
| 208 | if (irq) |
210 | dev->pin = irq; |
| Line 212... | Line 214... | ||
| 212 | 214 | }; |
|
| Line 213... | Line 215... | ||
| 213 | 215 | ||
| 214 | int pci_setup_device(struct pci_dev *dev) |
216 | |
| 215 | { |
217 | int pci_setup_device(struct pci_dev *dev) |
| Line 216... | Line 218... | ||
| 216 | u32_t class; |
218 | { |
| 217 | 219 | u32 class; |
|
| 218 | class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION); |
220 | |
| 219 | dev->revision = class & 0xff; |
221 | class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION); |
| Line 244... | Line 246... | ||
| 244 | * BAR0-3 in a few cases contain junk! |
246 | * addresses. These are not always echoed in BAR0-3, and |
| 245 | */ |
247 | * BAR0-3 in a few cases contain junk! |
| 246 | if (class == PCI_CLASS_STORAGE_IDE) |
248 | */ |
| 247 | { |
249 | if (class == PCI_CLASS_STORAGE_IDE) |
| 248 | u8_t progif; |
250 | { |
| 249 | 251 | u8 progif; |
|
| Line 250... | Line 252... | ||
| 250 | progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG); |
252 | |
| 251 | if ((progif & 1) == 0) |
253 | progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG); |
| 252 | { |
254 | if ((progif & 1) == 0) |
| 253 | dev->resource[0].start = 0x1F0; |
255 | { |
| Line 309... | Line 311... | ||
| 309 | 311 | /* We found a fine healthy device, go go go... */ |
|
| Line 310... | Line 312... | ||
| 310 | return 0; |
312 | |
| 311 | }; |
313 | return 0; |
| Line 312... | Line 314... | ||
| 312 | 314 | }; |
|
| 313 | static pci_dev_t* pci_scan_device(u32_t busnr, int devfn) |
315 | |
| 314 | { |
316 | static pci_dev_t* pci_scan_device(u32 busnr, int devfn) |
| Line 315... | Line 317... | ||
| 315 | pci_dev_t *dev; |
317 | { |
| 316 | 318 | pci_dev_t *dev; |
|
| Line 317... | Line 319... | ||
| 317 | u32_t id; |
319 | |
| Line 318... | Line 320... | ||
| 318 | u8_t hdr; |
320 | u32 id; |
| Line 370... | Line 372... | ||
| 370 | 372 | }; |
|
| Line 371... | Line 373... | ||
| 371 | 373 | ||
| 372 | 374 | ||
| 373 | 375 | ||
| Line 374... | Line 376... | ||
| 374 | int pci_scan_slot(u32_t bus, int devfn) |
376 | |
| 375 | { |
377 | int _pci_scan_slot(u32 bus, int devfn) |
| Line 478... | Line 480... | ||
| 478 | 480 | ||
| 479 | int enum_pci_devices() |
481 | |
| 480 | { |
482 | int enum_pci_devices() |
| 481 | pci_dev_t *dev; |
483 | { |
| 482 | u32_t last_bus; |
484 | pci_dev_t *dev; |
| Line 483... | Line 485... | ||
| 483 | u32_t bus = 0 , devfn = 0; |
485 | u32 last_bus; |
| Line 491... | Line 493... | ||
| 491 | 493 | return -1; |
|
| Line 492... | Line 494... | ||
| 492 | for(;bus <= last_bus; bus++) |
494 | |
| 493 | { |
495 | for(;bus <= last_bus; bus++) |
| 494 | for (devfn = 0; devfn < 0x100; devfn += 8) |
496 | { |
| 495 | pci_scan_slot(bus, devfn); |
497 | for (devfn = 0; devfn < 0x100; devfn += 8) |
| Line 496... | Line 498... | ||
| 496 | 498 | _pci_scan_slot(bus, devfn); |
|
| 497 | 499 | ||
| 498 | } |
500 | |
| Line 569... | Line 571... | ||
| 569 | return NULL; |
571 | } |
| 570 | }; |
572 | return NULL; |
| 571 | 573 | }; |
|
| Line 572... | Line 574... | ||
| 572 | 574 | ||
| 573 | struct pci_dev * pci_get_bus_and_slot(unsigned int bus, unsigned int devfn) |
575 | |
| 574 | { |
576 | struct pci_dev * _pci_get_bus_and_slot(unsigned int bus, unsigned int devfn) |
| Line 575... | Line 577... | ||
| 575 | pci_dev_t *dev; |
577 | { |
| 576 | 578 | pci_dev_t *dev; |
|
| Line 662... | Line 664... | ||
| 662 | IO_COND(addr, /* nothing */, iounmap(addr)); |
664 | { |
| 663 | } |
665 | IO_COND(addr, /* nothing */, iounmap(addr)); |
| 664 | 666 | } |
|
| Line 665... | Line -... | ||
| 665 | - | ||
| 666 | struct pci_bus_region { |
- | |
| 667 | resource_size_t start; |
- | |
| 668 | resource_size_t end; |
- | |
| 669 | }; |
- | |
| 670 | - | ||
| 671 | static inline void |
- | |
| 672 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
- | |
| 673 | struct resource *res) |
- | |
| 674 | { |
- | |
| 675 | region->start = res->start; |
- | |
| 676 | region->end = res->end; |
- | |
| Line 677... | Line 667... | ||
| 677 | } |
667 | |
| 678 | 668 | ||
| 679 | 669 | ||
| Line 685... | Line 675... | ||
| 685 | 675 | u32 rom_addr; |
|
| Line 686... | Line 676... | ||
| 686 | if (!res->flags) |
676 | |
| 687 | return -1; |
677 | if (!res->flags) |
| Line 688... | Line 678... | ||
| 688 | 678 | return -1; |
|
| 689 | pcibios_resource_to_bus(pdev, ®ion, res); |
679 | |
| 690 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
680 | _pcibios_resource_to_bus(pdev, ®ion, res); |
| 691 | rom_addr &= ~PCI_ROM_ADDRESS_MASK; |
681 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
| 692 | rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE; |
682 | rom_addr &= ~PCI_ROM_ADDRESS_MASK; |
| 693 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); |
683 | rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE; |
| Line 781... | Line 771... | ||
| 781 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
771 | (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) { |
| 782 | return (void __iomem *)(unsigned long) |
772 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
| 783 | pci_resource_start(pdev, PCI_ROM_RESOURCE); |
773 | return (void __iomem *)(unsigned long) |
| 784 | } else { |
774 | pci_resource_start(pdev, PCI_ROM_RESOURCE); |
| 785 | /* assign the ROM an address if it doesn't have one */ |
775 | } else { |
| 786 | // if (res->parent == NULL && |
- | |
| 787 | // pci_assign_resource(pdev,PCI_ROM_RESOURCE)) |
- | |
| 788 | return NULL; |
- | |
| 789 | // start = pci_resource_start(pdev, PCI_ROM_RESOURCE); |
- | |
| 790 | // *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
- | |
| 791 | // if (*size == 0) |
- | |
| 792 | // return NULL; |
776 | start = (loff_t)0xC0000; |
| 793 | 777 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
|
| 794 | /* Enable ROM space decodes */ |
778 | |
| 795 | // if (pci_enable_rom(pdev)) |
- | |
| 796 | // return NULL; |
- | |
| 797 | } |
- | |
| 798 | } |
779 | } |
| 799 | 780 | } |
|
| Line 800... | Line 781... | ||
| 800 | rom = ioremap(start, *size); |
781 | |
| 801 | if (!rom) { |
782 | rom = ioremap(start, *size); |
| Line 829... | Line 810... | ||
| 829 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW))) |
810 | /* Disable again before continuing, leave enabled if pci=rom */ |
| 830 | pci_disable_rom(pdev); |
811 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW))) |
| 831 | } |
812 | pci_disable_rom(pdev); |
| 832 | 813 | } |
|
| Line 833... | Line -... | ||
| 833 | #if 0 |
- | |
| 834 | void pcibios_set_master(struct pci_dev *dev) |
- | |
| 835 | { |
- | |
| 836 | u8 lat; |
- | |
| 837 | - | ||
| 838 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
- | |
| 839 | if (pci_is_pcie(dev)) |
- | |
| 840 | return; |
- | |
| 841 | - | ||
| 842 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
- | |
| 843 | if (lat < 16) |
- | |
| 844 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; |
- | |
| 845 | else if (lat > pcibios_max_latency) |
- | |
| 846 | lat = pcibios_max_latency; |
- | |
| 847 | else |
- | |
| 848 | return; |
- | |
| 849 | dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat); |
- | |
| 850 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
- | |
| 851 | } |
- | |
| 852 | #endif |
- | |
| 853 | - | ||
| 854 | - | ||
| 855 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
814 | |
| 856 | { |
815 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
| 857 | u16 old_cmd, cmd; |
816 | { |
| Line 858... | Line 817... | ||
| 858 | 817 | u16 old_cmd, cmd; |
|
| Line 868... | Line 827... | ||
| 868 | } |
827 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 869 | dev->is_busmaster = enable; |
828 | } |
| 870 | } |
829 | dev->is_busmaster = enable; |
| 871 | 830 | } |
|
| Line -... | Line 831... | ||
| - | 831 | ||
| - | 832 | ||
| - | 833 | /* pci_set_master - enables bus-mastering for device dev |
|
| - | 834 | * @dev: the PCI device to enable |
|
| - | 835 | * |
|
| - | 836 | * Enables bus-mastering on the device and calls pcibios_set_master() |
|
| - | 837 | * to do the needed arch specific settings. |
|
| 872 | void pci_set_master(struct pci_dev *dev) |
838 | */ |
| 873 | { |
839 | void pci_set_master(struct pci_dev *dev) |
| 874 | __pci_set_master(dev, true); |
840 | { |
| 875 | // pcibios_set_master(dev); |
841 | __pci_set_master(dev, true); |
| 876 | } |
842 | // pcibios_set_master(dev); |
| Line -... | Line 843... | ||
| - | 843 | } |
|
| - | 844 | ||
| - | 845 | /** |
|
| - | 846 | * pci_clear_master - disables bus-mastering for device dev |
|
| - | 847 | * @dev: the PCI device to disable |
|
| - | 848 | */ |
|
| - | 849 | void pci_clear_master(struct pci_dev *dev) |
|
| - | 850 | { |
|
| - | 851 | __pci_set_master(dev, false); |
|
| - | 852 | } |
|
| - | 853 | ||
| - | 854 | ||
| - | 855 | static inline int pcie_cap_version(const struct pci_dev *dev) |
|
| - | 856 | { |
|
| - | 857 | return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS; |
|
| - | 858 | } |
|
| - | 859 | ||
| - | 860 | static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) |
|
| - | 861 | { |
|
| - | 862 | return true; |
|
| - | 863 | } |
|
| - | 864 | ||
| - | 865 | static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev) |
|
| - | 866 | { |
|
| - | 867 | int type = pci_pcie_type(dev); |
|
| - | 868 | ||
| - | 869 | return pcie_cap_version(dev) > 1 || |
|
| - | 870 | type == PCI_EXP_TYPE_ROOT_PORT || |
|
| - | 871 | type == PCI_EXP_TYPE_ENDPOINT || |
|
| - | 872 | type == PCI_EXP_TYPE_LEG_END; |
|
| - | 873 | } |
|
| - | 874 | ||
| - | 875 | static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) |
|
| - | 876 | { |
|
| - | 877 | int type = pci_pcie_type(dev); |
|
| - | 878 | ||
| - | 879 | return pcie_cap_version(dev) > 1 || |
|
| - | 880 | type == PCI_EXP_TYPE_ROOT_PORT || |
|
| - | 881 | (type == PCI_EXP_TYPE_DOWNSTREAM && |
|
| - | 882 | dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT); |
|
| - | 883 | } |
|
| - | 884 | ||
| - | 885 | static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) |
|
| - | 886 | { |
|
| - | 887 | int type = pci_pcie_type(dev); |
|
| - | 888 | ||
| - | 889 | return pcie_cap_version(dev) > 1 || |
|
| - | 890 | type == PCI_EXP_TYPE_ROOT_PORT || |
|
| - | 891 | type == PCI_EXP_TYPE_RC_EC; |
|
| - | 892 | } |
|
| - | 893 | ||
| - | 894 | static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) |
|
| - | 895 | { |
|
| - | 896 | if (!pci_is_pcie(dev)) |
|
| - | 897 | return false; |
|
| - | 898 | ||
| - | 899 | switch (pos) { |
|
| - | 900 | case PCI_EXP_FLAGS_TYPE: |
|
| - | 901 | return true; |
|
| - | 902 | case PCI_EXP_DEVCAP: |
|
| - | 903 | case PCI_EXP_DEVCTL: |
|
| - | 904 | case PCI_EXP_DEVSTA: |
|
| - | 905 | return pcie_cap_has_devctl(dev); |
|
| - | 906 | case PCI_EXP_LNKCAP: |
|
| - | 907 | case PCI_EXP_LNKCTL: |
|
| - | 908 | case PCI_EXP_LNKSTA: |
|
| - | 909 | return pcie_cap_has_lnkctl(dev); |
|
| - | 910 | case PCI_EXP_SLTCAP: |
|
| - | 911 | case PCI_EXP_SLTCTL: |
|
| - | 912 | case PCI_EXP_SLTSTA: |
|
| - | 913 | return pcie_cap_has_sltctl(dev); |
|
| - | 914 | case PCI_EXP_RTCTL: |
|
| - | 915 | case PCI_EXP_RTCAP: |
|
| - | 916 | case PCI_EXP_RTSTA: |
|
| - | 917 | return pcie_cap_has_rtctl(dev); |
|
| - | 918 | case PCI_EXP_DEVCAP2: |
|
| - | 919 | case PCI_EXP_DEVCTL2: |
|
| - | 920 | case PCI_EXP_LNKCAP2: |
|
| - | 921 | case PCI_EXP_LNKCTL2: |
|
| - | 922 | case PCI_EXP_LNKSTA2: |
|
| - | 923 | return pcie_cap_version(dev) > 1; |
|
| - | 924 | default: |
|
| - | 925 | return false; |
|
| - | 926 | } |
|
| - | 927 | } |
|
| - | 928 | ||
| - | 929 | /* |
|
| - | 930 | * Note that these accessor functions are only for the "PCI Express |
|
| - | 931 | * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the |
|
| - | 932 | * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) |
|
| - | 933 | */ |
|
| - | 934 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) |
|
| - | 935 | { |
|
| - | 936 | int ret; |
|
| - | 937 | ||
| - | 938 | *val = 0; |
|
| Line -... | Line 939... | ||
| - | 939 | if (pos & 1) |
|
| - | 940 | return -EINVAL; |
|
| - | 941 | ||
| - | 942 | if (pcie_capability_reg_implemented(dev, pos)) { |
|
| - | 943 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); |
|
| - | 944 | /* |
|
| - | 945 | * Reset *val to 0 if pci_read_config_word() fails, it may |
|
| - | 946 | * have been written as 0xFFFF if hardware error happens |
|
| - | 947 | * during pci_read_config_word(). |
|
| - | 948 | */ |
|
| - | 949 | if (ret) |
|
| - | 950 | *val = 0; |
|
| - | 951 | return ret; |
|
| - | 952 | } |
|
| - | 953 | ||
| - | 954 | /* |
|
| - | 955 | * For Functions that do not implement the Slot Capabilities, |
|
| - | 956 | * Slot Status, and Slot Control registers, these spaces must |
|
| - | 957 | * be hardwired to 0b, with the exception of the Presence Detect |
|
| - | 958 | * State bit in the Slot Status register of Downstream Ports, |
|
| - | 959 | * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) |
|
| - | 960 | */ |
|
| - | 961 | if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA && |
|
| - | 962 | pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { |
|
| - | 963 | *val = PCI_EXP_SLTSTA_PDS; |
|
| - | 964 | } |
|
| - | 965 | ||
| - | 966 | return 0; |
|
| - | 967 | } |
|
| - | 968 | EXPORT_SYMBOL(pcie_capability_read_word); |
|
| - | 969 | ||
| - | 970 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) |
|
| - | 971 | { |
|
| - | 972 | int ret; |
|
| - | 973 | ||
| - | 974 | *val = 0; |
|
| - | 975 | if (pos & 3) |
|
| - | 976 | return -EINVAL; |
|
| - | 977 | ||
| - | 978 | if (pcie_capability_reg_implemented(dev, pos)) { |
|
| - | 979 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); |
|
| - | 980 | /* |
|
| - | 981 | * Reset *val to 0 if pci_read_config_dword() fails, it may |
|
| - | 982 | * have been written as 0xFFFFFFFF if hardware error happens |
|
| - | 983 | * during pci_read_config_dword(). |
|
| - | 984 | */ |
|
| - | 985 | if (ret) |
|
| - | 986 | *val = 0; |
|
| - | 987 | return ret; |
|
| - | 988 | } |
|
| - | 989 | ||
| - | 990 | if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL && |
|
| - | 991 | pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { |
|
| - | 992 | *val = PCI_EXP_SLTSTA_PDS; |
|
| - | 993 | } |
|
| - | 994 | ||
| - | 995 | return 0; |
|
| - | 996 | } |
|
| - | 997 | EXPORT_SYMBOL(pcie_capability_read_dword); |
|
| - | 998 | ||
| - | 999 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) |
|
| - | 1000 | { |
|
| - | 1001 | if (pos & 1) |
|
| - | 1002 | return -EINVAL; |
|
| - | 1003 | ||
| - | 1004 | if (!pcie_capability_reg_implemented(dev, pos)) |
|
| - | 1005 | return 0; |
|
| - | 1006 | ||
| - | 1007 | return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); |
|
| - | 1008 | } |
|
| - | 1009 | EXPORT_SYMBOL(pcie_capability_write_word); |
|
| - | 1010 | ||
| - | 1011 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) |
|
| - | 1012 | { |
|
| - | 1013 | if (pos & 3) |
|
| - | 1014 | return -EINVAL; |
|
| - | 1015 | ||
| - | 1016 | if (!pcie_capability_reg_implemented(dev, pos)) |
|
| - | 1017 | return 0; |
|
| - | 1018 | ||
| - | 1019 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val); |
|
| - | 1020 | } |
|
| - | 1021 | EXPORT_SYMBOL(pcie_capability_write_dword); |
|
| - | 1022 | ||
| - | 1023 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, |
|
| - | 1024 | u16 clear, u16 set) |
|
| - | 1025 | { |
|
| - | 1026 | int ret; |
|
| - | 1027 | u16 val; |
|
| - | 1028 | ||
| - | 1029 | ret = pcie_capability_read_word(dev, pos, &val); |
|
| - | 1030 | if (!ret) { |
|
| - | 1031 | val &= ~clear; |
|
| - | 1032 | val |= set; |
|
| - | 1033 | ret = pcie_capability_write_word(dev, pos, val); |
|
| - | 1034 | } |
|
| - | 1035 | ||
| - | 1036 | return ret; |
|
| - | 1037 | } |
|
| - | 1038 | ||
| - | 1039 | ||
| - | 1040 | ||
| - | 1041 | int pcie_get_readrq(struct pci_dev *dev) |
|
| - | 1042 | { |
|
| - | 1043 | u16 ctl; |
|
| - | 1044 | ||
| - | 1045 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
|
| - | 1046 | ||
| - | 1047 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
|
| - | 1048 | } |
|
| - | 1049 | EXPORT_SYMBOL(pcie_get_readrq); |
|
| - | 1050 | ||
| - | 1051 | /** |
|
| - | 1052 | * pcie_set_readrq - set PCI Express maximum memory read request |
|
| - | 1053 | * @dev: PCI device to query |
|
| - | 1054 | * @rq: maximum memory read count in bytes |
|
| - | 1055 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
|
| - | 1056 | * |
|
| - | 1057 | * If possible sets maximum memory read request in bytes |
|
| - | 1058 | */ |
|
| - | 1059 | int pcie_set_readrq(struct pci_dev *dev, int rq) |
|
| - | 1060 | { |
|
| - | 1061 | u16 v; |
|
| - | 1062 | ||
| - | 1063 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
|
| - | 1064 | return -EINVAL; |
|
| - | 1065 | ||
| - | 1066 | v = (ffs(rq) - 8) << 12; |
|
| - | 1067 | ||