WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/vce_v2_0.c


/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * Authors: Christian König 
 */
 
#include 
#include 
#include "radeon.h"
#include "radeon_asic.h"
#include "cikd.h"
 
#define VCE_V2_0_FW_SIZE	(256 * 1024)
#define VCE_V2_0_STACK_SIZE	(64 * 1024)
#define VCE_V2_0_DATA_SIZE	(23552 * RADEON_MAX_VCE_HANDLES)
 
static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
{
	u32 tmp;
 
	if (gated) {
		tmp = RREG32(VCE_CLOCK_GATING_B);
		tmp |= 0xe70000;
		WREG32(VCE_CLOCK_GATING_B, tmp);
 
		tmp = RREG32(VCE_UENC_CLOCK_GATING);
		tmp |= 0xff000000;
		WREG32(VCE_UENC_CLOCK_GATING, tmp);
 
		tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
		tmp &= ~0x3fc;
		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
 
		WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
    } else {
		tmp = RREG32(VCE_CLOCK_GATING_B);
		tmp |= 0xe7;
		tmp &= ~0xe70000;
		WREG32(VCE_CLOCK_GATING_B, tmp);
 
		tmp = RREG32(VCE_UENC_CLOCK_GATING);
		tmp |= 0x1fe000;
		tmp &= ~0xff000000;
		WREG32(VCE_UENC_CLOCK_GATING, tmp);
 
		tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
		tmp |= 0x3fc;
		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
	}
}
 
static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated)
{
	u32 orig, tmp;
 
	tmp = RREG32(VCE_CLOCK_GATING_B);
	tmp &= ~0x00060006;
	if (gated) {
		tmp |= 0xe10000;
	} else {
		tmp |= 0xe1;
		tmp &= ~0xe10000;
	}
	WREG32(VCE_CLOCK_GATING_B, tmp);
 
	orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
	tmp &= ~0x1fe000;
	tmp &= ~0xff000000;
	if (tmp != orig)
		WREG32(VCE_UENC_CLOCK_GATING, tmp);
 
	orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
	tmp &= ~0x3fc;
	if (tmp != orig)
		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
 
	if (gated)
		WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
}
 
static void vce_v2_0_disable_cg(struct radeon_device *rdev)
{
	WREG32(VCE_CGTT_CLK_OVERRIDE, 7);
}
 
void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)
{
	bool sw_cg = false;
 
	if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
		if (sw_cg)
			vce_v2_0_set_sw_cg(rdev, true);
		else
			vce_v2_0_set_dyn_cg(rdev, true);
	} else {
		vce_v2_0_disable_cg(rdev);
 
		if (sw_cg)
			vce_v2_0_set_sw_cg(rdev, false);
		else
			vce_v2_0_set_dyn_cg(rdev, false);
	}
}
 
static void vce_v2_0_init_cg(struct radeon_device *rdev)
{
	u32 tmp;
 
	tmp = RREG32(VCE_CLOCK_GATING_A);
	tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK | CGC_CLK_GATER_OFF_DLY_TIMER_MASK);
	tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4));
	tmp |= CGC_UENC_WAIT_AWAKE;
	WREG32(VCE_CLOCK_GATING_A, tmp);
 
	tmp = RREG32(VCE_UENC_CLOCK_GATING);
	tmp &= ~(CLOCK_ON_DELAY_MASK | CLOCK_OFF_DELAY_MASK);
	tmp |= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4));
	WREG32(VCE_UENC_CLOCK_GATING, tmp);
 
	tmp = RREG32(VCE_CLOCK_GATING_B);
	tmp |= 0x10;
	tmp &= ~0x100000;
	WREG32(VCE_CLOCK_GATING_B, tmp);
}
 
unsigned vce_v2_0_bo_size(struct radeon_device *rdev)
{
	WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE);
	return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE;
}
 
int vce_v2_0_resume(struct radeon_device *rdev)
{
	uint64_t addr = rdev->vce.gpu_addr;
	uint32_t size;
 
	WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
	WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
	WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
	WREG32(VCE_CLOCK_GATING_B, 0xf7);
 
	WREG32(VCE_LMI_CTRL, 0x00398000);
	WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
	WREG32(VCE_LMI_SWAP_CNTL, 0);
	WREG32(VCE_LMI_SWAP_CNTL1, 0);
	WREG32(VCE_LMI_VM_CTRL, 0);
 
	WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
 
	addr &= 0xff;
	size = VCE_V2_0_FW_SIZE;
	WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
	WREG32(VCE_VCPU_CACHE_SIZE0, size);
 
	addr += size;
	size = VCE_V2_0_STACK_SIZE;
	WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
	WREG32(VCE_VCPU_CACHE_SIZE1, size);
 
	addr += size;
	size = VCE_V2_0_DATA_SIZE;
	WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
	WREG32(VCE_VCPU_CACHE_SIZE2, size);
 
	WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
 
	WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,
		 ~VCE_SYS_INT_TRAP_INTERRUPT_EN);
 
	vce_v2_0_init_cg(rdev);
 
	return 0;
}

Rev 5078	Rev 6104
1	/*	1	/*
2	* Copyright 2013 Advanced Micro Devices, Inc.	2	* Copyright 2013 Advanced Micro Devices, Inc.
3	* All Rights Reserved.	3	* All Rights Reserved.
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the	6	* copy of this software and associated documentation files (the
7	* "Software"), to deal in the Software without restriction, including	7	* "Software"), to deal in the Software without restriction, including
8	* without limitation the rights to use, copy, modify, merge, publish,	8	* without limitation the rights to use, copy, modify, merge, publish,
9	* distribute, sub license, and/or sell copies of the Software, and to	9	* distribute, sub license, and/or sell copies of the Software, and to
10	* permit persons to whom the Software is furnished to do so, subject to	10	* permit persons to whom the Software is furnished to do so, subject to
11	* the following conditions:	11	* the following conditions:
12	*	12	*
13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19	* USE OR OTHER DEALINGS IN THE SOFTWARE.	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
20	*	20	*
21	* The above copyright notice and this permission notice (including the	21	* The above copyright notice and this permission notice (including the
22	* next paragraph) shall be included in all copies or substantial portions	22	* next paragraph) shall be included in all copies or substantial portions
23	* of the Software.	23	* of the Software.
24	*	24	*
25	* Authors: Christian König	25	* Authors: Christian König
26	*/	26	*/
27		27
28	#include	28	#include
29	#include	29	#include
30	#include "radeon.h"	30	#include "radeon.h"
31	#include "radeon_asic.h"	31	#include "radeon_asic.h"
32	#include "cikd.h"	32	#include "cikd.h"
-		33
-		34	#define VCE_V2_0_FW_SIZE (256 * 1024)
-		35	#define VCE_V2_0_STACK_SIZE (64 * 1024)
-		36	#define VCE_V2_0_DATA_SIZE (23552 * RADEON_MAX_VCE_HANDLES)
33		37
34	static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)	38	static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
35	{	39	{
36	u32 tmp;	40	u32 tmp;
37		41
38	if (gated) {	42	if (gated) {
39	tmp = RREG32(VCE_CLOCK_GATING_B);	43	tmp = RREG32(VCE_CLOCK_GATING_B);
40	tmp \|= 0xe70000;	44	tmp \|= 0xe70000;
41	WREG32(VCE_CLOCK_GATING_B, tmp);	45	WREG32(VCE_CLOCK_GATING_B, tmp);
42		46
43	tmp = RREG32(VCE_UENC_CLOCK_GATING);	47	tmp = RREG32(VCE_UENC_CLOCK_GATING);
44	tmp \|= 0xff000000;	48	tmp \|= 0xff000000;
45	WREG32(VCE_UENC_CLOCK_GATING, tmp);	49	WREG32(VCE_UENC_CLOCK_GATING, tmp);
46		50
47	tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);	51	tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
48	tmp &= ~0x3fc;	52	tmp &= ~0x3fc;
49	WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);	53	WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
50		54
51	WREG32(VCE_CGTT_CLK_OVERRIDE, 0);	55	WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
52	} else {	56	} else {
53	tmp = RREG32(VCE_CLOCK_GATING_B);	57	tmp = RREG32(VCE_CLOCK_GATING_B);
54	tmp \|= 0xe7;	58	tmp \|= 0xe7;
55	tmp &= ~0xe70000;	59	tmp &= ~0xe70000;
56	WREG32(VCE_CLOCK_GATING_B, tmp);	60	WREG32(VCE_CLOCK_GATING_B, tmp);
57		61
58	tmp = RREG32(VCE_UENC_CLOCK_GATING);	62	tmp = RREG32(VCE_UENC_CLOCK_GATING);
59	tmp \|= 0x1fe000;	63	tmp \|= 0x1fe000;
60	tmp &= ~0xff000000;	64	tmp &= ~0xff000000;
61	WREG32(VCE_UENC_CLOCK_GATING, tmp);	65	WREG32(VCE_UENC_CLOCK_GATING, tmp);
62		66
63	tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);	67	tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
64	tmp \|= 0x3fc;	68	tmp \|= 0x3fc;
65	WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);	69	WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
66	}	70	}
67	}	71	}
68		72
69	static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated)	73	static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated)
70	{	74	{
71	u32 orig, tmp;	75	u32 orig, tmp;
72		76
73	tmp = RREG32(VCE_CLOCK_GATING_B);	77	tmp = RREG32(VCE_CLOCK_GATING_B);
74	tmp &= ~0x00060006;	78	tmp &= ~0x00060006;
75	if (gated) {	79	if (gated) {
76	tmp \|= 0xe10000;	80	tmp \|= 0xe10000;
77	} else {	81	} else {
78	tmp \|= 0xe1;	82	tmp \|= 0xe1;
79	tmp &= ~0xe10000;	83	tmp &= ~0xe10000;
80	}	84	}
81	WREG32(VCE_CLOCK_GATING_B, tmp);	85	WREG32(VCE_CLOCK_GATING_B, tmp);
82		86
83	orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);	87	orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
84	tmp &= ~0x1fe000;	88	tmp &= ~0x1fe000;
85	tmp &= ~0xff000000;	89	tmp &= ~0xff000000;
86	if (tmp != orig)	90	if (tmp != orig)
87	WREG32(VCE_UENC_CLOCK_GATING, tmp);	91	WREG32(VCE_UENC_CLOCK_GATING, tmp);
88		92
89	orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);	93	orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
90	tmp &= ~0x3fc;	94	tmp &= ~0x3fc;
91	if (tmp != orig)	95	if (tmp != orig)
92	WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);	96	WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
93		97
94	if (gated)	98	if (gated)
95	WREG32(VCE_CGTT_CLK_OVERRIDE, 0);	99	WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
96	}	100	}
97		101
98	static void vce_v2_0_disable_cg(struct radeon_device *rdev)	102	static void vce_v2_0_disable_cg(struct radeon_device *rdev)
99	{	103	{
100	WREG32(VCE_CGTT_CLK_OVERRIDE, 7);	104	WREG32(VCE_CGTT_CLK_OVERRIDE, 7);
101	}	105	}
102		106
103	void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)	107	void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)
104	{	108	{
105	bool sw_cg = false;	109	bool sw_cg = false;
106		110
107	if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {	111	if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
108	if (sw_cg)	112	if (sw_cg)
109	vce_v2_0_set_sw_cg(rdev, true);	113	vce_v2_0_set_sw_cg(rdev, true);
110	else	114	else
111	vce_v2_0_set_dyn_cg(rdev, true);	115	vce_v2_0_set_dyn_cg(rdev, true);
112	} else {	116	} else {
113	vce_v2_0_disable_cg(rdev);	117	vce_v2_0_disable_cg(rdev);
114		118
115	if (sw_cg)	119	if (sw_cg)
116	vce_v2_0_set_sw_cg(rdev, false);	120	vce_v2_0_set_sw_cg(rdev, false);
117	else	121	else
118	vce_v2_0_set_dyn_cg(rdev, false);	122	vce_v2_0_set_dyn_cg(rdev, false);
119	}	123	}
120	}	124	}
121		125
122	static void vce_v2_0_init_cg(struct radeon_device *rdev)	126	static void vce_v2_0_init_cg(struct radeon_device *rdev)
123	{	127	{
124	u32 tmp;	128	u32 tmp;
125		129
126	tmp = RREG32(VCE_CLOCK_GATING_A);	130	tmp = RREG32(VCE_CLOCK_GATING_A);
127	tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK \| CGC_CLK_GATER_OFF_DLY_TIMER_MASK);	131	tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK \| CGC_CLK_GATER_OFF_DLY_TIMER_MASK);
128	tmp \|= (CGC_CLK_GATE_DLY_TIMER(0) \| CGC_CLK_GATER_OFF_DLY_TIMER(4));	132	tmp \|= (CGC_CLK_GATE_DLY_TIMER(0) \| CGC_CLK_GATER_OFF_DLY_TIMER(4));
129	tmp \|= CGC_UENC_WAIT_AWAKE;	133	tmp \|= CGC_UENC_WAIT_AWAKE;
130	WREG32(VCE_CLOCK_GATING_A, tmp);	134	WREG32(VCE_CLOCK_GATING_A, tmp);
131		135
132	tmp = RREG32(VCE_UENC_CLOCK_GATING);	136	tmp = RREG32(VCE_UENC_CLOCK_GATING);
133	tmp &= ~(CLOCK_ON_DELAY_MASK \| CLOCK_OFF_DELAY_MASK);	137	tmp &= ~(CLOCK_ON_DELAY_MASK \| CLOCK_OFF_DELAY_MASK);
134	tmp \|= (CLOCK_ON_DELAY(0) \| CLOCK_OFF_DELAY(4));	138	tmp \|= (CLOCK_ON_DELAY(0) \| CLOCK_OFF_DELAY(4));
135	WREG32(VCE_UENC_CLOCK_GATING, tmp);	139	WREG32(VCE_UENC_CLOCK_GATING, tmp);
136		140
137	tmp = RREG32(VCE_CLOCK_GATING_B);	141	tmp = RREG32(VCE_CLOCK_GATING_B);
138	tmp \|= 0x10;	142	tmp \|= 0x10;
139	tmp &= ~0x100000;	143	tmp &= ~0x100000;
140	WREG32(VCE_CLOCK_GATING_B, tmp);	144	WREG32(VCE_CLOCK_GATING_B, tmp);
141	}	145	}
-		146
-		147	unsigned vce_v2_0_bo_size(struct radeon_device *rdev)
-		148	{
-		149	WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE);
-		150	return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE;
-		151	}
142		152
143	int vce_v2_0_resume(struct radeon_device *rdev)	153	int vce_v2_0_resume(struct radeon_device *rdev)
144	{	154	{
145	uint64_t addr = rdev->vce.gpu_addr;	155	uint64_t addr = rdev->vce.gpu_addr;
146	uint32_t size;	156	uint32_t size;
147		157
148	WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));	158	WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
149	WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);	159	WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
150	WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);	160	WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
151	WREG32(VCE_CLOCK_GATING_B, 0xf7);	161	WREG32(VCE_CLOCK_GATING_B, 0xf7);
152		162
153	WREG32(VCE_LMI_CTRL, 0x00398000);	163	WREG32(VCE_LMI_CTRL, 0x00398000);
154	WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);	164	WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
155	WREG32(VCE_LMI_SWAP_CNTL, 0);	165	WREG32(VCE_LMI_SWAP_CNTL, 0);
156	WREG32(VCE_LMI_SWAP_CNTL1, 0);	166	WREG32(VCE_LMI_SWAP_CNTL1, 0);
157	WREG32(VCE_LMI_VM_CTRL, 0);	167	WREG32(VCE_LMI_VM_CTRL, 0);
158		168
-		169	WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
-		170
-		171	addr &= 0xff;
159	size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);	172	size = VCE_V2_0_FW_SIZE;
160	WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);	173	WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
161	WREG32(VCE_VCPU_CACHE_SIZE0, size);	174	WREG32(VCE_VCPU_CACHE_SIZE0, size);
162		175
163	addr += size;	176	addr += size;
164	size = RADEON_VCE_STACK_SIZE;	177	size = VCE_V2_0_STACK_SIZE;
165	WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);	178	WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
166	WREG32(VCE_VCPU_CACHE_SIZE1, size);	179	WREG32(VCE_VCPU_CACHE_SIZE1, size);
167		180
168	addr += size;	181	addr += size;
169	size = RADEON_VCE_HEAP_SIZE;	182	size = VCE_V2_0_DATA_SIZE;
170	WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);	183	WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
171	WREG32(VCE_VCPU_CACHE_SIZE2, size);	184	WREG32(VCE_VCPU_CACHE_SIZE2, size);
172		185
173	WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);	186	WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
174		187
175	WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,	188	WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,
176	~VCE_SYS_INT_TRAP_INTERRUPT_EN);	189	~VCE_SYS_INT_TRAP_INTERRUPT_EN);
177		190
178	vce_v2_0_init_cg(rdev);	191	vce_v2_0_init_cg(rdev);
179		192
180	return 0;	193	return 0;
181	}	194	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/vce_v2_0.c – Rev 5078 → 6104