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Rev 5078 | Rev 6104 | ||
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Line 29... | Line 29... | ||
29 | #include |
29 | #include |
30 | #include "radeon.h" |
30 | #include "radeon.h" |
31 | #include "radeon_asic.h" |
31 | #include "radeon_asic.h" |
32 | #include "cikd.h" |
32 | #include "cikd.h" |
Line -... | Line 33... | ||
- | 33 | ||
- | 34 | #define VCE_V2_0_FW_SIZE (256 * 1024) |
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- | 35 | #define VCE_V2_0_STACK_SIZE (64 * 1024) |
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- | 36 | #define VCE_V2_0_DATA_SIZE (23552 * RADEON_MAX_VCE_HANDLES) |
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33 | 37 | ||
34 | static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) |
38 | static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) |
35 | { |
39 | { |
Line 36... | Line 40... | ||
36 | u32 tmp; |
40 | u32 tmp; |
Line 138... | Line 142... | ||
138 | tmp |= 0x10; |
142 | tmp |= 0x10; |
139 | tmp &= ~0x100000; |
143 | tmp &= ~0x100000; |
140 | WREG32(VCE_CLOCK_GATING_B, tmp); |
144 | WREG32(VCE_CLOCK_GATING_B, tmp); |
141 | } |
145 | } |
Line -... | Line 146... | ||
- | 146 | ||
- | 147 | unsigned vce_v2_0_bo_size(struct radeon_device *rdev) |
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- | 148 | { |
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- | 149 | WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE); |
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- | 150 | return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE; |
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- | 151 | } |
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142 | 152 | ||
143 | int vce_v2_0_resume(struct radeon_device *rdev) |
153 | int vce_v2_0_resume(struct radeon_device *rdev) |
144 | { |
154 | { |
145 | uint64_t addr = rdev->vce.gpu_addr; |
155 | uint64_t addr = rdev->vce.gpu_addr; |
Line 154... | Line 164... | ||
154 | WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); |
164 | WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); |
155 | WREG32(VCE_LMI_SWAP_CNTL, 0); |
165 | WREG32(VCE_LMI_SWAP_CNTL, 0); |
156 | WREG32(VCE_LMI_SWAP_CNTL1, 0); |
166 | WREG32(VCE_LMI_SWAP_CNTL1, 0); |
157 | WREG32(VCE_LMI_VM_CTRL, 0); |
167 | WREG32(VCE_LMI_VM_CTRL, 0); |
Line 158... | Line 168... | ||
158 | 168 | ||
- | 169 | WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8); |
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- | 170 | ||
- | 171 | addr &= 0xff; |
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159 | size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size); |
172 | size = VCE_V2_0_FW_SIZE; |
160 | WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); |
173 | WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); |
Line 161... | Line 174... | ||
161 | WREG32(VCE_VCPU_CACHE_SIZE0, size); |
174 | WREG32(VCE_VCPU_CACHE_SIZE0, size); |
162 | 175 | ||
163 | addr += size; |
176 | addr += size; |
164 | size = RADEON_VCE_STACK_SIZE; |
177 | size = VCE_V2_0_STACK_SIZE; |
Line 165... | Line 178... | ||
165 | WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); |
178 | WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); |
166 | WREG32(VCE_VCPU_CACHE_SIZE1, size); |
179 | WREG32(VCE_VCPU_CACHE_SIZE1, size); |
167 | 180 | ||
168 | addr += size; |
181 | addr += size; |
Line 169... | Line 182... | ||
169 | size = RADEON_VCE_HEAP_SIZE; |
182 | size = VCE_V2_0_DATA_SIZE; |