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Rev 5078 Rev 6104
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#include
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#include
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#include "radeon.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "radeon_asic.h"
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#include "cikd.h"
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#include "cikd.h"
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#define VCE_V2_0_FW_SIZE	(256 * 1024)
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#define VCE_V2_0_STACK_SIZE	(64 * 1024)
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#define VCE_V2_0_DATA_SIZE	(23552 * RADEON_MAX_VCE_HANDLES)
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static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
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static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
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{
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{
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	u32 tmp;
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	u32 tmp;
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	tmp |= 0x10;
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	tmp |= 0x10;
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	tmp &= ~0x100000;
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	tmp &= ~0x100000;
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	WREG32(VCE_CLOCK_GATING_B, tmp);
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	WREG32(VCE_CLOCK_GATING_B, tmp);
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}
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}
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unsigned vce_v2_0_bo_size(struct radeon_device *rdev)
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{
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	WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE);
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	return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE;
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}
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int vce_v2_0_resume(struct radeon_device *rdev)
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int vce_v2_0_resume(struct radeon_device *rdev)
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{
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{
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	uint64_t addr = rdev->vce.gpu_addr;
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	uint64_t addr = rdev->vce.gpu_addr;
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	WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
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	WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
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	WREG32(VCE_LMI_SWAP_CNTL, 0);
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	WREG32(VCE_LMI_SWAP_CNTL, 0);
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	WREG32(VCE_LMI_SWAP_CNTL1, 0);
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	WREG32(VCE_LMI_SWAP_CNTL1, 0);
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	WREG32(VCE_LMI_VM_CTRL, 0);
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	WREG32(VCE_LMI_VM_CTRL, 0);
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	WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
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	addr &= 0xff;
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	size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
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	size = VCE_V2_0_FW_SIZE;
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	WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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	WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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	WREG32(VCE_VCPU_CACHE_SIZE0, size);
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	WREG32(VCE_VCPU_CACHE_SIZE0, size);
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	addr += size;
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	addr += size;
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	size = RADEON_VCE_STACK_SIZE;
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	size = VCE_V2_0_STACK_SIZE;
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	WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
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	WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
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	WREG32(VCE_VCPU_CACHE_SIZE1, size);
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	WREG32(VCE_VCPU_CACHE_SIZE1, size);
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	addr += size;
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	addr += size;
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	size = RADEON_VCE_HEAP_SIZE;
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	size = VCE_V2_0_DATA_SIZE;