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Rev 3192 Rev 3764
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#define TAHITI_RB_BITMAP_WIDTH_PER_SH  2
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#define TAHITI_RB_BITMAP_WIDTH_PER_SH  2
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- 
 
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#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003
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#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002
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#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001
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- 
 
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/* discrete uvd clocks */
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#define	CG_UPLL_FUNC_CNTL				0x634
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#	define UPLL_RESET_MASK				0x00000001
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#	define UPLL_SLEEP_MASK				0x00000002
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#	define UPLL_BYPASS_EN_MASK			0x00000004
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#	define UPLL_CTLREQ_MASK				0x00000008
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#	define UPLL_VCO_MODE_MASK			0x00000600
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#	define UPLL_REF_DIV_MASK			0x003F0000
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#	define UPLL_CTLACK_MASK				0x40000000
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#	define UPLL_CTLACK2_MASK			0x80000000
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#define	CG_UPLL_FUNC_CNTL_2				0x638
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#	define UPLL_PDIV_A(x)				((x) << 0)
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#	define UPLL_PDIV_A_MASK				0x0000007F
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#	define UPLL_PDIV_B(x)				((x) << 8)
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#	define UPLL_PDIV_B_MASK				0x00007F00
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#	define VCLK_SRC_SEL(x)				((x) << 20)
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#	define VCLK_SRC_SEL_MASK			0x01F00000
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#	define DCLK_SRC_SEL(x)				((x) << 25)
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#	define DCLK_SRC_SEL_MASK			0x3E000000
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#define	CG_UPLL_FUNC_CNTL_3				0x63C
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#	define UPLL_FB_DIV(x)				((x) << 0)
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#	define UPLL_FB_DIV_MASK				0x01FFFFFF
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#define	CG_UPLL_FUNC_CNTL_4                             0x644
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#	define UPLL_SPARE_ISPARE9			0x00020000
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#define	CG_UPLL_FUNC_CNTL_5				0x648
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#	define RESET_ANTI_MUX_MASK			0x00000200
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#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003
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#define	CG_UPLL_SPREAD_SPECTRUM				0x650
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#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002
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#	define SSEN_MASK				0x00000001
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#define	CG_MULT_THERMAL_STATUS					0x714
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#define	CG_MULT_THERMAL_STATUS					0x714
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#define SI_MAX_TCC_MASK          0xFFFF
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#define SI_MAX_TCC_MASK          0xFFFF
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#define VGA_HDP_CONTROL  				0x328
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#define VGA_HDP_CONTROL  				0x328
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#define		VGA_MEMORY_DISABLE				(1 << 4)
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#define CG_CLKPIN_CNTL                                    0x660
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#       define XTALIN_DIVIDE                              (1 << 1)
- 
 
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#define CG_CLKPIN_CNTL_2                                  0x664
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#define		VGA_MEMORY_DISABLE				(1 << 4)
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#       define MUX_TCLK_TO_XCLK                           (1 << 8)
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#define DMIF_ADDR_CONFIG  				0xBD4
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- 
 
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#define DMIF_ADDR_CALC  				0xC00
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#define	SRBM_STATUS				        0xE50
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#define		GRBM_RQ_PENDING 			(1 << 5)
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#define		VMC_BUSY 				(1 << 8)
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#define		MCB_BUSY 				(1 << 9)
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#define		MCB_NON_DISPLAY_BUSY 			(1 << 10)
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#define		MCC_BUSY 				(1 << 11)
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#define DMIF_ADDR_CONFIG  				0xBD4
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#define		MCD_BUSY 				(1 << 12)
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#define		SEM_BUSY 				(1 << 14)
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#define	SRBM_STATUS				        0xE50
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#define		IH_BUSY 				(1 << 17)
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#define		SOFT_RESET_ORB				(1 << 23)
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#define		SOFT_RESET_ORB				(1 << 23)
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#define	CC_SYS_RB_BACKEND_DISABLE			0xe80
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#define	CC_SYS_RB_BACKEND_DISABLE			0xe80
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#define	GC_USER_SYS_RB_BACKEND_DISABLE			0xe84
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- 
 
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#define	SRBM_STATUS2				        0x0EC4
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#define		DMA_BUSY 				(1 << 5)
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#define	GC_USER_SYS_RB_BACKEND_DISABLE			0xe84
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#define		DMA1_BUSY 				(1 << 6)
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#define VM_L2_CNTL					0x1400
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#define VM_L2_CNTL					0x1400
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#define		ENABLE_L2_CACHE					(1 << 0)
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#define		ENABLE_L2_CACHE					(1 << 0)
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#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
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#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
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#       define THREAD_TRACE_STOP                        (52 << 0)
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#       define THREAD_TRACE_STOP                        (52 << 0)
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#       define THREAD_TRACE_FLUSH                       (54 << 0)
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#       define THREAD_TRACE_FLUSH                       (54 << 0)
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#       define THREAD_TRACE_FINISH                      (55 << 0)
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#       define THREAD_TRACE_FINISH                      (55 << 0)
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- 
 
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/*
- 
 
 833 
 * UVD
- 
 
 834 
 */
- 
 
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#define UVD_UDEC_ADDR_CONFIG				0xEF4C
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#define UVD_UDEC_DB_ADDR_CONFIG				0xEF50
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#define UVD_UDEC_DBW_ADDR_CONFIG			0xEF54
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#define UVD_RBC_RB_RPTR					0xF690
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#define UVD_RBC_RB_WPTR					0xF694
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 840 
 
783 
/*
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/*
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 * PM4
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 * PM4
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 */
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786 
#define	PACKET_TYPE0	0
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787 
#define	PACKET_TYPE1	1
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788 
#define	PACKET_TYPE2	2
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#define	PACKET_TYPE3	3
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790 
 
 - 
 
791 
#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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792 
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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793 
#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
 843 
 */
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#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
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#define PACKET0(reg, n)	((RADEON_PACKET_TYPE0 << 30) |			\
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			 (((reg) >> 2) & 0xFFFF) |			\
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			 (((reg) >> 2) & 0xFFFF) |			\
797 
			 ((n) & 0x3FFF) << 16)
 846 
			 ((n) & 0x3FFF) << 16)
798 
#define CP_PACKET2			0x80000000
 847 
#define CP_PACKET2			0x80000000
799 
#define		PACKET2_PAD_SHIFT		0
 848 
#define		PACKET2_PAD_SHIFT		0
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#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
 849 
#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
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 850 
 
802 
#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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 852 
 
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#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
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#define PACKET3(op, n)	((RADEON_PACKET_TYPE3 << 30) |			\