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Rev 5179 Rev 5271
Line 2382... Line 2382...
2382 
	struct drm_display_mode *mode0 = NULL;
 2382 
	struct drm_display_mode *mode0 = NULL;
2383 
	struct drm_display_mode *mode1 = NULL;
 2383 
	struct drm_display_mode *mode1 = NULL;
2384 
	u32 num_heads = 0, lb_size;
 2384 
	u32 num_heads = 0, lb_size;
2385 
	int i;
 2385 
	int i;
Line -... Line 2386...
- 
 
 2386 
 
- 
 
 2387 
	if (!rdev->mode_info.mode_config_initialized)
- 
 
 2388 
		return;
2386 
 
 2389 
 
Line 2387... Line 2390...
2387 
	radeon_update_display_priority(rdev);
 2390 
	radeon_update_display_priority(rdev);
2388 
 
 2391 
 
2389 
	for (i = 0; i < rdev->num_crtc; i++) {
 2392 
	for (i = 0; i < rdev->num_crtc; i++) {
Line 3360... Line 3363...
3360 
 * IB stuff
 3363 
 * IB stuff
3361 
 */
 3364 
 */
3362 
void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 3365 
void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3363 
{
 3366 
{
3364 
	struct radeon_ring *ring = &rdev->ring[ib->ring];
 3367 
	struct radeon_ring *ring = &rdev->ring[ib->ring];
- 
 
 3368 
	unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
3365 
	u32 header;
 3369 
	u32 header;
Line 3366... Line 3370...
3366 
 
 3370 
 
3367 
	if (ib->is_const_ib) {
 3371 
	if (ib->is_const_ib) {
3368 
		/* set switch buffer packet before const IB */
 3372 
		/* set switch buffer packet before const IB */
Line 3395... Line 3399...
3395 
#ifdef __BIG_ENDIAN
 3399 
#ifdef __BIG_ENDIAN
3396 
			  (2 << 0) |
 3400 
			  (2 << 0) |
3397 
#endif
 3401 
#endif
3398 
			  (ib->gpu_addr & 0xFFFFFFFC));
 3402 
			  (ib->gpu_addr & 0xFFFFFFFC));
3399 
	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
 3403 
	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3400 
	radeon_ring_write(ring, ib->length_dw |
 3404 
	radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
3401 
			  (ib->vm ? (ib->vm->id << 24) : 0));
 - 
 
Line 3402... Line 3405...
3402 
 
 3405 
 
3403 
	if (!ib->is_const_ib) {
 3406 
	if (!ib->is_const_ib) {
3404 
		/* flush read cache over gart for this vmid */
 3407 
		/* flush read cache over gart for this vmid */
3405 
		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 3408 
		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3406 
		radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
 3409 
		radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3407 
		radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
 3410 
		radeon_ring_write(ring, vm_id);
3408 
		radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
 3411 
		radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3409 
		radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
 3412 
		radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3410 
				  PACKET3_TC_ACTION_ENA |
 3413 
				  PACKET3_TC_ACTION_ENA |
3411 
				  PACKET3_SH_KCACHE_ACTION_ENA |
 3414 
				  PACKET3_SH_KCACHE_ACTION_ENA |
Line 4682... Line 4685...
4682 
}
 4685 
}
Line 4683... Line 4686...
4683 
 
 4686 
 
4684 
int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
 4687 
int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
4685 
{
 4688 
{
4686 
	int ret = 0;
 4689 
	int ret = 0;
4687 
	u32 idx = 0;
 4690 
	u32 idx = 0, i;
Line 4688... Line 4691...
4688 
	struct radeon_cs_packet pkt;
 4691 
	struct radeon_cs_packet pkt;
4689 
 
 4692 
 
4690 
	do {
 4693 
	do {
4691 
		pkt.idx = idx;
 4694 
		pkt.idx = idx;
4692 
		pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
 4695 
		pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
4693 
		pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
 4696 
		pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
4694 
		pkt.one_reg_wr = 0;
 4697 
		pkt.one_reg_wr = 0;
4695 
		switch (pkt.type) {
 4698 
		switch (pkt.type) {
- 
 
 4699 
		case RADEON_PACKET_TYPE0:
- 
 
 4700 
			dev_err(rdev->dev, "Packet0 not allowed!\n");
- 
 
 4701 
			for (i = 0; i < ib->length_dw; i++) {
- 
 
 4702 
				if (i == idx)
- 
 
 4703 
					printk("\t0x%08x <---\n", ib->ptr[i]);
- 
 
 4704 
				else
4696 
		case RADEON_PACKET_TYPE0:
 4705 
					printk("\t0x%08x\n", ib->ptr[i]);
4697 
			dev_err(rdev->dev, "Packet0 not allowed!\n");
 4706 
			}
4698 
			ret = -EINVAL;
 4707 
			ret = -EINVAL;
4699 
			break;
 4708 
			break;
4700 
		case RADEON_PACKET_TYPE2:
 4709 
		case RADEON_PACKET_TYPE2:
Line 5012... Line 5021...
5012 
	       protections, vmid, addr,
 5021 
	       protections, vmid, addr,
5013 
	       (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
 5022 
	       (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
5014 
	       block, mc_id);
 5023 
	       block, mc_id);
5015 
}
 5024 
}
Line 5016... Line 5025...
5016 
 
 5025 
 
- 
 
 5026 
void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
5017 
void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
 5027 
		 unsigned vm_id, uint64_t pd_addr)
5018 
{
 - 
 
5019 
	struct radeon_ring *ring = &rdev->ring[ridx];
 - 
 
5020 
 
 - 
 
5021 
	if (vm == NULL)
 - 
 
5022 
		return;
 - 
 
5023 
 
 5028 
{
5024 
	/* write new base address */
 5029 
	/* write new base address */
5025 
	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 5030 
	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5026 
	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
 5031 
	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
Line 5027... Line 5032...
5027 
				 WRITE_DATA_DST_SEL(0)));
 5032 
				 WRITE_DATA_DST_SEL(0)));
5028 
 
 5033 
 
5029 
	if (vm->id < 8) {
 5034 
	if (vm_id < 8) {
5030 
		radeon_ring_write(ring,
 5035 
		radeon_ring_write(ring,
5031 
				  (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
 5036 
				  (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
5032 
	} else {
 5037 
	} else {
5033 
		radeon_ring_write(ring,
 5038 
		radeon_ring_write(ring,
5034 
				  (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
 5039 
				  (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
5035 
	}
 5040 
	}
Line 5036... Line 5041...
5036 
	radeon_ring_write(ring, 0);
 5041 
	radeon_ring_write(ring, 0);
5037 
	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
 5042 
	radeon_ring_write(ring, pd_addr >> 12);
5038 
 
 5043 
 
5039 
	/* flush hdp cache */
 5044 
	/* flush hdp cache */
Line 5048... Line 5053...
5048 
	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 5053 
	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5049 
	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
 5054 
	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5050 
				 WRITE_DATA_DST_SEL(0)));
 5055 
				 WRITE_DATA_DST_SEL(0)));
5051 
	radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
 5056 
	radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5052 
	radeon_ring_write(ring, 0);
 5057 
	radeon_ring_write(ring, 0);
5053 
	radeon_ring_write(ring, 1 << vm->id);
 5058 
	radeon_ring_write(ring, 1 << vm_id);
Line 5054... Line 5059...
5054 
 
 5059 
 
5055 
	/* sync PFP to ME, otherwise we might get invalid PFP reads */
 5060 
	/* sync PFP to ME, otherwise we might get invalid PFP reads */
5056 
	radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
 5061 
	radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5057 
	radeon_ring_write(ring, 0x0);
 5062 
	radeon_ring_write(ring, 0x0);