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| Rev 3031 | Rev 3120 | ||
|---|---|---|---|
| Line 2005... | Line 2005... | ||
| 2005 | /* Initialize the ring buffer's read and write pointers */ |
2005 | /* Initialize the ring buffer's read and write pointers */ |
| 2006 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); |
2006 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); |
| 2007 | ring->wptr = 0; |
2007 | ring->wptr = 0; |
| 2008 | WREG32(CP_RB0_WPTR, ring->wptr); |
2008 | WREG32(CP_RB0_WPTR, ring->wptr); |
| Line 2009... | Line 2009... | ||
| 2009 | 2009 | ||
| 2010 | /* set the wb address wether it's enabled or not */ |
2010 | /* set the wb address whether it's enabled or not */ |
| 2011 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); |
2011 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); |
| Line 2012... | Line 2012... | ||
| 2012 | WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
2012 | WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
| 2013 | 2013 | ||
| Line 2038... | Line 2038... | ||
| 2038 | /* Initialize the ring buffer's read and write pointers */ |
2038 | /* Initialize the ring buffer's read and write pointers */ |
| 2039 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); |
2039 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); |
| 2040 | ring->wptr = 0; |
2040 | ring->wptr = 0; |
| 2041 | WREG32(CP_RB1_WPTR, ring->wptr); |
2041 | WREG32(CP_RB1_WPTR, ring->wptr); |
| Line 2042... | Line 2042... | ||
| 2042 | 2042 | ||
| 2043 | /* set the wb address wether it's enabled or not */ |
2043 | /* set the wb address whether it's enabled or not */ |
| 2044 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); |
2044 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); |
| Line 2045... | Line 2045... | ||
| 2045 | WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); |
2045 | WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); |
| 2046 | 2046 | ||
| Line 2064... | Line 2064... | ||
| 2064 | /* Initialize the ring buffer's read and write pointers */ |
2064 | /* Initialize the ring buffer's read and write pointers */ |
| 2065 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); |
2065 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); |
| 2066 | ring->wptr = 0; |
2066 | ring->wptr = 0; |
| 2067 | WREG32(CP_RB2_WPTR, ring->wptr); |
2067 | WREG32(CP_RB2_WPTR, ring->wptr); |
| Line 2068... | Line 2068... | ||
| 2068 | 2068 | ||
| 2069 | /* set the wb address wether it's enabled or not */ |
2069 | /* set the wb address whether it's enabled or not */ |
| 2070 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); |
2070 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); |
| Line 2071... | Line 2071... | ||
| 2071 | WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); |
2071 | WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); |
| 2072 | 2072 | ||
| Line 3839... | Line 3839... | ||
| 3839 | return r; |
3839 | return r; |
| 3840 | r = si_cp_resume(rdev); |
3840 | r = si_cp_resume(rdev); |
| 3841 | if (r) |
3841 | if (r) |
| 3842 | return r; |
3842 | return r; |
| Line 3843... | Line 3843... | ||
| 3843 | 3843 | ||
| 3844 | // r = radeon_ib_pool_init(rdev); |
3844 | r = radeon_ib_pool_init(rdev); |
| 3845 | // if (r) { |
3845 | if (r) { |
| 3846 | // dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
3846 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 3847 | // return r; |
3847 | return r; |
| Line 3848... | Line 3848... | ||
| 3848 | // } |
3848 | } |
| 3849 | 3849 | ||
| 3850 | // r = radeon_vm_manager_init(rdev); |
3850 | // r = radeon_vm_manager_init(rdev); |
| 3851 | // if (r) { |
3851 | // if (r) { |
| Line 3855... | Line 3855... | ||
| 3855 | 3855 | ||
| 3856 | return 0; |
3856 | return 0; |
| Line -... | Line 3857... | ||
| - | 3857 | } |
|
| - | 3858 | ||
| 3857 | } |
3859 | |
| 3858 | 3860 | ||
| 3859 | 3861 | ||
| 3860 | /* Plan is to move initialization in that function and use |
3862 | /* Plan is to move initialization in that function and use |
| 3861 | * helper function so that radeon_device_init pretty much |
3863 | * helper function so that radeon_device_init pretty much |