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Rev 3192 Rev 3764
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#define R7XX_MAX_SIMDS             16
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#define R7XX_MAX_SIMDS             16
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#define R7XX_MAX_SIMDS_MASK        0xffff
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#define R7XX_MAX_SIMDS_MASK        0xffff
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#define R7XX_MAX_PIPES             8
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#define R7XX_MAX_PIPES             8
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#define R7XX_MAX_PIPES_MASK        0xff
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#define R7XX_MAX_PIPES_MASK        0xff
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/* discrete uvd clocks */
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#define CG_UPLL_FUNC_CNTL				0x718
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#	define UPLL_RESET_MASK				0x00000001
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#	define UPLL_SLEEP_MASK				0x00000002
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#	define UPLL_BYPASS_EN_MASK			0x00000004
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#	define UPLL_CTLREQ_MASK				0x00000008
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#	define UPLL_REF_DIV(x)				((x) << 16)
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#	define UPLL_REF_DIV_MASK			0x003F0000
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#	define UPLL_CTLACK_MASK				0x40000000
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#	define UPLL_CTLACK2_MASK			0x80000000
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#define CG_UPLL_FUNC_CNTL_2				0x71c
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#	define UPLL_SW_HILEN(x)				((x) << 0)
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#	define UPLL_SW_LOLEN(x)				((x) << 4)
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#	define UPLL_SW_HILEN2(x)			((x) << 8)
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#	define UPLL_SW_LOLEN2(x)			((x) << 12)
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#	define UPLL_SW_MASK				0x0000FFFF
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#	define VCLK_SRC_SEL(x)				((x) << 20)
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#	define VCLK_SRC_SEL_MASK			0x01F00000
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#	define DCLK_SRC_SEL(x)				((x) << 25)
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#	define DCLK_SRC_SEL_MASK			0x3E000000
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#define CG_UPLL_FUNC_CNTL_3				0x720
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#	define UPLL_FB_DIV(x)				((x) << 0)
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#	define UPLL_FB_DIV_MASK				0x01FFFFFF
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/* Registers */
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/* Registers */
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#define	CB_COLOR0_BASE					0x28040
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#define	CB_COLOR0_BASE					0x28040
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#define	CB_COLOR1_BASE					0x28044
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#define	CB_COLOR1_BASE					0x28044
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#define	CB_COLOR2_BASE					0x28048
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#define	CB_COLOR2_BASE					0x28048
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#define     PIPE_TILING__MASK               0x0000000e
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#define     PIPE_TILING__MASK               0x0000000e
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#define DMA_TILING_CONFIG                               0x3ec8
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#define DMA_TILING_CONFIG                               0x3ec8
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#define DMA_TILING_CONFIG2                              0xd0b8
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/* RV730 only */
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#define UVD_UDEC_TILING_CONFIG                          0xef40
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#define UVD_UDEC_DB_TILING_CONFIG                       0xef44
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#define DMA_TILING_CONFIG2                              0xd0b8
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#define UVD_UDEC_DBW_TILING_CONFIG                      0xef48
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#define	GC_USER_SHADER_PIPE_CONFIG			0x8954
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#define	GC_USER_SHADER_PIPE_CONFIG			0x8954
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#define		INACTIVE_QD_PIPES(x)				((x) << 8)
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#define		INACTIVE_QD_PIPES(x)				((x) << 8)
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#define		INACTIVE_QD_PIPES_MASK				0x0000FF00
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#define		INACTIVE_QD_PIPES_MASK				0x0000FF00
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#define	GRBM_STATUS					0x8010
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#define	GRBM_STATUS					0x8010
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#define		CMDFIFO_AVAIL_MASK				0x0000000F
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#define		CMDFIFO_AVAIL_MASK				0x0000000F
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#define		GUI_ACTIVE					(1<<31)
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#define		GUI_ACTIVE					(1<<31)
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#define	GRBM_STATUS2					0x8014
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#define	GRBM_STATUS2					0x8014
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#define CG_CLKPIN_CNTL                                    0x660
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#       define MUX_TCLK_TO_XCLK                           (1 << 8)
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#       define XTALIN_DIVIDE                              (1 << 9)
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#define	CG_MULT_THERMAL_STATUS				0x740
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#define	CG_MULT_THERMAL_STATUS				0x740
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#define		ASIC_T(x)			        ((x) << 16)
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#define		ASIC_T(x)			        ((x) << 16)
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#define		ASIC_T_MASK			        0x3FF0000
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#define		ASIC_T_MASK			        0x3FF0000
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#       define MM_WR_TO_CFG_EN                            (1 << 3)
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#       define MM_WR_TO_CFG_EN                            (1 << 3)
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#define LINK_CNTL2                                        0x88 /* F0 */
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#define LINK_CNTL2                                        0x88 /* F0 */
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#       define TARGET_LINK_SPEED_MASK                     (0xf << 0)
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#       define TARGET_LINK_SPEED_MASK                     (0xf << 0)
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#       define SELECTABLE_DEEMPHASIS                      (1 << 6)
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#       define SELECTABLE_DEEMPHASIS                      (1 << 6)
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/* UVD */
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#define UVD_LMI_EXT40_ADDR				0xf498
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#define UVD_VCPU_CHIP_ID				0xf4d4
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#define UVD_VCPU_CACHE_OFFSET0				0xf4d8
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#define UVD_VCPU_CACHE_SIZE0				0xf4dc
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#define UVD_VCPU_CACHE_OFFSET1				0xf4e0
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#define UVD_VCPU_CACHE_SIZE1				0xf4e4
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#define UVD_VCPU_CACHE_OFFSET2				0xf4e8
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#define UVD_VCPU_CACHE_SIZE2				0xf4ec
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#define UVD_LMI_ADDR_EXT				0xf594
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#define UVD_RBC_RB_RPTR					0xf690
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#define UVD_RBC_RB_WPTR					0xf694
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