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Rev 3192 Rev 3764
Line 40... Line 40...
40 
#define R700_PM4_UCODE_SIZE 1360
 40 
#define R700_PM4_UCODE_SIZE 1360
Line 41... Line 41...
41 
 
 41 
 
42 
static void rv770_gpu_init(struct radeon_device *rdev);
 42 
static void rv770_gpu_init(struct radeon_device *rdev);
43 
void rv770_fini(struct radeon_device *rdev);
 43 
void rv770_fini(struct radeon_device *rdev);
- 
 
 44 
static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
Line -... Line 45...
- 
 
 45 
int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
- 
 
 46 
 
- 
 
 47 
int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
- 
 
 48 
{
- 
 
 49 
	unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
- 
 
 50 
	int r;
- 
 
 51 
 
- 
 
 52 
	/* RV740 uses evergreen uvd clk programming */
- 
 
 53 
	if (rdev->family == CHIP_RV740)
- 
 
 54 
		return evergreen_set_uvd_clocks(rdev, vclk, dclk);
- 
 
 55 
 
- 
 
 56 
	/* bypass vclk and dclk with bclk */
- 
 
 57 
	WREG32_P(CG_UPLL_FUNC_CNTL_2,
- 
 
 58 
		 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
- 
 
 59 
		 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
- 
 
 60 
 
- 
 
 61 
	if (!vclk || !dclk) {
- 
 
 62 
		/* keep the Bypass mode, put PLL to sleep */
- 
 
 63 
		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
- 
 
 64 
		return 0;
- 
 
 65 
	}
- 
 
 66 
 
- 
 
 67 
//   r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
- 
 
 68 
//                     43663, 0x03FFFFFE, 1, 30, ~0,
- 
 
 69 
//                     &fb_div, &vclk_div, &dclk_div);
- 
 
 70 
//   if (r)
- 
 
 71 
		return r;
- 
 
 72 
 
- 
 
 73 
	fb_div |= 1;
- 
 
 74 
	vclk_div -= 1;
- 
 
 75 
	dclk_div -= 1;
- 
 
 76 
 
- 
 
 77 
	/* set UPLL_FB_DIV to 0x50000 */
- 
 
 78 
	WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
- 
 
 79 
 
- 
 
 80 
	/* deassert UPLL_RESET and UPLL_SLEEP */
- 
 
 81 
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
- 
 
 82 
 
- 
 
 83 
	/* assert BYPASS EN and FB_DIV[0] <- ??? why? */
- 
 
 84 
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
- 
 
 85 
	WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
- 
 
 86 
 
- 
 
 87 
//   r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
- 
 
 88 
//   if (r)
- 
 
 89 
		return r;
- 
 
 90 
 
- 
 
 91 
	/* assert PLL_RESET */
- 
 
 92 
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
- 
 
 93 
 
- 
 
 94 
	/* set the required FB_DIV, REF_DIV, Post divder values */
- 
 
 95 
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
- 
 
 96 
	WREG32_P(CG_UPLL_FUNC_CNTL_2,
- 
 
 97 
		 UPLL_SW_HILEN(vclk_div >> 1) |
- 
 
 98 
		 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
- 
 
 99 
		 UPLL_SW_HILEN2(dclk_div >> 1) |
- 
 
 100 
		 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
- 
 
 101 
		 ~UPLL_SW_MASK);
- 
 
 102 
 
- 
 
 103 
	WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
- 
 
 104 
		 ~UPLL_FB_DIV_MASK);
- 
 
 105 
 
- 
 
 106 
	/* give the PLL some time to settle */
- 
 
 107 
	mdelay(15);
- 
 
 108 
 
- 
 
 109 
	/* deassert PLL_RESET */
- 
 
 110 
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
- 
 
 111 
 
- 
 
 112 
	mdelay(15);
- 
 
 113 
 
- 
 
 114 
	/* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
- 
 
 115 
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
- 
 
 116 
	WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
- 
 
 117 
 
- 
 
 118 
//   r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
- 
 
 119 
//   if (r)
- 
 
 120 
		return r;
- 
 
 121 
 
- 
 
 122 
	/* switch VCLK and DCLK selection */
- 
 
 123 
	WREG32_P(CG_UPLL_FUNC_CNTL_2,
- 
 
 124 
		 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
- 
 
 125 
		 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
- 
 
 126 
 
- 
 
 127 
	mdelay(100);
- 
 
 128 
 
- 
 
 129 
	return 0;
- 
 
 130 
}
- 
 
 131 
 
- 
 
 132 
static const u32 r7xx_golden_registers[] =
- 
 
 133 
{
- 
 
 134 
	0x8d00, 0xffffffff, 0x0e0e0074,
- 
 
 135 
	0x8d04, 0xffffffff, 0x013a2b34,
- 
 
 136 
	0x9508, 0xffffffff, 0x00000002,
- 
 
 137 
	0x8b20, 0xffffffff, 0,
- 
 
 138 
	0x88c4, 0xffffffff, 0x000000c2,
- 
 
 139 
	0x28350, 0xffffffff, 0,
- 
 
 140 
	0x9058, 0xffffffff, 0x0fffc40f,
- 
 
 141 
	0x240c, 0xffffffff, 0x00000380,
- 
 
 142 
	0x733c, 0xffffffff, 0x00000002,
- 
 
 143 
	0x2650, 0x00040000, 0,
- 
 
 144 
	0x20bc, 0x00040000, 0,
- 
 
 145 
	0x7300, 0xffffffff, 0x001000f0
- 
 
 146 
};
- 
 
 147 
 
- 
 
 148 
static const u32 r7xx_golden_dyn_gpr_registers[] =
- 
 
 149 
{
- 
 
 150 
	0x8db0, 0xffffffff, 0x98989898,
- 
 
 151 
	0x8db4, 0xffffffff, 0x98989898,
- 
 
 152 
	0x8db8, 0xffffffff, 0x98989898,
- 
 
 153 
	0x8dbc, 0xffffffff, 0x98989898,
- 
 
 154 
	0x8dc0, 0xffffffff, 0x98989898,
- 
 
 155 
	0x8dc4, 0xffffffff, 0x98989898,
- 
 
 156 
	0x8dc8, 0xffffffff, 0x98989898,
- 
 
 157 
	0x8dcc, 0xffffffff, 0x98989898,
- 
 
 158 
	0x88c4, 0xffffffff, 0x00000082
- 
 
 159 
};
- 
 
 160 
 
- 
 
 161 
static const u32 rv770_golden_registers[] =
- 
 
 162 
{
- 
 
 163 
	0x562c, 0xffffffff, 0,
- 
 
 164 
	0x3f90, 0xffffffff, 0,
- 
 
 165 
	0x9148, 0xffffffff, 0,
- 
 
 166 
	0x3f94, 0xffffffff, 0,
- 
 
 167 
	0x914c, 0xffffffff, 0,
- 
 
 168 
	0x9698, 0x18000000, 0x18000000
- 
 
 169 
};
- 
 
 170 
 
- 
 
 171 
static const u32 rv770ce_golden_registers[] =
- 
 
 172 
{
- 
 
 173 
	0x562c, 0xffffffff, 0,
- 
 
 174 
	0x3f90, 0xffffffff, 0x00cc0000,
- 
 
 175 
	0x9148, 0xffffffff, 0x00cc0000,
- 
 
 176 
	0x3f94, 0xffffffff, 0x00cc0000,
- 
 
 177 
	0x914c, 0xffffffff, 0x00cc0000,
- 
 
 178 
	0x9b7c, 0xffffffff, 0x00fa0000,
- 
 
 179 
	0x3f8c, 0xffffffff, 0x00fa0000,
- 
 
 180 
	0x9698, 0x18000000, 0x18000000
- 
 
 181 
};
- 
 
 182 
 
- 
 
 183 
static const u32 rv770_mgcg_init[] =
- 
 
 184 
{
- 
 
 185 
	0x8bcc, 0xffffffff, 0x130300f9,
- 
 
 186 
	0x5448, 0xffffffff, 0x100,
- 
 
 187 
	0x55e4, 0xffffffff, 0x100,
- 
 
 188 
	0x160c, 0xffffffff, 0x100,
- 
 
 189 
	0x5644, 0xffffffff, 0x100,
- 
 
 190 
	0xc164, 0xffffffff, 0x100,
- 
 
 191 
	0x8a18, 0xffffffff, 0x100,
- 
 
 192 
	0x897c, 0xffffffff, 0x8000100,
- 
 
 193 
	0x8b28, 0xffffffff, 0x3c000100,
- 
 
 194 
	0x9144, 0xffffffff, 0x100,
- 
 
 195 
	0x9a1c, 0xffffffff, 0x10000,
- 
 
 196 
	0x9a50, 0xffffffff, 0x100,
- 
 
 197 
	0x9a1c, 0xffffffff, 0x10001,
- 
 
 198 
	0x9a50, 0xffffffff, 0x100,
- 
 
 199 
	0x9a1c, 0xffffffff, 0x10002,
- 
 
 200 
	0x9a50, 0xffffffff, 0x100,
- 
 
 201 
	0x9a1c, 0xffffffff, 0x10003,
- 
 
 202 
	0x9a50, 0xffffffff, 0x100,
- 
 
 203 
	0x9a1c, 0xffffffff, 0x0,
- 
 
 204 
	0x9870, 0xffffffff, 0x100,
- 
 
 205 
	0x8d58, 0xffffffff, 0x100,
- 
 
 206 
	0x9500, 0xffffffff, 0x0,
- 
 
 207 
	0x9510, 0xffffffff, 0x100,
- 
 
 208 
	0x9500, 0xffffffff, 0x1,
- 
 
 209 
	0x9510, 0xffffffff, 0x100,
- 
 
 210 
	0x9500, 0xffffffff, 0x2,
- 
 
 211 
	0x9510, 0xffffffff, 0x100,
- 
 
 212 
	0x9500, 0xffffffff, 0x3,
- 
 
 213 
	0x9510, 0xffffffff, 0x100,
- 
 
 214 
	0x9500, 0xffffffff, 0x4,
- 
 
 215 
	0x9510, 0xffffffff, 0x100,
- 
 
 216 
	0x9500, 0xffffffff, 0x5,
- 
 
 217 
	0x9510, 0xffffffff, 0x100,
- 
 
 218 
	0x9500, 0xffffffff, 0x6,
- 
 
 219 
	0x9510, 0xffffffff, 0x100,
- 
 
 220 
	0x9500, 0xffffffff, 0x7,
- 
 
 221 
	0x9510, 0xffffffff, 0x100,
- 
 
 222 
	0x9500, 0xffffffff, 0x8,
- 
 
 223 
	0x9510, 0xffffffff, 0x100,
- 
 
 224 
	0x9500, 0xffffffff, 0x9,
- 
 
 225 
	0x9510, 0xffffffff, 0x100,
- 
 
 226 
	0x9500, 0xffffffff, 0x8000,
- 
 
 227 
	0x9490, 0xffffffff, 0x0,
- 
 
 228 
	0x949c, 0xffffffff, 0x100,
- 
 
 229 
	0x9490, 0xffffffff, 0x1,
- 
 
 230 
	0x949c, 0xffffffff, 0x100,
- 
 
 231 
	0x9490, 0xffffffff, 0x2,
- 
 
 232 
	0x949c, 0xffffffff, 0x100,
- 
 
 233 
	0x9490, 0xffffffff, 0x3,
- 
 
 234 
	0x949c, 0xffffffff, 0x100,
- 
 
 235 
	0x9490, 0xffffffff, 0x4,
- 
 
 236 
	0x949c, 0xffffffff, 0x100,
- 
 
 237 
	0x9490, 0xffffffff, 0x5,
- 
 
 238 
	0x949c, 0xffffffff, 0x100,
- 
 
 239 
	0x9490, 0xffffffff, 0x6,
- 
 
 240 
	0x949c, 0xffffffff, 0x100,
- 
 
 241 
	0x9490, 0xffffffff, 0x7,
- 
 
 242 
	0x949c, 0xffffffff, 0x100,
- 
 
 243 
	0x9490, 0xffffffff, 0x8,
- 
 
 244 
	0x949c, 0xffffffff, 0x100,
- 
 
 245 
	0x9490, 0xffffffff, 0x9,
- 
 
 246 
	0x949c, 0xffffffff, 0x100,
- 
 
 247 
	0x9490, 0xffffffff, 0x8000,
- 
 
 248 
	0x9604, 0xffffffff, 0x0,
- 
 
 249 
	0x9654, 0xffffffff, 0x100,
- 
 
 250 
	0x9604, 0xffffffff, 0x1,
- 
 
 251 
	0x9654, 0xffffffff, 0x100,
- 
 
 252 
	0x9604, 0xffffffff, 0x2,
- 
 
 253 
	0x9654, 0xffffffff, 0x100,
- 
 
 254 
	0x9604, 0xffffffff, 0x3,
- 
 
 255 
	0x9654, 0xffffffff, 0x100,
- 
 
 256 
	0x9604, 0xffffffff, 0x4,
- 
 
 257 
	0x9654, 0xffffffff, 0x100,
- 
 
 258 
	0x9604, 0xffffffff, 0x5,
- 
 
 259 
	0x9654, 0xffffffff, 0x100,
- 
 
 260 
	0x9604, 0xffffffff, 0x6,
- 
 
 261 
	0x9654, 0xffffffff, 0x100,
- 
 
 262 
	0x9604, 0xffffffff, 0x7,
- 
 
 263 
	0x9654, 0xffffffff, 0x100,
- 
 
 264 
	0x9604, 0xffffffff, 0x8,
- 
 
 265 
	0x9654, 0xffffffff, 0x100,
- 
 
 266 
	0x9604, 0xffffffff, 0x9,
- 
 
 267 
	0x9654, 0xffffffff, 0x100,
- 
 
 268 
	0x9604, 0xffffffff, 0x80000000,
- 
 
 269 
	0x9030, 0xffffffff, 0x100,
- 
 
 270 
	0x9034, 0xffffffff, 0x100,
- 
 
 271 
	0x9038, 0xffffffff, 0x100,
- 
 
 272 
	0x903c, 0xffffffff, 0x100,
- 
 
 273 
	0x9040, 0xffffffff, 0x100,
- 
 
 274 
	0xa200, 0xffffffff, 0x100,
- 
 
 275 
	0xa204, 0xffffffff, 0x100,
- 
 
 276 
	0xa208, 0xffffffff, 0x100,
- 
 
 277 
	0xa20c, 0xffffffff, 0x100,
- 
 
 278 
	0x971c, 0xffffffff, 0x100,
- 
 
 279 
	0x915c, 0xffffffff, 0x00020001,
- 
 
 280 
	0x9160, 0xffffffff, 0x00040003,
- 
 
 281 
	0x916c, 0xffffffff, 0x00060005,
- 
 
 282 
	0x9170, 0xffffffff, 0x00080007,
- 
 
 283 
	0x9174, 0xffffffff, 0x000a0009,
- 
 
 284 
	0x9178, 0xffffffff, 0x000c000b,
- 
 
 285 
	0x917c, 0xffffffff, 0x000e000d,
- 
 
 286 
	0x9180, 0xffffffff, 0x0010000f,
- 
 
 287 
	0x918c, 0xffffffff, 0x00120011,
- 
 
 288 
	0x9190, 0xffffffff, 0x00140013,
- 
 
 289 
	0x9194, 0xffffffff, 0x00020001,
- 
 
 290 
	0x9198, 0xffffffff, 0x00040003,
- 
 
 291 
	0x919c, 0xffffffff, 0x00060005,
- 
 
 292 
	0x91a8, 0xffffffff, 0x00080007,
- 
 
 293 
	0x91ac, 0xffffffff, 0x000a0009,
- 
 
 294 
	0x91b0, 0xffffffff, 0x000c000b,
- 
 
 295 
	0x91b4, 0xffffffff, 0x000e000d,
- 
 
 296 
	0x91b8, 0xffffffff, 0x0010000f,
- 
 
 297 
	0x91c4, 0xffffffff, 0x00120011,
- 
 
 298 
	0x91c8, 0xffffffff, 0x00140013,
- 
 
 299 
	0x91cc, 0xffffffff, 0x00020001,
- 
 
 300 
	0x91d0, 0xffffffff, 0x00040003,
- 
 
 301 
	0x91d4, 0xffffffff, 0x00060005,
- 
 
 302 
	0x91e0, 0xffffffff, 0x00080007,
- 
 
 303 
	0x91e4, 0xffffffff, 0x000a0009,
- 
 
 304 
	0x91e8, 0xffffffff, 0x000c000b,
- 
 
 305 
	0x91ec, 0xffffffff, 0x00020001,
- 
 
 306 
	0x91f0, 0xffffffff, 0x00040003,
- 
 
 307 
	0x91f4, 0xffffffff, 0x00060005,
- 
 
 308 
	0x9200, 0xffffffff, 0x00080007,
- 
 
 309 
	0x9204, 0xffffffff, 0x000a0009,
- 
 
 310 
	0x9208, 0xffffffff, 0x000c000b,
- 
 
 311 
	0x920c, 0xffffffff, 0x000e000d,
- 
 
 312 
	0x9210, 0xffffffff, 0x0010000f,
- 
 
 313 
	0x921c, 0xffffffff, 0x00120011,
- 
 
 314 
	0x9220, 0xffffffff, 0x00140013,
- 
 
 315 
	0x9224, 0xffffffff, 0x00020001,
- 
 
 316 
	0x9228, 0xffffffff, 0x00040003,
- 
 
 317 
	0x922c, 0xffffffff, 0x00060005,
- 
 
 318 
	0x9238, 0xffffffff, 0x00080007,
- 
 
 319 
	0x923c, 0xffffffff, 0x000a0009,
- 
 
 320 
	0x9240, 0xffffffff, 0x000c000b,
- 
 
 321 
	0x9244, 0xffffffff, 0x000e000d,
- 
 
 322 
	0x9248, 0xffffffff, 0x0010000f,
- 
 
 323 
	0x9254, 0xffffffff, 0x00120011,
- 
 
 324 
	0x9258, 0xffffffff, 0x00140013,
- 
 
 325 
	0x925c, 0xffffffff, 0x00020001,
- 
 
 326 
	0x9260, 0xffffffff, 0x00040003,
- 
 
 327 
	0x9264, 0xffffffff, 0x00060005,
- 
 
 328 
	0x9270, 0xffffffff, 0x00080007,
- 
 
 329 
	0x9274, 0xffffffff, 0x000a0009,
- 
 
 330 
	0x9278, 0xffffffff, 0x000c000b,
- 
 
 331 
	0x927c, 0xffffffff, 0x000e000d,
- 
 
 332 
	0x9280, 0xffffffff, 0x0010000f,
- 
 
 333 
	0x928c, 0xffffffff, 0x00120011,
- 
 
 334 
	0x9290, 0xffffffff, 0x00140013,
- 
 
 335 
	0x9294, 0xffffffff, 0x00020001,
- 
 
 336 
	0x929c, 0xffffffff, 0x00040003,
- 
 
 337 
	0x92a0, 0xffffffff, 0x00060005,
- 
 
 338 
	0x92a4, 0xffffffff, 0x00080007
- 
 
 339 
};
- 
 
 340 
 
- 
 
 341 
static const u32 rv710_golden_registers[] =
- 
 
 342 
{
- 
 
 343 
	0x3f90, 0x00ff0000, 0x00fc0000,
- 
 
 344 
	0x9148, 0x00ff0000, 0x00fc0000,
- 
 
 345 
	0x3f94, 0x00ff0000, 0x00fc0000,
- 
 
 346 
	0x914c, 0x00ff0000, 0x00fc0000,
- 
 
 347 
	0xb4c, 0x00000020, 0x00000020,
- 
 
 348 
	0xa180, 0xffffffff, 0x00003f3f
- 
 
 349 
};
- 
 
 350 
 
- 
 
 351 
static const u32 rv710_mgcg_init[] =
- 
 
 352 
{
- 
 
 353 
	0x8bcc, 0xffffffff, 0x13030040,
- 
 
 354 
	0x5448, 0xffffffff, 0x100,
- 
 
 355 
	0x55e4, 0xffffffff, 0x100,
- 
 
 356 
	0x160c, 0xffffffff, 0x100,
- 
 
 357 
	0x5644, 0xffffffff, 0x100,
- 
 
 358 
	0xc164, 0xffffffff, 0x100,
- 
 
 359 
	0x8a18, 0xffffffff, 0x100,
- 
 
 360 
	0x897c, 0xffffffff, 0x8000100,
- 
 
 361 
	0x8b28, 0xffffffff, 0x3c000100,
- 
 
 362 
	0x9144, 0xffffffff, 0x100,
- 
 
 363 
	0x9a1c, 0xffffffff, 0x10000,
- 
 
 364 
	0x9a50, 0xffffffff, 0x100,
- 
 
 365 
	0x9a1c, 0xffffffff, 0x0,
- 
 
 366 
	0x9870, 0xffffffff, 0x100,
- 
 
 367 
	0x8d58, 0xffffffff, 0x100,
- 
 
 368 
	0x9500, 0xffffffff, 0x0,
- 
 
 369 
	0x9510, 0xffffffff, 0x100,
- 
 
 370 
	0x9500, 0xffffffff, 0x1,
- 
 
 371 
	0x9510, 0xffffffff, 0x100,
- 
 
 372 
	0x9500, 0xffffffff, 0x8000,
- 
 
 373 
	0x9490, 0xffffffff, 0x0,
- 
 
 374 
	0x949c, 0xffffffff, 0x100,
- 
 
 375 
	0x9490, 0xffffffff, 0x1,
- 
 
 376 
	0x949c, 0xffffffff, 0x100,
- 
 
 377 
	0x9490, 0xffffffff, 0x8000,
- 
 
 378 
	0x9604, 0xffffffff, 0x0,
- 
 
 379 
	0x9654, 0xffffffff, 0x100,
- 
 
 380 
	0x9604, 0xffffffff, 0x1,
- 
 
 381 
	0x9654, 0xffffffff, 0x100,
- 
 
 382 
	0x9604, 0xffffffff, 0x80000000,
- 
 
 383 
	0x9030, 0xffffffff, 0x100,
- 
 
 384 
	0x9034, 0xffffffff, 0x100,
- 
 
 385 
	0x9038, 0xffffffff, 0x100,
- 
 
 386 
	0x903c, 0xffffffff, 0x100,
- 
 
 387 
	0x9040, 0xffffffff, 0x100,
- 
 
 388 
	0xa200, 0xffffffff, 0x100,
- 
 
 389 
	0xa204, 0xffffffff, 0x100,
- 
 
 390 
	0xa208, 0xffffffff, 0x100,
- 
 
 391 
	0xa20c, 0xffffffff, 0x100,
- 
 
 392 
	0x971c, 0xffffffff, 0x100,
- 
 
 393 
	0x915c, 0xffffffff, 0x00020001,
- 
 
 394 
	0x9174, 0xffffffff, 0x00000003,
- 
 
 395 
	0x9178, 0xffffffff, 0x00050001,
- 
 
 396 
	0x917c, 0xffffffff, 0x00030002,
- 
 
 397 
	0x918c, 0xffffffff, 0x00000004,
- 
 
 398 
	0x9190, 0xffffffff, 0x00070006,
- 
 
 399 
	0x9194, 0xffffffff, 0x00050001,
- 
 
 400 
	0x9198, 0xffffffff, 0x00030002,
- 
 
 401 
	0x91a8, 0xffffffff, 0x00000004,
- 
 
 402 
	0x91ac, 0xffffffff, 0x00070006,
- 
 
 403 
	0x91e8, 0xffffffff, 0x00000001,
- 
 
 404 
	0x9294, 0xffffffff, 0x00000001,
- 
 
 405 
	0x929c, 0xffffffff, 0x00000002,
- 
 
 406 
	0x92a0, 0xffffffff, 0x00040003,
- 
 
 407 
	0x9150, 0xffffffff, 0x4d940000
- 
 
 408 
};
- 
 
 409 
 
- 
 
 410 
static const u32 rv730_golden_registers[] =
- 
 
 411 
{
- 
 
 412 
	0x3f90, 0x00ff0000, 0x00f00000,
- 
 
 413 
	0x9148, 0x00ff0000, 0x00f00000,
- 
 
 414 
	0x3f94, 0x00ff0000, 0x00f00000,
- 
 
 415 
	0x914c, 0x00ff0000, 0x00f00000,
- 
 
 416 
	0x900c, 0xffffffff, 0x003b033f,
- 
 
 417 
	0xb4c, 0x00000020, 0x00000020,
- 
 
 418 
	0xa180, 0xffffffff, 0x00003f3f
- 
 
 419 
};
- 
 
 420 
 
- 
 
 421 
static const u32 rv730_mgcg_init[] =
- 
 
 422 
{
- 
 
 423 
	0x8bcc, 0xffffffff, 0x130300f9,
- 
 
 424 
	0x5448, 0xffffffff, 0x100,
- 
 
 425 
	0x55e4, 0xffffffff, 0x100,
- 
 
 426 
	0x160c, 0xffffffff, 0x100,
- 
 
 427 
	0x5644, 0xffffffff, 0x100,
- 
 
 428 
	0xc164, 0xffffffff, 0x100,
- 
 
 429 
	0x8a18, 0xffffffff, 0x100,
- 
 
 430 
	0x897c, 0xffffffff, 0x8000100,
- 
 
 431 
	0x8b28, 0xffffffff, 0x3c000100,
- 
 
 432 
	0x9144, 0xffffffff, 0x100,
- 
 
 433 
	0x9a1c, 0xffffffff, 0x10000,
- 
 
 434 
	0x9a50, 0xffffffff, 0x100,
- 
 
 435 
	0x9a1c, 0xffffffff, 0x10001,
- 
 
 436 
	0x9a50, 0xffffffff, 0x100,
- 
 
 437 
	0x9a1c, 0xffffffff, 0x0,
- 
 
 438 
	0x9870, 0xffffffff, 0x100,
- 
 
 439 
	0x8d58, 0xffffffff, 0x100,
- 
 
 440 
	0x9500, 0xffffffff, 0x0,
- 
 
 441 
	0x9510, 0xffffffff, 0x100,
- 
 
 442 
	0x9500, 0xffffffff, 0x1,
- 
 
 443 
	0x9510, 0xffffffff, 0x100,
- 
 
 444 
	0x9500, 0xffffffff, 0x2,
- 
 
 445 
	0x9510, 0xffffffff, 0x100,
- 
 
 446 
	0x9500, 0xffffffff, 0x3,
- 
 
 447 
	0x9510, 0xffffffff, 0x100,
- 
 
 448 
	0x9500, 0xffffffff, 0x4,
- 
 
 449 
	0x9510, 0xffffffff, 0x100,
- 
 
 450 
	0x9500, 0xffffffff, 0x5,
- 
 
 451 
	0x9510, 0xffffffff, 0x100,
- 
 
 452 
	0x9500, 0xffffffff, 0x6,
- 
 
 453 
	0x9510, 0xffffffff, 0x100,
- 
 
 454 
	0x9500, 0xffffffff, 0x7,
- 
 
 455 
	0x9510, 0xffffffff, 0x100,
- 
 
 456 
	0x9500, 0xffffffff, 0x8000,
- 
 
 457 
	0x9490, 0xffffffff, 0x0,
- 
 
 458 
	0x949c, 0xffffffff, 0x100,
- 
 
 459 
	0x9490, 0xffffffff, 0x1,
- 
 
 460 
	0x949c, 0xffffffff, 0x100,
- 
 
 461 
	0x9490, 0xffffffff, 0x2,
- 
 
 462 
	0x949c, 0xffffffff, 0x100,
- 
 
 463 
	0x9490, 0xffffffff, 0x3,
- 
 
 464 
	0x949c, 0xffffffff, 0x100,
- 
 
 465 
	0x9490, 0xffffffff, 0x4,
- 
 
 466 
	0x949c, 0xffffffff, 0x100,
- 
 
 467 
	0x9490, 0xffffffff, 0x5,
- 
 
 468 
	0x949c, 0xffffffff, 0x100,
- 
 
 469 
	0x9490, 0xffffffff, 0x6,
- 
 
 470 
	0x949c, 0xffffffff, 0x100,
- 
 
 471 
	0x9490, 0xffffffff, 0x7,
- 
 
 472 
	0x949c, 0xffffffff, 0x100,
- 
 
 473 
	0x9490, 0xffffffff, 0x8000,
- 
 
 474 
	0x9604, 0xffffffff, 0x0,
- 
 
 475 
	0x9654, 0xffffffff, 0x100,
- 
 
 476 
	0x9604, 0xffffffff, 0x1,
- 
 
 477 
	0x9654, 0xffffffff, 0x100,
- 
 
 478 
	0x9604, 0xffffffff, 0x2,
- 
 
 479 
	0x9654, 0xffffffff, 0x100,
- 
 
 480 
	0x9604, 0xffffffff, 0x3,
- 
 
 481 
	0x9654, 0xffffffff, 0x100,
- 
 
 482 
	0x9604, 0xffffffff, 0x4,
- 
 
 483 
	0x9654, 0xffffffff, 0x100,
- 
 
 484 
	0x9604, 0xffffffff, 0x5,
- 
 
 485 
	0x9654, 0xffffffff, 0x100,
- 
 
 486 
	0x9604, 0xffffffff, 0x6,
- 
 
 487 
	0x9654, 0xffffffff, 0x100,
- 
 
 488 
	0x9604, 0xffffffff, 0x7,
- 
 
 489 
	0x9654, 0xffffffff, 0x100,
- 
 
 490 
	0x9604, 0xffffffff, 0x80000000,
- 
 
 491 
	0x9030, 0xffffffff, 0x100,
- 
 
 492 
	0x9034, 0xffffffff, 0x100,
- 
 
 493 
	0x9038, 0xffffffff, 0x100,
- 
 
 494 
	0x903c, 0xffffffff, 0x100,
- 
 
 495 
	0x9040, 0xffffffff, 0x100,
- 
 
 496 
	0xa200, 0xffffffff, 0x100,
- 
 
 497 
	0xa204, 0xffffffff, 0x100,
- 
 
 498 
	0xa208, 0xffffffff, 0x100,
- 
 
 499 
	0xa20c, 0xffffffff, 0x100,
- 
 
 500 
	0x971c, 0xffffffff, 0x100,
- 
 
 501 
	0x915c, 0xffffffff, 0x00020001,
- 
 
 502 
	0x916c, 0xffffffff, 0x00040003,
- 
 
 503 
	0x9170, 0xffffffff, 0x00000005,
- 
 
 504 
	0x9178, 0xffffffff, 0x00050001,
- 
 
 505 
	0x917c, 0xffffffff, 0x00030002,
- 
 
 506 
	0x918c, 0xffffffff, 0x00000004,
- 
 
 507 
	0x9190, 0xffffffff, 0x00070006,
- 
 
 508 
	0x9194, 0xffffffff, 0x00050001,
- 
 
 509 
	0x9198, 0xffffffff, 0x00030002,
- 
 
 510 
	0x91a8, 0xffffffff, 0x00000004,
- 
 
 511 
	0x91ac, 0xffffffff, 0x00070006,
- 
 
 512 
	0x91b0, 0xffffffff, 0x00050001,
- 
 
 513 
	0x91b4, 0xffffffff, 0x00030002,
- 
 
 514 
	0x91c4, 0xffffffff, 0x00000004,
- 
 
 515 
	0x91c8, 0xffffffff, 0x00070006,
- 
 
 516 
	0x91cc, 0xffffffff, 0x00050001,
- 
 
 517 
	0x91d0, 0xffffffff, 0x00030002,
- 
 
 518 
	0x91e0, 0xffffffff, 0x00000004,
- 
 
 519 
	0x91e4, 0xffffffff, 0x00070006,
- 
 
 520 
	0x91e8, 0xffffffff, 0x00000001,
- 
 
 521 
	0x91ec, 0xffffffff, 0x00050001,
- 
 
 522 
	0x91f0, 0xffffffff, 0x00030002,
- 
 
 523 
	0x9200, 0xffffffff, 0x00000004,
- 
 
 524 
	0x9204, 0xffffffff, 0x00070006,
- 
 
 525 
	0x9208, 0xffffffff, 0x00050001,
- 
 
 526 
	0x920c, 0xffffffff, 0x00030002,
- 
 
 527 
	0x921c, 0xffffffff, 0x00000004,
- 
 
 528 
	0x9220, 0xffffffff, 0x00070006,
- 
 
 529 
	0x9224, 0xffffffff, 0x00050001,
- 
 
 530 
	0x9228, 0xffffffff, 0x00030002,
- 
 
 531 
	0x9238, 0xffffffff, 0x00000004,
- 
 
 532 
	0x923c, 0xffffffff, 0x00070006,
- 
 
 533 
	0x9240, 0xffffffff, 0x00050001,
- 
 
 534 
	0x9244, 0xffffffff, 0x00030002,
- 
 
 535 
	0x9254, 0xffffffff, 0x00000004,
- 
 
 536 
	0x9258, 0xffffffff, 0x00070006,
- 
 
 537 
	0x9294, 0xffffffff, 0x00000001,
- 
 
 538 
	0x929c, 0xffffffff, 0x00000002,
- 
 
 539 
	0x92a0, 0xffffffff, 0x00040003,
- 
 
 540 
	0x92a4, 0xffffffff, 0x00000005
- 
 
 541 
};
- 
 
 542 
 
- 
 
 543 
static const u32 rv740_golden_registers[] =
- 
 
 544 
{
- 
 
 545 
	0x88c4, 0xffffffff, 0x00000082,
- 
 
 546 
	0x28a50, 0xfffffffc, 0x00000004,
- 
 
 547 
	0x2650, 0x00040000, 0,
- 
 
 548 
	0x20bc, 0x00040000, 0,
- 
 
 549 
	0x733c, 0xffffffff, 0x00000002,
- 
 
 550 
	0x7300, 0xffffffff, 0x001000f0,
- 
 
 551 
	0x3f90, 0x00ff0000, 0,
- 
 
 552 
	0x9148, 0x00ff0000, 0,
- 
 
 553 
	0x3f94, 0x00ff0000, 0,
- 
 
 554 
	0x914c, 0x00ff0000, 0,
- 
 
 555 
	0x240c, 0xffffffff, 0x00000380,
- 
 
 556 
	0x8a14, 0x00000007, 0x00000007,
- 
 
 557 
	0x8b24, 0xffffffff, 0x00ff0fff,
- 
 
 558 
	0x28a4c, 0xffffffff, 0x00004000,
- 
 
 559 
	0xa180, 0xffffffff, 0x00003f3f,
- 
 
 560 
	0x8d00, 0xffffffff, 0x0e0e003a,
- 
 
 561 
	0x8d04, 0xffffffff, 0x013a0e2a,
- 
 
 562 
	0x8c00, 0xffffffff, 0xe400000f,
- 
 
 563 
	0x8db0, 0xffffffff, 0x98989898,
- 
 
 564 
	0x8db4, 0xffffffff, 0x98989898,
- 
 
 565 
	0x8db8, 0xffffffff, 0x98989898,
- 
 
 566 
	0x8dbc, 0xffffffff, 0x98989898,
- 
 
 567 
	0x8dc0, 0xffffffff, 0x98989898,
- 
 
 568 
	0x8dc4, 0xffffffff, 0x98989898,
- 
 
 569 
	0x8dc8, 0xffffffff, 0x98989898,
- 
 
 570 
	0x8dcc, 0xffffffff, 0x98989898,
- 
 
 571 
	0x9058, 0xffffffff, 0x0fffc40f,
- 
 
 572 
	0x900c, 0xffffffff, 0x003b033f,
- 
 
 573 
	0x28350, 0xffffffff, 0,
- 
 
 574 
	0x8cf0, 0x1fffffff, 0x08e00420,
- 
 
 575 
	0x9508, 0xffffffff, 0x00000002,
- 
 
 576 
	0x88c4, 0xffffffff, 0x000000c2,
- 
 
 577 
	0x9698, 0x18000000, 0x18000000
- 
 
 578 
};
- 
 
 579 
 
- 
 
 580 
static const u32 rv740_mgcg_init[] =
- 
 
 581 
{
- 
 
 582 
	0x8bcc, 0xffffffff, 0x13030100,
- 
 
 583 
	0x5448, 0xffffffff, 0x100,
- 
 
 584 
	0x55e4, 0xffffffff, 0x100,
- 
 
 585 
	0x160c, 0xffffffff, 0x100,
- 
 
 586 
	0x5644, 0xffffffff, 0x100,
- 
 
 587 
	0xc164, 0xffffffff, 0x100,
- 
 
 588 
	0x8a18, 0xffffffff, 0x100,
- 
 
 589 
	0x897c, 0xffffffff, 0x100,
- 
 
 590 
	0x8b28, 0xffffffff, 0x100,
- 
 
 591 
	0x9144, 0xffffffff, 0x100,
- 
 
 592 
	0x9a1c, 0xffffffff, 0x10000,
- 
 
 593 
	0x9a50, 0xffffffff, 0x100,
- 
 
 594 
	0x9a1c, 0xffffffff, 0x10001,
- 
 
 595 
	0x9a50, 0xffffffff, 0x100,
- 
 
 596 
	0x9a1c, 0xffffffff, 0x10002,
- 
 
 597 
	0x9a50, 0xffffffff, 0x100,
- 
 
 598 
	0x9a1c, 0xffffffff, 0x10003,
- 
 
 599 
	0x9a50, 0xffffffff, 0x100,
- 
 
 600 
	0x9a1c, 0xffffffff, 0x0,
- 
 
 601 
	0x9870, 0xffffffff, 0x100,
- 
 
 602 
	0x8d58, 0xffffffff, 0x100,
- 
 
 603 
	0x9500, 0xffffffff, 0x0,
- 
 
 604 
	0x9510, 0xffffffff, 0x100,
- 
 
 605 
	0x9500, 0xffffffff, 0x1,
- 
 
 606 
	0x9510, 0xffffffff, 0x100,
- 
 
 607 
	0x9500, 0xffffffff, 0x2,
- 
 
 608 
	0x9510, 0xffffffff, 0x100,
- 
 
 609 
	0x9500, 0xffffffff, 0x3,
- 
 
 610 
	0x9510, 0xffffffff, 0x100,
- 
 
 611 
	0x9500, 0xffffffff, 0x4,
- 
 
 612 
	0x9510, 0xffffffff, 0x100,
- 
 
 613 
	0x9500, 0xffffffff, 0x5,
- 
 
 614 
	0x9510, 0xffffffff, 0x100,
- 
 
 615 
	0x9500, 0xffffffff, 0x6,
- 
 
 616 
	0x9510, 0xffffffff, 0x100,
- 
 
 617 
	0x9500, 0xffffffff, 0x7,
- 
 
 618 
	0x9510, 0xffffffff, 0x100,
- 
 
 619 
	0x9500, 0xffffffff, 0x8000,
- 
 
 620 
	0x9490, 0xffffffff, 0x0,
- 
 
 621 
	0x949c, 0xffffffff, 0x100,
- 
 
 622 
	0x9490, 0xffffffff, 0x1,
- 
 
 623 
	0x949c, 0xffffffff, 0x100,
- 
 
 624 
	0x9490, 0xffffffff, 0x2,
- 
 
 625 
	0x949c, 0xffffffff, 0x100,
- 
 
 626 
	0x9490, 0xffffffff, 0x3,
- 
 
 627 
	0x949c, 0xffffffff, 0x100,
- 
 
 628 
	0x9490, 0xffffffff, 0x4,
- 
 
 629 
	0x949c, 0xffffffff, 0x100,
- 
 
 630 
	0x9490, 0xffffffff, 0x5,
- 
 
 631 
	0x949c, 0xffffffff, 0x100,
- 
 
 632 
	0x9490, 0xffffffff, 0x6,
- 
 
 633 
	0x949c, 0xffffffff, 0x100,
- 
 
 634 
	0x9490, 0xffffffff, 0x7,
- 
 
 635 
	0x949c, 0xffffffff, 0x100,
- 
 
 636 
	0x9490, 0xffffffff, 0x8000,
- 
 
 637 
	0x9604, 0xffffffff, 0x0,
- 
 
 638 
	0x9654, 0xffffffff, 0x100,
- 
 
 639 
	0x9604, 0xffffffff, 0x1,
- 
 
 640 
	0x9654, 0xffffffff, 0x100,
- 
 
 641 
	0x9604, 0xffffffff, 0x2,
- 
 
 642 
	0x9654, 0xffffffff, 0x100,
- 
 
 643 
	0x9604, 0xffffffff, 0x3,
- 
 
 644 
	0x9654, 0xffffffff, 0x100,
- 
 
 645 
	0x9604, 0xffffffff, 0x4,
- 
 
 646 
	0x9654, 0xffffffff, 0x100,
- 
 
 647 
	0x9604, 0xffffffff, 0x5,
- 
 
 648 
	0x9654, 0xffffffff, 0x100,
- 
 
 649 
	0x9604, 0xffffffff, 0x6,
- 
 
 650 
	0x9654, 0xffffffff, 0x100,
- 
 
 651 
	0x9604, 0xffffffff, 0x7,
- 
 
 652 
	0x9654, 0xffffffff, 0x100,
- 
 
 653 
	0x9604, 0xffffffff, 0x80000000,
- 
 
 654 
	0x9030, 0xffffffff, 0x100,
- 
 
 655 
	0x9034, 0xffffffff, 0x100,
- 
 
 656 
	0x9038, 0xffffffff, 0x100,
- 
 
 657 
	0x903c, 0xffffffff, 0x100,
- 
 
 658 
	0x9040, 0xffffffff, 0x100,
- 
 
 659 
	0xa200, 0xffffffff, 0x100,
- 
 
 660 
	0xa204, 0xffffffff, 0x100,
- 
 
 661 
	0xa208, 0xffffffff, 0x100,
- 
 
 662 
	0xa20c, 0xffffffff, 0x100,
- 
 
 663 
	0x971c, 0xffffffff, 0x100,
- 
 
 664 
	0x915c, 0xffffffff, 0x00020001,
- 
 
 665 
	0x9160, 0xffffffff, 0x00040003,
- 
 
 666 
	0x916c, 0xffffffff, 0x00060005,
- 
 
 667 
	0x9170, 0xffffffff, 0x00080007,
- 
 
 668 
	0x9174, 0xffffffff, 0x000a0009,
- 
 
 669 
	0x9178, 0xffffffff, 0x000c000b,
- 
 
 670 
	0x917c, 0xffffffff, 0x000e000d,
- 
 
 671 
	0x9180, 0xffffffff, 0x0010000f,
- 
 
 672 
	0x918c, 0xffffffff, 0x00120011,
- 
 
 673 
	0x9190, 0xffffffff, 0x00140013,
- 
 
 674 
	0x9194, 0xffffffff, 0x00020001,
- 
 
 675 
	0x9198, 0xffffffff, 0x00040003,
- 
 
 676 
	0x919c, 0xffffffff, 0x00060005,
- 
 
 677 
	0x91a8, 0xffffffff, 0x00080007,
- 
 
 678 
	0x91ac, 0xffffffff, 0x000a0009,
- 
 
 679 
	0x91b0, 0xffffffff, 0x000c000b,
- 
 
 680 
	0x91b4, 0xffffffff, 0x000e000d,
- 
 
 681 
	0x91b8, 0xffffffff, 0x0010000f,
- 
 
 682 
	0x91c4, 0xffffffff, 0x00120011,
- 
 
 683 
	0x91c8, 0xffffffff, 0x00140013,
- 
 
 684 
	0x91cc, 0xffffffff, 0x00020001,
- 
 
 685 
	0x91d0, 0xffffffff, 0x00040003,
- 
 
 686 
	0x91d4, 0xffffffff, 0x00060005,
- 
 
 687 
	0x91e0, 0xffffffff, 0x00080007,
- 
 
 688 
	0x91e4, 0xffffffff, 0x000a0009,
- 
 
 689 
	0x91e8, 0xffffffff, 0x000c000b,
- 
 
 690 
	0x91ec, 0xffffffff, 0x00020001,
- 
 
 691 
	0x91f0, 0xffffffff, 0x00040003,
- 
 
 692 
	0x91f4, 0xffffffff, 0x00060005,
- 
 
 693 
	0x9200, 0xffffffff, 0x00080007,
- 
 
 694 
	0x9204, 0xffffffff, 0x000a0009,
- 
 
 695 
	0x9208, 0xffffffff, 0x000c000b,
- 
 
 696 
	0x920c, 0xffffffff, 0x000e000d,
- 
 
 697 
	0x9210, 0xffffffff, 0x0010000f,
- 
 
 698 
	0x921c, 0xffffffff, 0x00120011,
- 
 
 699 
	0x9220, 0xffffffff, 0x00140013,
- 
 
 700 
	0x9224, 0xffffffff, 0x00020001,
- 
 
 701 
	0x9228, 0xffffffff, 0x00040003,
- 
 
 702 
	0x922c, 0xffffffff, 0x00060005,
- 
 
 703 
	0x9238, 0xffffffff, 0x00080007,
- 
 
 704 
	0x923c, 0xffffffff, 0x000a0009,
- 
 
 705 
	0x9240, 0xffffffff, 0x000c000b,
- 
 
 706 
	0x9244, 0xffffffff, 0x000e000d,
- 
 
 707 
	0x9248, 0xffffffff, 0x0010000f,
- 
 
 708 
	0x9254, 0xffffffff, 0x00120011,
- 
 
 709 
	0x9258, 0xffffffff, 0x00140013,
- 
 
 710 
	0x9294, 0xffffffff, 0x00020001,
- 
 
 711 
	0x929c, 0xffffffff, 0x00040003,
- 
 
 712 
	0x92a0, 0xffffffff, 0x00060005,
- 
 
 713 
	0x92a4, 0xffffffff, 0x00080007
- 
 
 714 
};
- 
 
 715 
 
- 
 
 716 
static void rv770_init_golden_registers(struct radeon_device *rdev)
- 
 
 717 
{
- 
 
 718 
	switch (rdev->family) {
- 
 
 719 
	case CHIP_RV770:
- 
 
 720 
		radeon_program_register_sequence(rdev,
- 
 
 721 
						 r7xx_golden_registers,
- 
 
 722 
						 (const u32)ARRAY_SIZE(r7xx_golden_registers));
- 
 
 723 
		radeon_program_register_sequence(rdev,
- 
 
 724 
						 r7xx_golden_dyn_gpr_registers,
- 
 
 725 
						 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
- 
 
 726 
		if (rdev->pdev->device == 0x994e)
- 
 
 727 
			radeon_program_register_sequence(rdev,
- 
 
 728 
							 rv770ce_golden_registers,
- 
 
 729 
							 (const u32)ARRAY_SIZE(rv770ce_golden_registers));
- 
 
 730 
		else
- 
 
 731 
			radeon_program_register_sequence(rdev,
- 
 
 732 
							 rv770_golden_registers,
- 
 
 733 
							 (const u32)ARRAY_SIZE(rv770_golden_registers));
- 
 
 734 
		radeon_program_register_sequence(rdev,
- 
 
 735 
						 rv770_mgcg_init,
- 
 
 736 
						 (const u32)ARRAY_SIZE(rv770_mgcg_init));
- 
 
 737 
		break;
- 
 
 738 
	case CHIP_RV730:
- 
 
 739 
		radeon_program_register_sequence(rdev,
- 
 
 740 
						 r7xx_golden_registers,
- 
 
 741 
						 (const u32)ARRAY_SIZE(r7xx_golden_registers));
- 
 
 742 
		radeon_program_register_sequence(rdev,
- 
 
 743 
						 r7xx_golden_dyn_gpr_registers,
- 
 
 744 
						 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
- 
 
 745 
		radeon_program_register_sequence(rdev,
- 
 
 746 
						 rv730_golden_registers,
- 
 
 747 
						 (const u32)ARRAY_SIZE(rv770_golden_registers));
- 
 
 748 
		radeon_program_register_sequence(rdev,
- 
 
 749 
						 rv730_mgcg_init,
- 
 
 750 
						 (const u32)ARRAY_SIZE(rv770_mgcg_init));
- 
 
 751 
		break;
- 
 
 752 
	case CHIP_RV710:
- 
 
 753 
		radeon_program_register_sequence(rdev,
- 
 
 754 
						 r7xx_golden_registers,
- 
 
 755 
						 (const u32)ARRAY_SIZE(r7xx_golden_registers));
- 
 
 756 
		radeon_program_register_sequence(rdev,
- 
 
 757 
						 r7xx_golden_dyn_gpr_registers,
- 
 
 758 
						 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
- 
 
 759 
		radeon_program_register_sequence(rdev,
- 
 
 760 
						 rv710_golden_registers,
- 
 
 761 
						 (const u32)ARRAY_SIZE(rv770_golden_registers));
- 
 
 762 
		radeon_program_register_sequence(rdev,
- 
 
 763 
						 rv710_mgcg_init,
- 
 
 764 
						 (const u32)ARRAY_SIZE(rv770_mgcg_init));
- 
 
 765 
		break;
- 
 
 766 
	case CHIP_RV740:
- 
 
 767 
		radeon_program_register_sequence(rdev,
- 
 
 768 
						 rv740_golden_registers,
- 
 
 769 
						 (const u32)ARRAY_SIZE(rv770_golden_registers));
- 
 
 770 
		radeon_program_register_sequence(rdev,
- 
 
 771 
						 rv740_mgcg_init,
- 
 
 772 
						 (const u32)ARRAY_SIZE(rv770_mgcg_init));
- 
 
 773 
		break;
- 
 
 774 
	default:
- 
 
 775 
		break;
- 
 
 776 
	}
- 
 
 777 
}
- 
 
 778 
 
- 
 
 779 
#define PCIE_BUS_CLK                10000
- 
 
 780 
#define TCLK                        (PCIE_BUS_CLK / 10)
- 
 
 781 
 
- 
 
 782 
/**
- 
 
 783 
 * rv770_get_xclk - get the xclk
- 
 
 784 
 *
- 
 
 785 
 * @rdev: radeon_device pointer
- 
 
 786 
 *
- 
 
 787 
 * Returns the reference clock used by the gfx engine
- 
 
 788 
 * (r7xx-cayman).
- 
 
 789 
 */
- 
 
 790 
u32 rv770_get_xclk(struct radeon_device *rdev)
- 
 
 791 
{
- 
 
 792 
	u32 reference_clock = rdev->clock.spll.reference_freq;
- 
 
 793 
	u32 tmp = RREG32(CG_CLKPIN_CNTL);
- 
 
 794 
 
- 
 
 795 
	if (tmp & MUX_TCLK_TO_XCLK)
- 
 
 796 
		return TCLK;
- 
 
 797 
 
- 
 
 798 
	if (tmp & XTALIN_DIVIDE)
- 
 
 799 
		return reference_clock / 4;
- 
 
 800 
 
- 
 
 801 
	return reference_clock;
- 
 
 802 
}
- 
 
 803 
 
- 
 
 804 
u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
- 
 
 805 
{
- 
 
 806 
	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
- 
 
 807 
	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
- 
 
 808 
	int i;
- 
 
 809 
 
- 
 
 810 
	/* Lock the graphics update lock */
- 
 
 811 
	tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
- 
 
 812 
	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
- 
 
 813 
 
- 
 
 814 
	/* update the scanout addresses */
- 
 
 815 
	if (radeon_crtc->crtc_id) {
- 
 
 816 
		WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
- 
 
 817 
		WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
- 
 
 818 
	} else {
- 
 
 819 
		WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
- 
 
 820 
		WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
- 
 
 821 
	}
- 
 
 822 
	WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
- 
 
 823 
	       (u32)crtc_base);
- 
 
 824 
	WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
- 
 
 825 
	       (u32)crtc_base);
- 
 
 826 
 
- 
 
 827 
	/* Wait for update_pending to go high. */
- 
 
 828 
	for (i = 0; i < rdev->usec_timeout; i++) {
- 
 
 829 
		if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
- 
 
 830 
			break;
- 
 
 831 
		udelay(1);
- 
 
 832 
	}
- 
 
 833 
	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
- 
 
 834 
 
- 
 
 835 
	/* Unlock the lock, so double-buffering can take place inside vblank */
- 
 
 836 
	tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
- 
 
 837 
	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
- 
 
 838 
 
- 
 
 839 
	/* Return current update_pending status: */
- 
 
 840 
	return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
- 
 
 841 
}
- 
 
 842 
 
- 
 
 843 
/* get temperature in millidegrees */
- 
 
 844 
int rv770_get_temp(struct radeon_device *rdev)
- 
 
 845 
{
- 
 
 846 
	u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
- 
 
 847 
		ASIC_T_SHIFT;
- 
 
 848 
	int actual_temp;
- 
 
 849 
 
- 
 
 850 
	if (temp & 0x400)
- 
 
 851 
		actual_temp = -256;
- 
 
 852 
	else if (temp & 0x200)
- 
 
 853 
		actual_temp = 255;
- 
 
 854 
	else if (temp & 0x100) {
- 
 
 855 
		actual_temp = temp & 0x1ff;
- 
 
 856 
		actual_temp |= ~0x1ff;
- 
 
 857 
	} else
- 
 
 858 
		actual_temp = temp & 0xff;
- 
 
 859 
 
- 
 
 860 
	return (actual_temp * 1000) / 2;
- 
 
 861 
}
- 
 
 862 
 
- 
 
 863 
void rv770_pm_misc(struct radeon_device *rdev)
- 
 
 864 
{
- 
 
 865 
	int req_ps_idx = rdev->pm.requested_power_state_index;
- 
 
 866 
	int req_cm_idx = rdev->pm.requested_clock_mode_index;
- 
 
 867 
	struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
- 
 
 868 
	struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
- 
 
 869 
 
- 
 
 870 
	if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
- 
 
 871 
		/* 0xff01 is a flag rather then an actual voltage */
- 
 
 872 
		if (voltage->voltage == 0xff01)
- 
 
 873 
			return;
- 
 
 874 
		if (voltage->voltage != rdev->pm.current_vddc) {
- 
 
 875 
			radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
- 
 
 876 
			rdev->pm.current_vddc = voltage->voltage;
- 
 
 877 
			DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
- 
 
 878 
		}
Line 44... Line 879...
44 
static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
 879 
	}
45 
 
 880 
}
46 
 
 881 
 
47 
/*
 882 
/*
Line 500... Line 1335...
500 
	WREG32(GB_TILING_CONFIG, gb_tiling_config);
 1335 
	WREG32(GB_TILING_CONFIG, gb_tiling_config);
501 
	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 1336 
	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
502 
	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 1337 
	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
503 
	WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
 1338 
	WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
504 
	WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
 1339 
	WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
- 
 
 1340 
	if (rdev->family == CHIP_RV730) {
- 
 
 1341 
		WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
- 
 
 1342 
		WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
- 
 
 1343 
		WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
- 
 
 1344 
	}
Line 505... Line 1345...
505 
 
 1345 
 
506 
	WREG32(CGTS_SYS_TCC_DISABLE, 0);
 1346 
	WREG32(CGTS_SYS_TCC_DISABLE, 0);
507 
	WREG32(CGTS_TCC_DISABLE, 0);
 1347 
	WREG32(CGTS_TCC_DISABLE, 0);
508 
	WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
 1348 
	WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
Line 729... Line 1569...
729 
		mc->real_vram_size = 0xE0000000;
 1569 
		mc->real_vram_size = 0xE0000000;
730 
		mc->mc_vram_size = 0xE0000000;
 1570 
		mc->mc_vram_size = 0xE0000000;
731 
	}
 1571 
	}
732 
	if (rdev->flags & RADEON_IS_AGP) {
 1572 
	if (rdev->flags & RADEON_IS_AGP) {
733 
		size_bf = mc->gtt_start;
 1573 
		size_bf = mc->gtt_start;
734 
		size_af = 0xFFFFFFFF - mc->gtt_end;
 1574 
		size_af = mc->mc_mask - mc->gtt_end;
735 
		if (size_bf > size_af) {
 1575 
		if (size_bf > size_af) {
736 
			if (mc->mc_vram_size > size_bf) {
 1576 
			if (mc->mc_vram_size > size_bf) {
737 
				dev_warn(rdev->dev, "limiting VRAM\n");
 1577 
				dev_warn(rdev->dev, "limiting VRAM\n");
738 
				mc->real_vram_size = size_bf;
 1578 
				mc->real_vram_size = size_bf;
739 
				mc->mc_vram_size = size_bf;
 1579 
				mc->mc_vram_size = size_bf;
Line 801... Line 1641...
801 
	radeon_update_bandwidth_info(rdev);
 1641 
	radeon_update_bandwidth_info(rdev);
Line 802... Line 1642...
802 
 
 1642 
 
803 
	return 0;
 1643 
	return 0;
Line -... Line 1644...
- 
 
 1644 
}
- 
 
 1645 
 
- 
 
 1646 
/**
- 
 
 1647 
 * rv770_copy_dma - copy pages using the DMA engine
- 
 
 1648 
 *
- 
 
 1649 
 * @rdev: radeon_device pointer
- 
 
 1650 
 * @src_offset: src GPU address
- 
 
 1651 
 * @dst_offset: dst GPU address
- 
 
 1652 
 * @num_gpu_pages: number of GPU pages to xfer
- 
 
 1653 
 * @fence: radeon fence object
- 
 
 1654 
 *
- 
 
 1655 
 * Copy GPU paging using the DMA engine (r7xx).
- 
 
 1656 
 * Used by the radeon ttm implementation to move pages if
- 
 
 1657 
 * registered as the asic copy callback.
- 
 
 1658 
 */
- 
 
 1659 
int rv770_copy_dma(struct radeon_device *rdev,
- 
 
 1660 
		  uint64_t src_offset, uint64_t dst_offset,
- 
 
 1661 
		  unsigned num_gpu_pages,
- 
 
 1662 
		  struct radeon_fence **fence)
- 
 
 1663 
{
- 
 
 1664 
	struct radeon_semaphore *sem = NULL;
- 
 
 1665 
	int ring_index = rdev->asic->copy.dma_ring_index;
- 
 
 1666 
	struct radeon_ring *ring = &rdev->ring[ring_index];
- 
 
 1667 
	u32 size_in_dw, cur_size_in_dw;
- 
 
 1668 
	int i, num_loops;
- 
 
 1669 
	int r = 0;
- 
 
 1670 
 
- 
 
 1671 
	r = radeon_semaphore_create(rdev, &sem);
- 
 
 1672 
	if (r) {
- 
 
 1673 
		DRM_ERROR("radeon: moving bo (%d).\n", r);
- 
 
 1674 
		return r;
- 
 
 1675 
	}
- 
 
 1676 
 
- 
 
 1677 
	size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
- 
 
 1678 
	num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
- 
 
 1679 
	r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
- 
 
 1680 
	if (r) {
- 
 
 1681 
		DRM_ERROR("radeon: moving bo (%d).\n", r);
- 
 
 1682 
		radeon_semaphore_free(rdev, &sem, NULL);
- 
 
 1683 
		return r;
- 
 
 1684 
	}
- 
 
 1685 
 
- 
 
 1686 
	if (radeon_fence_need_sync(*fence, ring->idx)) {
- 
 
 1687 
		radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
- 
 
 1688 
					    ring->idx);
- 
 
 1689 
		radeon_fence_note_sync(*fence, ring->idx);
- 
 
 1690 
	} else {
- 
 
 1691 
		radeon_semaphore_free(rdev, &sem, NULL);
- 
 
 1692 
	}
- 
 
 1693 
 
- 
 
 1694 
	for (i = 0; i < num_loops; i++) {
- 
 
 1695 
		cur_size_in_dw = size_in_dw;
- 
 
 1696 
		if (cur_size_in_dw > 0xFFFF)
- 
 
 1697 
			cur_size_in_dw = 0xFFFF;
- 
 
 1698 
		size_in_dw -= cur_size_in_dw;
- 
 
 1699 
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
- 
 
 1700 
		radeon_ring_write(ring, dst_offset & 0xfffffffc);
- 
 
 1701 
		radeon_ring_write(ring, src_offset & 0xfffffffc);
- 
 
 1702 
		radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
- 
 
 1703 
		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
- 
 
 1704 
		src_offset += cur_size_in_dw * 4;
- 
 
 1705 
		dst_offset += cur_size_in_dw * 4;
- 
 
 1706 
	}
- 
 
 1707 
 
- 
 
 1708 
	r = radeon_fence_emit(rdev, fence, ring->idx);
- 
 
 1709 
	if (r) {
- 
 
 1710 
		radeon_ring_unlock_undo(rdev, ring);
- 
 
 1711 
		return r;
- 
 
 1712 
	}
- 
 
 1713 
 
- 
 
 1714 
	radeon_ring_unlock_commit(rdev, ring);
- 
 
 1715 
	radeon_semaphore_free(rdev, &sem, *fence);
- 
 
 1716 
 
- 
 
 1717 
	return r;
804 
}
 1718 
}
805 
 
 1719 
 
806 
static int rv770_startup(struct radeon_device *rdev)
 1720 
static int rv770_startup(struct radeon_device *rdev)
807 
{
 1721 
{
Line 838... Line 1752...
838 
		r600_blit_fini(rdev);
 1752 
		r600_blit_fini(rdev);
839 
		rdev->asic->copy.copy = NULL;
 1753 
		rdev->asic->copy.copy = NULL;
840 
		dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
 1754 
		dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
841 
	}
 1755 
	}
Line 842... Line -...
842 
 
 - 
 
843 
//    r = r600_video_init(rdev);
 - 
 
844 
//    if (r) {
 - 
 
845 
//      r600_video_fini(rdev);
 - 
 
846 
//        rdev->asic->copy = NULL;
 - 
 
847 
//        dev_warn(rdev->dev, "failed video blitter (%d) falling back to memcpy\n", r);
 - 
 
848 
//    }
 - 
 
849 
 
 1756 
 
850 
	/* allocate wb buffer */
 1757 
	/* allocate wb buffer */
851 
	r = radeon_wb_init(rdev);
 1758 
	r = radeon_wb_init(rdev);
852 
	if (r)
 1759 
	if (r)
Line 862... Line 1769...
862 
	if (r) {
 1769 
	if (r) {
863 
		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
 1770 
		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
864 
		return r;
 1771 
		return r;
865 
	}
 1772 
	}
Line -... Line 1773...
- 
 
 1773 
 
- 
 
 1774 
//   r = rv770_uvd_resume(rdev);
- 
 
 1775 
//   if (!r) {
- 
 
 1776 
//       r = radeon_fence_driver_start_ring(rdev,
- 
 
 1777 
//                          R600_RING_TYPE_UVD_INDEX);
- 
 
 1778 
//       if (r)
- 
 
 1779 
//           dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
- 
 
 1780 
//   }
- 
 
 1781 
 
- 
 
 1782 
//   if (r)
- 
 
 1783 
//       rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
866 
 
 1784 
 
- 
 
 1785 
	/* Enable IRQ */
- 
 
 1786 
	if (!rdev->irq.installed) {
- 
 
 1787 
		r = radeon_irq_kms_init(rdev);
- 
 
 1788 
		if (r)
- 
 
 1789 
			return r;
- 
 
 1790 
	}
867 
	/* Enable IRQ */
 1791 
 
868 
	r = r600_irq_init(rdev);
 1792 
	r = r600_irq_init(rdev);
869 
	if (r) {
 1793 
	if (r) {
870 
		DRM_ERROR("radeon: IH init failed (%d).\n", r);
 1794 
		DRM_ERROR("radeon: IH init failed (%d).\n", r);
871 
//		radeon_irq_kms_fini(rdev);
 1795 
//		radeon_irq_kms_fini(rdev);
Line 896... Line 1820...
896 
 
 1820 
 
897 
	r = r600_dma_resume(rdev);
 1821 
	r = r600_dma_resume(rdev);
898 
	if (r)
 1822 
	if (r)
Line -... Line 1823...
- 
 
 1823 
		return r;
- 
 
 1824 
 
- 
 
 1825 
//   ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
- 
 
 1826 
//   if (ring->ring_size) {
- 
 
 1827 
//       r = radeon_ring_init(rdev, ring, ring->ring_size,
- 
 
 1828 
//                    R600_WB_UVD_RPTR_OFFSET,
- 
 
 1829 
//                    UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
- 
 
 1830 
//                    0, 0xfffff, RADEON_CP_PACKET2);
- 
 
 1831 
//       if (!r)
- 
 
 1832 
//           r = r600_uvd_init(rdev);
- 
 
 1833 
 
- 
 
 1834 
//       if (r)
- 
 
 1835 
//           DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
899 
		return r;
 1836 
//   }
900 
 
 1837 
 
901 
	r = radeon_ib_pool_init(rdev);
 1838 
	r = radeon_ib_pool_init(rdev);
902 
	if (r) {
 1839 
	if (r) {
903 
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 1840 
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
Line 944... Line 1881...
944 
			return -EINVAL;
 1881 
			return -EINVAL;
945 
		}
 1882 
		}
946 
		DRM_INFO("GPU not posted. posting now...\n");
 1883 
		DRM_INFO("GPU not posted. posting now...\n");
947 
		atom_asic_init(rdev->mode_info.atom_context);
 1884 
		atom_asic_init(rdev->mode_info.atom_context);
948 
	}
 1885 
	}
- 
 
 1886 
	/* init golden registers */
- 
 
 1887 
	rv770_init_golden_registers(rdev);
949 
	/* Initialize scratch registers */
 1888 
	/* Initialize scratch registers */
950 
	r600_scratch_init(rdev);
 1889 
	r600_scratch_init(rdev);
951 
	/* Initialize surface registers */
 1890 
	/* Initialize surface registers */
952 
	radeon_surface_init(rdev);
 1891 
	radeon_surface_init(rdev);
953 
	/* Initialize clocks */
 1892 
	/* Initialize clocks */
Line 968... Line 1907...
968 
	/* Memory manager */
 1907 
	/* Memory manager */
969 
	r = radeon_bo_init(rdev);
 1908 
	r = radeon_bo_init(rdev);
970 
	if (r)
 1909 
	if (r)
971 
		return r;
 1910 
		return r;
Line 972... Line -...
972 
 
 - 
 
973 
	r = radeon_irq_kms_init(rdev);
 - 
 
974 
	if (r)
 - 
 
975 
		return r;
 - 
 
976 
 
 1911 
 
977 
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
 1912 
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
Line 978... Line 1913...
978 
	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 1913 
	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
979 
 
 1914 
 
Line -... Line 1915...
- 
 
 1915 
	rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
- 
 
 1916 
	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
- 
 
 1917 
 
- 
 
 1918 
//   r = radeon_uvd_init(rdev);
- 
 
 1919 
//   if (!r) {
- 
 
 1920 
//       rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
- 
 
 1921 
//       r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
980 
	rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
 1922 
//                  4096);
981 
	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
 1923 
//   }
Line 982... Line 1924...
982 
 
 1924 
 
983 
	rdev->ih.ring_obj = NULL;
 1925 
	rdev->ih.ring_obj = NULL;
Line 1000... Line 1942...
1000 
 
 1942 
 
1001 
static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
 1943 
static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1002 
{
 1944 
{
1003 
	u32 link_width_cntl, lanes, speed_cntl, tmp;
 1945 
	u32 link_width_cntl, lanes, speed_cntl, tmp;
1004 
	u16 link_cntl2;
 - 
 
1005 
	u32 mask;
 - 
 
Line 1006... Line 1946...
1006 
	int ret;
 1946 
	u16 link_cntl2;
1007 
 
 1947 
 
Line 1008... Line 1948...
1008 
	if (radeon_pcie_gen2 == 0)
 1948 
	if (radeon_pcie_gen2 == 0)
Line 1016... Line 1956...
1016 
 
 1956 
 
1017 
	/* x2 cards have a special sequence */
 1957 
	/* x2 cards have a special sequence */
1018 
	if (ASIC_IS_X2(rdev))
 1958 
	if (ASIC_IS_X2(rdev))
Line 1019... Line 1959...
1019 
		return;
 1959 
		return;
1020 
 
 - 
 
1021 
	ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
 - 
 
1022 
	if (ret != 0)
 - 
 
1023 
		return;
 1960 
 
1024 
 
 1961 
	if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
Line 1025... Line 1962...
1025 
	if (!(mask & DRM_PCIE_SPEED_50))
 1962 
		(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
Line 1026... Line 1963...
1026 
		return;
 1963 
		return;
1027 
 
 1964 
 
1028 
	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
 1965 
	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
1029 
 
 1966 
 
1030 
	/* advertise upconfig capability */
 1967 
	/* advertise upconfig capability */
1031 
	link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
 1968 
	link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1032 
	link_width_cntl &= ~LC_UPCONFIGURE_DIS;
 1969 
	link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1033 
	WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 1970 
	WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1034 
	link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
 1971 
	link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1035 
	if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
 1972 
	if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1036 
		lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
 1973 
		lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1037 
		link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
 1974 
		link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1038 
				     LC_RECONFIG_ARC_MISSING_ESCAPE);
 1975 
				     LC_RECONFIG_ARC_MISSING_ESCAPE);
1039 
		link_width_cntl |= lanes | LC_RECONFIG_NOW |
 1976 
		link_width_cntl |= lanes | LC_RECONFIG_NOW |
1040 
			LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
 1977 
			LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1041 
		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 1978 
		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
Line 1042... Line 1979...
1042 
	} else {
 1979 
	} else {
1043 
		link_width_cntl |= LC_UPCONFIGURE_DIS;
 1980 
		link_width_cntl |= LC_UPCONFIGURE_DIS;
1044 
		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 1981 
		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
Line 1045... Line 1982...
1045 
	}
 1982 
	}
1046 
 
 1983 
 
Line 1055... Line 1992...
1055 
		link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
 1992 
		link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1056 
		link_cntl2 |= 0x2;
 1993 
		link_cntl2 |= 0x2;
1057 
		WREG16(0x4088, link_cntl2);
 1994 
		WREG16(0x4088, link_cntl2);
1058 
		WREG32(MM_CFGREGS_CNTL, 0);
 1995 
		WREG32(MM_CFGREGS_CNTL, 0);
Line 1059... Line 1996...
1059 
 
 1996 
 
1060 
		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
 1997 
		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1061 
		speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
 1998 
		speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
Line 1062... Line 1999...
1062 
		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
 1999 
		WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1063 
 
 2000 
 
1064 
		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
 2001 
		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
Line 1065... Line 2002...
1065 
		speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
 2002 
		speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1066 
		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
 2003 
		WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1067 
 
 2004 
 
Line 1068... Line 2005...
1068 
		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
 2005 
		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1069 
		speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
 2006 
		speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1070 
		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
 2007 
		WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
Line 1071... Line 2008...
1071 
 
 2008 
 
1072 
		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
 2009 
		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1073 
		speed_cntl |= LC_GEN2_EN_STRAP;
 2010 
		speed_cntl |= LC_GEN2_EN_STRAP;
1074 
		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
 2011 
		WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1075 
 
 2012 
 
1076 
	} else {
 2013 
	} else {
1077 
		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
 2014 
		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1078 
		/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
 2015 
		/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1079 
		if (1)
 2016 
		if (1)
1080 
			link_width_cntl |= LC_UPCONFIGURE_DIS;
 2017 
			link_width_cntl |= LC_UPCONFIGURE_DIS;