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| Rev 1413 | Rev 1430 | ||
|---|---|---|---|
| Line 54... | Line 54... | ||
| 54 | return -EINVAL; |
54 | return -EINVAL; |
| 55 | } |
55 | } |
| 56 | r = radeon_gart_table_vram_pin(rdev); |
56 | r = radeon_gart_table_vram_pin(rdev); |
| 57 | if (r) |
57 | if (r) |
| 58 | return r; |
58 | return r; |
| - | 59 | radeon_gart_restore(rdev); |
|
| 59 | /* Setup L2 cache */ |
60 | /* Setup L2 cache */ |
| 60 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
61 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| 61 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
62 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 62 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
63 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 63 | WREG32(VM_L2_CNTL2, 0); |
64 | WREG32(VM_L2_CNTL2, 0); |
| Line 271... | Line 272... | ||
| 271 | 272 | ||
| 272 | 273 | ||
| 273 | /* |
274 | /* |
| 274 | * Core functions |
275 | * Core functions |
| - | 276 | */ |
|
| 275 | */ |
277 | static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
| 276 | static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, |
278 | u32 num_tile_pipes, |
| 277 | u32 num_backends, |
279 | u32 num_backends, |
| 278 | u32 backend_disable_mask) |
280 | u32 backend_disable_mask) |
| 279 | { |
281 | { |
| 280 | u32 backend_map = 0; |
282 | u32 backend_map = 0; |
| 281 | u32 enabled_backends_mask; |
283 | u32 enabled_backends_mask; |
| 282 | u32 enabled_backends_count; |
284 | u32 enabled_backends_count; |
| 283 | u32 cur_pipe; |
285 | u32 cur_pipe; |
| 284 | u32 swizzle_pipe[R7XX_MAX_PIPES]; |
286 | u32 swizzle_pipe[R7XX_MAX_PIPES]; |
| - | 287 | u32 cur_backend; |
|
| Line 285... | Line 288... | ||
| 285 | u32 cur_backend; |
288 | u32 i; |
| 286 | u32 i; |
289 | bool force_no_swizzle; |
| 287 | 290 | ||
| 288 | if (num_tile_pipes > R7XX_MAX_PIPES) |
291 | if (num_tile_pipes > R7XX_MAX_PIPES) |
| Line 311... | Line 314... | ||
| 311 | } |
314 | } |
| Line 312... | Line 315... | ||
| 312 | 315 | ||
| 313 | if (enabled_backends_count != num_backends) |
316 | if (enabled_backends_count != num_backends) |
| Line -... | Line 317... | ||
| - | 317 | num_backends = enabled_backends_count; |
|
| - | 318 | ||
| - | 319 | switch (rdev->family) { |
|
| - | 320 | case CHIP_RV770: |
|
| - | 321 | case CHIP_RV730: |
|
| - | 322 | force_no_swizzle = false; |
|
| - | 323 | break; |
|
| - | 324 | case CHIP_RV710: |
|
| - | 325 | case CHIP_RV740: |
|
| - | 326 | default: |
|
| - | 327 | force_no_swizzle = true; |
|
| - | 328 | break; |
|
| 314 | num_backends = enabled_backends_count; |
329 | } |
| 315 | 330 | ||
| 316 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); |
331 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); |
| 317 | switch (num_tile_pipes) { |
332 | switch (num_tile_pipes) { |
| 318 | case 1: |
333 | case 1: |
| 319 | swizzle_pipe[0] = 0; |
334 | swizzle_pipe[0] = 0; |
| 320 | break; |
335 | break; |
| 321 | case 2: |
336 | case 2: |
| 322 | swizzle_pipe[0] = 0; |
337 | swizzle_pipe[0] = 0; |
| 323 | swizzle_pipe[1] = 1; |
338 | swizzle_pipe[1] = 1; |
| - | 339 | break; |
|
| - | 340 | case 3: |
|
| - | 341 | if (force_no_swizzle) { |
|
| - | 342 | swizzle_pipe[0] = 0; |
|
| - | 343 | swizzle_pipe[1] = 1; |
|
| 324 | break; |
344 | swizzle_pipe[2] = 2; |
| 325 | case 3: |
345 | } else { |
| 326 | swizzle_pipe[0] = 0; |
346 | swizzle_pipe[0] = 0; |
| - | 347 | swizzle_pipe[1] = 2; |
|
| 327 | swizzle_pipe[1] = 2; |
348 | swizzle_pipe[2] = 1; |
| 328 | swizzle_pipe[2] = 1; |
349 | } |
| - | 350 | break; |
|
| - | 351 | case 4: |
|
| - | 352 | if (force_no_swizzle) { |
|
| - | 353 | swizzle_pipe[0] = 0; |
|
| - | 354 | swizzle_pipe[1] = 1; |
|
| - | 355 | swizzle_pipe[2] = 2; |
|
| 329 | break; |
356 | swizzle_pipe[3] = 3; |
| 330 | case 4: |
357 | } else { |
| 331 | swizzle_pipe[0] = 0; |
358 | swizzle_pipe[0] = 0; |
| 332 | swizzle_pipe[1] = 2; |
359 | swizzle_pipe[1] = 2; |
| - | 360 | swizzle_pipe[2] = 3; |
|
| 333 | swizzle_pipe[2] = 3; |
361 | swizzle_pipe[3] = 1; |
| 334 | swizzle_pipe[3] = 1; |
362 | } |
| - | 363 | break; |
|
| - | 364 | case 5: |
|
| - | 365 | if (force_no_swizzle) { |
|
| - | 366 | swizzle_pipe[0] = 0; |
|
| - | 367 | swizzle_pipe[1] = 1; |
|
| - | 368 | swizzle_pipe[2] = 2; |
|
| - | 369 | swizzle_pipe[3] = 3; |
|
| 335 | break; |
370 | swizzle_pipe[4] = 4; |
| 336 | case 5: |
371 | } else { |
| 337 | swizzle_pipe[0] = 0; |
372 | swizzle_pipe[0] = 0; |
| 338 | swizzle_pipe[1] = 2; |
373 | swizzle_pipe[1] = 2; |
| 339 | swizzle_pipe[2] = 4; |
374 | swizzle_pipe[2] = 4; |
| - | 375 | swizzle_pipe[3] = 1; |
|
| 340 | swizzle_pipe[3] = 1; |
376 | swizzle_pipe[4] = 3; |
| 341 | swizzle_pipe[4] = 3; |
377 | } |
| - | 378 | break; |
|
| - | 379 | case 6: |
|
| - | 380 | if (force_no_swizzle) { |
|
| - | 381 | swizzle_pipe[0] = 0; |
|
| - | 382 | swizzle_pipe[1] = 1; |
|
| - | 383 | swizzle_pipe[2] = 2; |
|
| - | 384 | swizzle_pipe[3] = 3; |
|
| - | 385 | swizzle_pipe[4] = 4; |
|
| 342 | break; |
386 | swizzle_pipe[5] = 5; |
| 343 | case 6: |
387 | } else { |
| 344 | swizzle_pipe[0] = 0; |
388 | swizzle_pipe[0] = 0; |
| 345 | swizzle_pipe[1] = 2; |
389 | swizzle_pipe[1] = 2; |
| 346 | swizzle_pipe[2] = 4; |
390 | swizzle_pipe[2] = 4; |
| 347 | swizzle_pipe[3] = 5; |
391 | swizzle_pipe[3] = 5; |
| - | 392 | swizzle_pipe[4] = 3; |
|
| 348 | swizzle_pipe[4] = 3; |
393 | swizzle_pipe[5] = 1; |
| 349 | swizzle_pipe[5] = 1; |
394 | } |
| - | 395 | break; |
|
| - | 396 | case 7: |
|
| - | 397 | if (force_no_swizzle) { |
|
| - | 398 | swizzle_pipe[0] = 0; |
|
| - | 399 | swizzle_pipe[1] = 1; |
|
| - | 400 | swizzle_pipe[2] = 2; |
|
| - | 401 | swizzle_pipe[3] = 3; |
|
| - | 402 | swizzle_pipe[4] = 4; |
|
| - | 403 | swizzle_pipe[5] = 5; |
|
| 350 | break; |
404 | swizzle_pipe[6] = 6; |
| 351 | case 7: |
405 | } else { |
| 352 | swizzle_pipe[0] = 0; |
406 | swizzle_pipe[0] = 0; |
| 353 | swizzle_pipe[1] = 2; |
407 | swizzle_pipe[1] = 2; |
| 354 | swizzle_pipe[2] = 4; |
408 | swizzle_pipe[2] = 4; |
| 355 | swizzle_pipe[3] = 6; |
409 | swizzle_pipe[3] = 6; |
| 356 | swizzle_pipe[4] = 3; |
410 | swizzle_pipe[4] = 3; |
| - | 411 | swizzle_pipe[5] = 1; |
|
| 357 | swizzle_pipe[5] = 1; |
412 | swizzle_pipe[6] = 5; |
| 358 | swizzle_pipe[6] = 5; |
413 | } |
| - | 414 | break; |
|
| - | 415 | case 8: |
|
| - | 416 | if (force_no_swizzle) { |
|
| - | 417 | swizzle_pipe[0] = 0; |
|
| - | 418 | swizzle_pipe[1] = 1; |
|
| - | 419 | swizzle_pipe[2] = 2; |
|
| - | 420 | swizzle_pipe[3] = 3; |
|
| - | 421 | swizzle_pipe[4] = 4; |
|
| - | 422 | swizzle_pipe[5] = 5; |
|
| - | 423 | swizzle_pipe[6] = 6; |
|
| 359 | break; |
424 | swizzle_pipe[7] = 7; |
| 360 | case 8: |
425 | } else { |
| 361 | swizzle_pipe[0] = 0; |
426 | swizzle_pipe[0] = 0; |
| 362 | swizzle_pipe[1] = 2; |
427 | swizzle_pipe[1] = 2; |
| 363 | swizzle_pipe[2] = 4; |
428 | swizzle_pipe[2] = 4; |
| 364 | swizzle_pipe[3] = 6; |
429 | swizzle_pipe[3] = 6; |
| 365 | swizzle_pipe[4] = 3; |
430 | swizzle_pipe[4] = 3; |
| 366 | swizzle_pipe[5] = 1; |
431 | swizzle_pipe[5] = 1; |
| - | 432 | swizzle_pipe[6] = 7; |
|
| 367 | swizzle_pipe[6] = 7; |
433 | swizzle_pipe[7] = 5; |
| 368 | swizzle_pipe[7] = 5; |
434 | } |
| Line 369... | Line 435... | ||
| 369 | break; |
435 | break; |
| 370 | } |
436 | } |
| Line 383... | Line 449... | ||
| 383 | } |
449 | } |
| Line 384... | Line 450... | ||
| 384 | 450 | ||
| 385 | static void rv770_gpu_init(struct radeon_device *rdev) |
451 | static void rv770_gpu_init(struct radeon_device *rdev) |
| 386 | { |
452 | { |
| - | 453 | int i, j, num_qd_pipes; |
|
| 387 | int i, j, num_qd_pipes; |
454 | u32 ta_aux_cntl; |
| 388 | u32 sx_debug_1; |
455 | u32 sx_debug_1; |
| - | 456 | u32 smx_dc_ctl0; |
|
| 389 | u32 smx_dc_ctl0; |
457 | u32 db_debug3; |
| 390 | u32 num_gs_verts_per_thread; |
458 | u32 num_gs_verts_per_thread; |
| 391 | u32 vgt_gs_per_es; |
459 | u32 vgt_gs_per_es; |
| 392 | u32 gs_prim_buffer_depth = 0; |
460 | u32 gs_prim_buffer_depth = 0; |
| 393 | u32 sq_ms_fifo_sizes; |
461 | u32 sq_ms_fifo_sizes; |
| Line 513... | Line 581... | ||
| 513 | /* setup tiling, simd, pipe config */ |
581 | /* setup tiling, simd, pipe config */ |
| 514 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
582 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
| Line 515... | Line 583... | ||
| 515 | 583 | ||
| 516 | switch (rdev->config.rv770.max_tile_pipes) { |
584 | switch (rdev->config.rv770.max_tile_pipes) { |
| - | 585 | case 1: |
|
| 517 | case 1: |
586 | default: |
| 518 | gb_tiling_config |= PIPE_TILING(0); |
587 | gb_tiling_config |= PIPE_TILING(0); |
| 519 | break; |
588 | break; |
| 520 | case 2: |
589 | case 2: |
| 521 | gb_tiling_config |= PIPE_TILING(1); |
590 | gb_tiling_config |= PIPE_TILING(1); |
| Line 524... | Line 593... | ||
| 524 | gb_tiling_config |= PIPE_TILING(2); |
593 | gb_tiling_config |= PIPE_TILING(2); |
| 525 | break; |
594 | break; |
| 526 | case 8: |
595 | case 8: |
| 527 | gb_tiling_config |= PIPE_TILING(3); |
596 | gb_tiling_config |= PIPE_TILING(3); |
| 528 | break; |
597 | break; |
| 529 | default: |
- | |
| 530 | break; |
- | |
| 531 | } |
598 | } |
| - | 599 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
|
| Line 532... | Line 600... | ||
| 532 | 600 | ||
| 533 | if (rdev->family == CHIP_RV770) |
601 | if (rdev->family == CHIP_RV770) |
| 534 | gb_tiling_config |= BANK_TILING(1); |
602 | gb_tiling_config |= BANK_TILING(1); |
| 535 | else |
603 | else |
| - | 604 | gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
|
| Line 536... | Line 605... | ||
| 536 | gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
605 | rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); |
| - | 606 | ||
| Line 537... | Line 607... | ||
| 537 | 607 | gb_tiling_config |= GROUP_SIZE(0); |
|
| 538 | gb_tiling_config |= GROUP_SIZE(0); |
608 | rdev->config.rv770.tiling_group_size = 256; |
| 539 | 609 | ||
| 540 | if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { |
610 | if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { |
| Line 547... | Line 617... | ||
| 547 | SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
617 | SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
| 548 | } |
618 | } |
| Line 549... | Line 619... | ||
| 549 | 619 | ||
| Line 550... | Line 620... | ||
| 550 | gb_tiling_config |= BANK_SWAPS(1); |
620 | gb_tiling_config |= BANK_SWAPS(1); |
| 551 | 621 | ||
| 552 | backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes, |
622 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
| 553 | rdev->config.rv770.max_backends, |
- | |
| Line -... | Line 623... | ||
| - | 623 | cc_rb_backend_disable |= |
|
| 554 | (0xff << rdev->config.rv770.max_backends) & 0xff); |
624 | BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); |
| 555 | gb_tiling_config |= BACKEND_MAP(backend_map); |
625 | |
| 556 | 626 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
|
| 557 | cc_gc_shader_pipe_config = |
627 | cc_gc_shader_pipe_config |= |
| Line -... | Line 628... | ||
| - | 628 | INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); |
|
| - | 629 | cc_gc_shader_pipe_config |= |
|
| - | 630 | INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); |
|
| - | 631 | ||
| - | 632 | if (rdev->family == CHIP_RV740) |
|
| - | 633 | backend_map = 0x28; |
|
| - | 634 | else |
|
| - | 635 | backend_map = r700_get_tile_pipe_to_backend_map(rdev, |
|
| 558 | INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); |
636 | rdev->config.rv770.max_tile_pipes, |
| 559 | cc_gc_shader_pipe_config |= |
637 | (R7XX_MAX_BACKENDS - |
| - | 638 | r600_count_pipe_bits((cc_rb_backend_disable & |
|
| Line 560... | Line 639... | ||
| 560 | INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); |
639 | R7XX_MAX_BACKENDS_MASK) >> 16)), |
| 561 | 640 | (cc_rb_backend_disable >> 16)); |
|
| 562 | cc_rb_backend_disable = |
641 | gb_tiling_config |= BACKEND_MAP(backend_map); |
| Line 563... | Line 642... | ||
| 563 | BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); |
642 | |
| 564 | 643 | ||
| 565 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
- | |
| 566 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
- | |
| 567 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
644 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
| - | 645 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
|
| 568 | 646 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
|
| 569 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
647 | |
| 570 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
- | |
| 571 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
- | |
| Line 572... | Line 648... | ||
| 572 | 648 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
|
| 573 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
649 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
| 574 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
650 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
| 575 | WREG32(CGTS_TCC_DISABLE, 0); |
651 | |
| Line 576... | Line 652... | ||
| 576 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); |
652 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
| 577 | WREG32(CGTS_USER_TCC_DISABLE, 0); |
653 | WREG32(CGTS_TCC_DISABLE, 0); |
| 578 | 654 | ||
| Line 579... | Line 655... | ||
| 579 | num_qd_pipes = |
655 | num_qd_pipes = |
| Line -... | Line 656... | ||
| - | 656 | R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
|
| 580 | R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK); |
657 | WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); |
| 581 | WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); |
- | |
| 582 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
- | |
| 583 | - | ||
| Line 584... | Line 658... | ||
| 584 | /* set HW defaults for 3D engine */ |
658 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
| 585 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | |
659 | |
| 586 | ROQ_IB2_START(0x2b))); |
660 | /* set HW defaults for 3D engine */ |
| Line 587... | Line 661... | ||
| 587 | 661 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | |
|
| 588 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); |
662 | ROQ_IB2_START(0x2b))); |
| 589 | 663 | ||
| 590 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | |
664 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); |
| Line -... | Line 665... | ||
| - | 665 | ||
| 591 | SYNC_GRADIENT | |
666 | ta_aux_cntl = RREG32(TA_CNTL_AUX); |
| 592 | SYNC_WALKER | |
667 | WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); |
| 593 | SYNC_ALIGNER)); |
668 | |
| 594 | 669 | sx_debug_1 = RREG32(SX_DEBUG_1); |
|
| Line -... | Line 670... | ||
| - | 670 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
|
| - | 671 | WREG32(SX_DEBUG_1, sx_debug_1); |
|
| 595 | sx_debug_1 = RREG32(SX_DEBUG_1); |
672 | |
| - | 673 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
|
| - | 674 | smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); |
|
| 596 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
675 | smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); |
| - | 676 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
|
| - | 677 | ||
| - | 678 | if (rdev->family != CHIP_RV740) |
|
| - | 679 | WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | |
|
| - | 680 | GS_FLUSH_CTL(4) | |
|
| 597 | WREG32(SX_DEBUG_1, sx_debug_1); |
681 | ACK_FLUSH_CTL(3) | |
| - | 682 | SYNC_FLUSH_CTL)); |
|
| - | 683 | ||
| - | 684 | db_debug3 = RREG32(DB_DEBUG3); |
|
| - | 685 | db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); |
|
| 598 | 686 | switch (rdev->family) { |
|
| 599 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
687 | case CHIP_RV770: |
| 600 | smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); |
688 | case CHIP_RV740: |
| 601 | smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); |
689 | db_debug3 |= DB_CLK_OFF_DELAY(0x1f); |
| Line 635... | Line 723... | ||
| 635 | sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | |
723 | sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | |
| 636 | DONE_FIFO_HIWATER(0xe0) | |
724 | DONE_FIFO_HIWATER(0xe0) | |
| 637 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
725 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
| 638 | switch (rdev->family) { |
726 | switch (rdev->family) { |
| 639 | case CHIP_RV770: |
727 | case CHIP_RV770: |
| 640 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); |
- | |
| 641 | break; |
- | |
| 642 | case CHIP_RV730: |
728 | case CHIP_RV730: |
| 643 | case CHIP_RV710: |
729 | case CHIP_RV710: |
| - | 730 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); |
|
| - | 731 | break; |
|
| 644 | case CHIP_RV740: |
732 | case CHIP_RV740: |
| 645 | default: |
733 | default: |
| 646 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); |
734 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); |
| 647 | break; |
735 | break; |
| 648 | } |
736 | } |
| Line 811... | Line 899... | ||
| 811 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
899 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
| 812 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
900 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
| 813 | /* Setup GPU memory space */ |
901 | /* Setup GPU memory space */ |
| 814 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
902 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
| 815 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
903 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
| 816 | - | ||
| - | 904 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
|
| - | 905 | /* FIXME remove this once we support unmappable VRAM */ |
|
| 817 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) |
906 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { |
| 818 | rdev->mc.mc_vram_size = rdev->mc.aper_size; |
907 | rdev->mc.mc_vram_size = rdev->mc.aper_size; |
| 819 | - | ||
| 820 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
- | |
| 821 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
908 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
| 822 | - | ||
| 823 | if (rdev->flags & RADEON_IS_AGP) { |
- | |
| 824 | /* gtt_size is setup by radeon_agp_init */ |
- | |
| 825 | rdev->mc.gtt_location = rdev->mc.agp_base; |
- | |
| 826 | tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; |
- | |
| 827 | /* Try to put vram before or after AGP because we |
- | |
| 828 | * we want SYSTEM_APERTURE to cover both VRAM and |
- | |
| 829 | * AGP so that GPU can catch out of VRAM/AGP access |
- | |
| 830 | */ |
- | |
| 831 | if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { |
- | |
| 832 | /* Enough place before */ |
- | |
| 833 | rdev->mc.vram_location = rdev->mc.gtt_location - |
- | |
| 834 | rdev->mc.mc_vram_size; |
- | |
| 835 | } else if (tmp > rdev->mc.mc_vram_size) { |
- | |
| 836 | /* Enough place after */ |
- | |
| 837 | rdev->mc.vram_location = rdev->mc.gtt_location + |
- | |
| 838 | rdev->mc.gtt_size; |
- | |
| 839 | } else { |
- | |
| 840 | /* Try to setup VRAM then AGP might not |
- | |
| 841 | * not work on some card |
- | |
| 842 | */ |
- | |
| 843 | rdev->mc.vram_location = 0x00000000UL; |
- | |
| 844 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
- | |
| 845 | } |
909 | } |
| 846 | } else { |
- | |
| 847 | rdev->mc.vram_location = 0x00000000UL; |
- | |
| 848 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
910 | r600_vram_gtt_location(rdev, &rdev->mc); |
| 849 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
- | |
| 850 | } |
- | |
| 851 | rdev->mc.vram_start = rdev->mc.vram_location; |
- | |
| 852 | rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
- | |
| 853 | rdev->mc.gtt_start = rdev->mc.gtt_location; |
- | |
| 854 | rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
- | |
| 855 | /* FIXME: we should enforce default clock in case GPU is not in |
911 | /* FIXME: we should enforce default clock in case GPU is not in |
| 856 | * default setup |
912 | * default setup |
| 857 | */ |
913 | */ |
| 858 | a.full = rfixed_const(100); |
914 | a.full = rfixed_const(100); |
| 859 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
915 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
| 860 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
916 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
| 861 | return 0; |
917 | return 0; |
| 862 | } |
918 | } |
| - | 919 | ||
| 863 | int rv770_gpu_reset(struct radeon_device *rdev) |
920 | int rv770_gpu_reset(struct radeon_device *rdev) |
| 864 | { |
921 | { |
| 865 | /* FIXME: implement any rv770 specific bits */ |
922 | /* FIXME: implement any rv770 specific bits */ |
| 866 | return r600_gpu_reset(rdev); |
923 | return r600_gpu_reset(rdev); |
| 867 | } |
924 | } |
| Line 959... | Line 1016... | ||
| 959 | radeon_pm_init(rdev); |
1016 | radeon_pm_init(rdev); |
| 960 | /* Fence driver */ |
1017 | /* Fence driver */ |
| 961 | // r = radeon_fence_driver_init(rdev); |
1018 | // r = radeon_fence_driver_init(rdev); |
| 962 | // if (r) |
1019 | // if (r) |
| 963 | // return r; |
1020 | // return r; |
| - | 1021 | /* initialize AGP */ |
|
| 964 | if (rdev->flags & RADEON_IS_AGP) { |
1022 | if (rdev->flags & RADEON_IS_AGP) { |
| 965 | r = radeon_agp_init(rdev); |
1023 | r = radeon_agp_init(rdev); |
| 966 | if (r) |
1024 | if (r) |
| 967 | radeon_agp_disable(rdev); |
1025 | radeon_agp_disable(rdev); |
| 968 | } |
1026 | } |
| Line 992... | Line 1050... | ||
| 992 | rdev->accel_working = false; |
1050 | rdev->accel_working = false; |
| 993 | } |
1051 | } |
| 994 | if (rdev->accel_working) { |
1052 | if (rdev->accel_working) { |
| 995 | // r = radeon_ib_pool_init(rdev); |
1053 | // r = radeon_ib_pool_init(rdev); |
| 996 | // if (r) { |
1054 | // if (r) { |
| 997 | // DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); |
1055 | // dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 998 | // rdev->accel_working = false; |
1056 | // rdev->accel_working = false; |
| 999 | // } |
1057 | // } else { |
| 1000 | // r = r600_ib_test(rdev); |
1058 | // r = r600_ib_test(rdev); |
| 1001 | // if (r) { |
1059 | // if (r) { |
| 1002 | // DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
1060 | // dev_err(rdev->dev, "IB test failed (%d).\n", r); |
| 1003 | // rdev->accel_working = false; |
1061 | // rdev->accel_working = false; |
| 1004 | // } |
1062 | // } |
| - | 1063 | // } |
|
| 1005 | } |
1064 | } |
| 1006 | return 0; |
1065 | return 0; |
| 1007 | } |
1066 | } |