WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/rv770.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
//#include 
//#include 
#include "drmP.h"
#include "radeon.h"
#include "radeon_drm.h"
#include "rv770d.h"
#include "atom.h"
#include "avivod.h"
 
#define R700_PFP_UCODE_SIZE 848
#define R700_PM4_UCODE_SIZE 1360
 
static void rv770_gpu_init(struct radeon_device *rdev);
void rv770_fini(struct radeon_device *rdev);
 
 
/*
 * GART
 */
int rv770_pcie_gart_enable(struct radeon_device *rdev)
{
	u32 tmp;
	int r, i;
 
	if (rdev->gart.table.vram.robj == NULL) {
		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		return -EINVAL;
	}
	r = radeon_gart_table_vram_pin(rdev);
	if (r)
		return r;
	/* Setup L2 cache */
	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
				EFFECTIVE_L2_QUEUE_SIZE(7));
	WREG32(VM_L2_CNTL2, 0);
	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
	/* Setup TLB control */
	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
		SYSTEM_ACCESS_MODE_NOT_IN_SYS |
		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
		EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
			(u32)(rdev->dummy_page.addr >> 12));
	for (i = 1; i < 7; i++)
		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 
	r600_pcie_gart_tlb_flush(rdev);
	rdev->gart.ready = true;
	return 0;
}
 
void rv770_pcie_gart_disable(struct radeon_device *rdev)
{
	u32 tmp;
	int i, r;
 
	/* Disable all tables */
	for (i = 0; i < 7; i++)
		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 
	/* Setup L2 cache */
	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
				EFFECTIVE_L2_QUEUE_SIZE(7));
	WREG32(VM_L2_CNTL2, 0);
	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
	/* Setup TLB control */
	tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
	if (rdev->gart.table.vram.robj) {
		r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(rdev->gart.table.vram.robj);
			radeon_bo_unpin(rdev->gart.table.vram.robj);
			radeon_bo_unreserve(rdev->gart.table.vram.robj);
		}
	}
}
 
void rv770_pcie_gart_fini(struct radeon_device *rdev)
{
	rv770_pcie_gart_disable(rdev);
	radeon_gart_table_vram_free(rdev);
    radeon_gart_fini(rdev);
}
 
 
void rv770_agp_enable(struct radeon_device *rdev)
{
	u32 tmp;
	int i;
 
	/* Setup L2 cache */
	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
				EFFECTIVE_L2_QUEUE_SIZE(7));
	WREG32(VM_L2_CNTL2, 0);
	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
	/* Setup TLB control */
	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
		SYSTEM_ACCESS_MODE_NOT_IN_SYS |
		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
		EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
	for (i = 0; i < 7; i++)
		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
}
 
static void rv770_mc_program(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
	u32 tmp;
	int i, j;
 
	/* Initialize HDP */
	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
		WREG32((0x2c14 + j), 0x00000000);
		WREG32((0x2c18 + j), 0x00000000);
		WREG32((0x2c1c + j), 0x00000000);
		WREG32((0x2c20 + j), 0x00000000);
		WREG32((0x2c24 + j), 0x00000000);
	}
	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 
	rv515_mc_stop(rdev, &save);
	if (r600_mc_wait_for_idle(rdev)) {
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
	}
	/* Lockout access through VGA aperture*/
	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
	/* Update configuration */
	if (rdev->flags & RADEON_IS_AGP) {
		if (rdev->mc.vram_start < rdev->mc.gtt_start) {
			/* VRAM before AGP */
			WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
				rdev->mc.vram_start >> 12);
			WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
				rdev->mc.gtt_end >> 12);
		} else {
			/* VRAM after AGP */
			WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
				rdev->mc.gtt_start >> 12);
			WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
				rdev->mc.vram_end >> 12);
		}
	} else {
		WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
			rdev->mc.vram_start >> 12);
		WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
			rdev->mc.vram_end >> 12);
	}
	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
	WREG32(MC_VM_FB_LOCATION, tmp);
	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
	WREG32(HDP_NONSURFACE_INFO, (2 << 7));
	WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
	if (rdev->flags & RADEON_IS_AGP) {
		WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
		WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
	} else {
		WREG32(MC_VM_AGP_BASE, 0);
		WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
		WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
	}
	if (r600_mc_wait_for_idle(rdev)) {
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
	}
	rv515_mc_resume(rdev, &save);
	/* we need to own VRAM, so turn off the VGA renderer here
	 * to stop it overwriting our objects */
	rv515_vga_render_disable(rdev);
}
 
 
/*
 * CP.
 */
void r700_cp_stop(struct radeon_device *rdev)
{
	WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
}
 
#if 0
static int rv770_cp_load_microcode(struct radeon_device *rdev)
{
	const __be32 *fw_data;
	int i;
 
	if (!rdev->me_fw || !rdev->pfp_fw)
		return -EINVAL;
 
	r700_cp_stop(rdev);
	WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
 
	/* Reset cp */
	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
	RREG32(GRBM_SOFT_RESET);
	mdelay(15);
	WREG32(GRBM_SOFT_RESET, 0);
 
	fw_data = (const __be32 *)rdev->pfp_fw->data;
	WREG32(CP_PFP_UCODE_ADDR, 0);
	for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
		WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
	WREG32(CP_PFP_UCODE_ADDR, 0);
 
	fw_data = (const __be32 *)rdev->me_fw->data;
	WREG32(CP_ME_RAM_WADDR, 0);
	for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
		WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 
	WREG32(CP_PFP_UCODE_ADDR, 0);
	WREG32(CP_ME_RAM_WADDR, 0);
	WREG32(CP_ME_RAM_RADDR, 0);
	return 0;
}
 
#endif
 
/*
 * Core functions
 */
static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
						u32 num_backends,
						u32 backend_disable_mask)
{
	u32 backend_map = 0;
	u32 enabled_backends_mask;
	u32 enabled_backends_count;
	u32 cur_pipe;
	u32 swizzle_pipe[R7XX_MAX_PIPES];
	u32 cur_backend;
	u32 i;
 
	if (num_tile_pipes > R7XX_MAX_PIPES)
		num_tile_pipes = R7XX_MAX_PIPES;
	if (num_tile_pipes < 1)
		num_tile_pipes = 1;
	if (num_backends > R7XX_MAX_BACKENDS)
		num_backends = R7XX_MAX_BACKENDS;
	if (num_backends < 1)
		num_backends = 1;
 
	enabled_backends_mask = 0;
	enabled_backends_count = 0;
	for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
		if (((backend_disable_mask >> i) & 1) == 0) {
			enabled_backends_mask |= (1 << i);
			++enabled_backends_count;
		}
		if (enabled_backends_count == num_backends)
			break;
	}
 
	if (enabled_backends_count == 0) {
		enabled_backends_mask = 1;
		enabled_backends_count = 1;
	}
 
	if (enabled_backends_count != num_backends)
		num_backends = enabled_backends_count;
 
	memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
	switch (num_tile_pipes) {
	case 1:
		swizzle_pipe[0] = 0;
		break;
	case 2:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 1;
		break;
	case 3:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 2;
		swizzle_pipe[2] = 1;
		break;
	case 4:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 2;
		swizzle_pipe[2] = 3;
		swizzle_pipe[3] = 1;
		break;
	case 5:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 2;
		swizzle_pipe[2] = 4;
		swizzle_pipe[3] = 1;
		swizzle_pipe[4] = 3;
		break;
	case 6:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 2;
		swizzle_pipe[2] = 4;
		swizzle_pipe[3] = 5;
		swizzle_pipe[4] = 3;
		swizzle_pipe[5] = 1;
		break;
	case 7:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 2;
		swizzle_pipe[2] = 4;
		swizzle_pipe[3] = 6;
		swizzle_pipe[4] = 3;
		swizzle_pipe[5] = 1;
		swizzle_pipe[6] = 5;
		break;
	case 8:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 2;
		swizzle_pipe[2] = 4;
		swizzle_pipe[3] = 6;
		swizzle_pipe[4] = 3;
		swizzle_pipe[5] = 1;
		swizzle_pipe[6] = 7;
		swizzle_pipe[7] = 5;
		break;
	}
 
	cur_backend = 0;
	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
		while (((1 << cur_backend) & enabled_backends_mask) == 0)
			cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 
		backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 
		cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
	}
 
	return backend_map;
}
 
static void rv770_gpu_init(struct radeon_device *rdev)
{
	int i, j, num_qd_pipes;
	u32 sx_debug_1;
	u32 smx_dc_ctl0;
	u32 num_gs_verts_per_thread;
	u32 vgt_gs_per_es;
	u32 gs_prim_buffer_depth = 0;
	u32 sq_ms_fifo_sizes;
	u32 sq_config;
	u32 sq_thread_resource_mgmt;
	u32 hdp_host_path_cntl;
	u32 sq_dyn_gpr_size_simd_ab_0;
	u32 backend_map;
	u32 gb_tiling_config = 0;
	u32 cc_rb_backend_disable = 0;
	u32 cc_gc_shader_pipe_config = 0;
	u32 mc_arb_ramcfg;
	u32 db_debug4;
 
	/* setup chip specs */
	switch (rdev->family) {
	case CHIP_RV770:
		rdev->config.rv770.max_pipes = 4;
		rdev->config.rv770.max_tile_pipes = 8;
		rdev->config.rv770.max_simds = 10;
		rdev->config.rv770.max_backends = 4;
		rdev->config.rv770.max_gprs = 256;
		rdev->config.rv770.max_threads = 248;
		rdev->config.rv770.max_stack_entries = 512;
		rdev->config.rv770.max_hw_contexts = 8;
		rdev->config.rv770.max_gs_threads = 16 * 2;
		rdev->config.rv770.sx_max_export_size = 128;
		rdev->config.rv770.sx_max_export_pos_size = 16;
		rdev->config.rv770.sx_max_export_smx_size = 112;
		rdev->config.rv770.sq_num_cf_insts = 2;
 
		rdev->config.rv770.sx_num_of_sets = 7;
		rdev->config.rv770.sc_prim_fifo_size = 0xF9;
		rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
		rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
		break;
	case CHIP_RV730:
		rdev->config.rv770.max_pipes = 2;
		rdev->config.rv770.max_tile_pipes = 4;
		rdev->config.rv770.max_simds = 8;
		rdev->config.rv770.max_backends = 2;
		rdev->config.rv770.max_gprs = 128;
		rdev->config.rv770.max_threads = 248;
		rdev->config.rv770.max_stack_entries = 256;
		rdev->config.rv770.max_hw_contexts = 8;
		rdev->config.rv770.max_gs_threads = 16 * 2;
		rdev->config.rv770.sx_max_export_size = 256;
		rdev->config.rv770.sx_max_export_pos_size = 32;
		rdev->config.rv770.sx_max_export_smx_size = 224;
		rdev->config.rv770.sq_num_cf_insts = 2;
 
		rdev->config.rv770.sx_num_of_sets = 7;
		rdev->config.rv770.sc_prim_fifo_size = 0xf9;
		rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
		rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
		if (rdev->config.rv770.sx_max_export_pos_size > 16) {
			rdev->config.rv770.sx_max_export_pos_size -= 16;
			rdev->config.rv770.sx_max_export_smx_size += 16;
		}
		break;
	case CHIP_RV710:
		rdev->config.rv770.max_pipes = 2;
		rdev->config.rv770.max_tile_pipes = 2;
		rdev->config.rv770.max_simds = 2;
		rdev->config.rv770.max_backends = 1;
		rdev->config.rv770.max_gprs = 256;
		rdev->config.rv770.max_threads = 192;
		rdev->config.rv770.max_stack_entries = 256;
		rdev->config.rv770.max_hw_contexts = 4;
		rdev->config.rv770.max_gs_threads = 8 * 2;
		rdev->config.rv770.sx_max_export_size = 128;
		rdev->config.rv770.sx_max_export_pos_size = 16;
		rdev->config.rv770.sx_max_export_smx_size = 112;
		rdev->config.rv770.sq_num_cf_insts = 1;
 
		rdev->config.rv770.sx_num_of_sets = 7;
		rdev->config.rv770.sc_prim_fifo_size = 0x40;
		rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
		rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
		break;
	case CHIP_RV740:
		rdev->config.rv770.max_pipes = 4;
		rdev->config.rv770.max_tile_pipes = 4;
		rdev->config.rv770.max_simds = 8;
		rdev->config.rv770.max_backends = 4;
		rdev->config.rv770.max_gprs = 256;
		rdev->config.rv770.max_threads = 248;
		rdev->config.rv770.max_stack_entries = 512;
		rdev->config.rv770.max_hw_contexts = 8;
		rdev->config.rv770.max_gs_threads = 16 * 2;
		rdev->config.rv770.sx_max_export_size = 256;
		rdev->config.rv770.sx_max_export_pos_size = 32;
		rdev->config.rv770.sx_max_export_smx_size = 224;
		rdev->config.rv770.sq_num_cf_insts = 2;
 
		rdev->config.rv770.sx_num_of_sets = 7;
		rdev->config.rv770.sc_prim_fifo_size = 0x100;
		rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
		rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 
		if (rdev->config.rv770.sx_max_export_pos_size > 16) {
			rdev->config.rv770.sx_max_export_pos_size -= 16;
			rdev->config.rv770.sx_max_export_smx_size += 16;
		}
		break;
	default:
		break;
	}
 
	/* Initialize HDP */
	j = 0;
	for (i = 0; i < 32; i++) {
		WREG32((0x2c14 + j), 0x00000000);
		WREG32((0x2c18 + j), 0x00000000);
		WREG32((0x2c1c + j), 0x00000000);
		WREG32((0x2c20 + j), 0x00000000);
		WREG32((0x2c24 + j), 0x00000000);
		j += 0x18;
	}
 
	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 
	/* setup tiling, simd, pipe config */
	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 
	switch (rdev->config.rv770.max_tile_pipes) {
	case 1:
		gb_tiling_config |= PIPE_TILING(0);
		break;
	case 2:
		gb_tiling_config |= PIPE_TILING(1);
		break;
	case 4:
		gb_tiling_config |= PIPE_TILING(2);
		break;
	case 8:
		gb_tiling_config |= PIPE_TILING(3);
		break;
	default:
		break;
	}
 
	if (rdev->family == CHIP_RV770)
		gb_tiling_config |= BANK_TILING(1);
	else
		gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 
	gb_tiling_config |= GROUP_SIZE(0);
 
	if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
		gb_tiling_config |= ROW_TILING(3);
		gb_tiling_config |= SAMPLE_SPLIT(3);
	} else {
		gb_tiling_config |=
			ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
		gb_tiling_config |=
			SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
	}
 
	gb_tiling_config |= BANK_SWAPS(1);
 
	backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
							rdev->config.rv770.max_backends,
							(0xff << rdev->config.rv770.max_backends) & 0xff);
	gb_tiling_config |= BACKEND_MAP(backend_map);
 
	cc_gc_shader_pipe_config =
		INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
	cc_gc_shader_pipe_config |=
		INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 
	cc_rb_backend_disable =
		BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 
	WREG32(GB_TILING_CONFIG, gb_tiling_config);
	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 
	WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
	WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
	WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 
	WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
	WREG32(CGTS_SYS_TCC_DISABLE, 0);
	WREG32(CGTS_TCC_DISABLE, 0);
	WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
	WREG32(CGTS_USER_TCC_DISABLE, 0);
 
	num_qd_pipes =
		R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
	WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 
	/* set HW defaults for 3D engine */
	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
						ROQ_IB2_START(0x2b)));
 
	WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 
	WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
					SYNC_GRADIENT |
					SYNC_WALKER |
					SYNC_ALIGNER));
 
	sx_debug_1 = RREG32(SX_DEBUG_1);
	sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
	WREG32(SX_DEBUG_1, sx_debug_1);
 
	smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
	smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
	smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
	WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 
	WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
					  GS_FLUSH_CTL(4) |
					  ACK_FLUSH_CTL(3) |
					  SYNC_FLUSH_CTL));
 
	if (rdev->family == CHIP_RV770)
		WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
	else {
		db_debug4 = RREG32(DB_DEBUG4);
		db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
		WREG32(DB_DEBUG4, db_debug4);
	}
 
	WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
						   POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
						   SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 
	WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
						 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
						 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 
	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 
	WREG32(VGT_NUM_INSTANCES, 1);
 
	WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 
	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 
	WREG32(CP_PERFMON_CNTL, 0);
 
	sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
			    DONE_FIFO_HIWATER(0xe0) |
			    ALU_UPDATE_FIFO_HIWATER(0x8));
	switch (rdev->family) {
	case CHIP_RV770:
		sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
		break;
	case CHIP_RV730:
	case CHIP_RV710:
	case CHIP_RV740:
	default:
		sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
		break;
	}
	WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 
	/* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
	 * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
	 */
	sq_config = RREG32(SQ_CONFIG);
	sq_config &= ~(PS_PRIO(3) |
		       VS_PRIO(3) |
		       GS_PRIO(3) |
		       ES_PRIO(3));
	sq_config |= (DX9_CONSTS |
		      VC_ENABLE |
		      EXPORT_SRC_C |
		      PS_PRIO(0) |
		      VS_PRIO(1) |
		      GS_PRIO(2) |
		      ES_PRIO(3));
	if (rdev->family == CHIP_RV710)
		/* no vertex cache */
		sq_config &= ~VC_ENABLE;
 
	WREG32(SQ_CONFIG, sq_config);
 
	WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
					 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
					 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 
	WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
					 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 
	sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
				   NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
				   NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
	if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
		sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
	else
		sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
	WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 
	WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
						     NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 
	WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
						     NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 
	sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
				     SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
				     SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
				     SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 
	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 
	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
					  FORCE_EOV_MAX_REZ_CNT(255)));
 
	if (rdev->family == CHIP_RV710)
		WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
						AUTO_INVLD_EN(ES_AND_GS_AUTO)));
	else
		WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
						AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 
	switch (rdev->family) {
	case CHIP_RV770:
	case CHIP_RV730:
	case CHIP_RV740:
		gs_prim_buffer_depth = 384;
		break;
	case CHIP_RV710:
		gs_prim_buffer_depth = 128;
		break;
	default:
		break;
	}
 
	num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
	vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
	/* Max value for this is 256 */
	if (vgt_gs_per_es > 256)
		vgt_gs_per_es = 256;
 
	WREG32(VGT_ES_PER_GS, 128);
	WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
	WREG32(VGT_GS_PER_VS, 2);
 
	/* more default values. 2D/3D driver should adjust as needed */
	WREG32(VGT_GS_VERTEX_REUSE, 16);
	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
	WREG32(VGT_STRMOUT_EN, 0);
	WREG32(SX_MISC, 0);
	WREG32(PA_SC_MODE_CNTL, 0);
	WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
	WREG32(PA_SC_AA_CONFIG, 0);
	WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
	WREG32(PA_SC_LINE_STIPPLE, 0);
	WREG32(SPI_INPUT_Z, 0);
	WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
	WREG32(CB_COLOR7_FRAG, 0);
 
	/* clear render buffer base addresses */
	WREG32(CB_COLOR0_BASE, 0);
	WREG32(CB_COLOR1_BASE, 0);
	WREG32(CB_COLOR2_BASE, 0);
	WREG32(CB_COLOR3_BASE, 0);
	WREG32(CB_COLOR4_BASE, 0);
	WREG32(CB_COLOR5_BASE, 0);
	WREG32(CB_COLOR6_BASE, 0);
	WREG32(CB_COLOR7_BASE, 0);
 
	WREG32(TCP_CNTL, 0);
 
	hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
	WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 
	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 
	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
					  NUM_CLIP_SEQ(3)));
 
}
 
int rv770_mc_init(struct radeon_device *rdev)
{
	fixed20_12 a;
	u32 tmp;
	int chansize, numchan;
 
	/* Get VRAM informations */
	rdev->mc.vram_is_ddr = true;
	tmp = RREG32(MC_ARB_RAMCFG);
	if (tmp & CHANSIZE_OVERRIDE) {
		chansize = 16;
	} else if (tmp & CHANSIZE_MASK) {
		chansize = 64;
	} else {
		chansize = 32;
	}
	tmp = RREG32(MC_SHARED_CHMAP);
	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
	case 0:
	default:
		numchan = 1;
		break;
	case 1:
		numchan = 2;
		break;
	case 2:
		numchan = 4;
		break;
	case 3:
		numchan = 8;
		break;
	}
	rdev->mc.vram_width = numchan * chansize;
	/* Could aper size report 0 ? */
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
	/* Setup GPU memory space */
	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 
	if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
		rdev->mc.mc_vram_size = rdev->mc.aper_size;
 
	if (rdev->mc.real_vram_size > rdev->mc.aper_size)
		rdev->mc.real_vram_size = rdev->mc.aper_size;
 
	if (rdev->flags & RADEON_IS_AGP) {
		/* gtt_size is setup by radeon_agp_init */
		rdev->mc.gtt_location = rdev->mc.agp_base;
		tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
		/* Try to put vram before or after AGP because we
		 * we want SYSTEM_APERTURE to cover both VRAM and
		 * AGP so that GPU can catch out of VRAM/AGP access
		 */
		if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
			/* Enough place before */
			rdev->mc.vram_location = rdev->mc.gtt_location -
							rdev->mc.mc_vram_size;
		} else if (tmp > rdev->mc.mc_vram_size) {
			/* Enough place after */
			rdev->mc.vram_location = rdev->mc.gtt_location +
							rdev->mc.gtt_size;
		} else {
			/* Try to setup VRAM then AGP might not
			 * not work on some card
			 */
			rdev->mc.vram_location = 0x00000000UL;
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
		}
	} else {
		rdev->mc.vram_location = 0x00000000UL;
		rdev->mc.gtt_location = rdev->mc.mc_vram_size;
		rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
	}
	rdev->mc.vram_start = rdev->mc.vram_location;
	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
	rdev->mc.gtt_start = rdev->mc.gtt_location;
	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
	/* FIXME: we should enforce default clock in case GPU is not in
	 * default setup
	 */
	a.full = rfixed_const(100);
	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
	return 0;
}
int rv770_gpu_reset(struct radeon_device *rdev)
{
	/* FIXME: implement any rv770 specific bits */
	return r600_gpu_reset(rdev);
}
 
static int rv770_startup(struct radeon_device *rdev)
{
	int r;
 
	rv770_mc_program(rdev);
	if (rdev->flags & RADEON_IS_AGP) {
		rv770_agp_enable(rdev);
	} else {
		r = rv770_pcie_gart_enable(rdev);
		if (r)
			return r;
	}
	rv770_gpu_init(rdev);
 
 
//  r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
//                 &rdev->r600_blit.shader_gpu_addr);
//   if (r) {
//       DRM_ERROR("failed to pin blit object %d\n", r);
//       return r;
//   }
 
//   r = radeon_ring_init(rdev, rdev->cp.ring_size);
//   if (r)
//       return r;
//   r = rv770_cp_load_microcode(rdev);
//   if (r)
//       return r;
//   r = r600_cp_resume(rdev);
//   if (r)
//       return r;
	/* write back buffer are not vital so don't worry about failure */
//   r600_wb_enable(rdev);
	return 0;
}
 
 
/* Plan is to move initialization in that function and use
 * helper function so that radeon_device_init pretty much
 * do nothing more than calling asic specific function. This
 * should also allow to remove a bunch of callback function
 * like vram_info.
 */
int rv770_init(struct radeon_device *rdev)
{
	int r;
 
	r = radeon_dummy_page_init(rdev);
	if (r)
		return r;
	/* This don't do much */
	r = radeon_gem_init(rdev);
	if (r)
		return r;
	/* Read BIOS */
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	/* Must be an ATOMBIOS */
	if (!rdev->is_atom_bios) {
		dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
		return -EINVAL;
	}
	r = radeon_atombios_init(rdev);
	if (r)
		return r;
	/* Post card if necessary */
	if (!r600_card_posted(rdev)) {
		if (!rdev->bios) {
			dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
			return -EINVAL;
		}
		DRM_INFO("GPU not posted. posting now...\n");
		atom_asic_init(rdev->mode_info.atom_context);
	}
	/* Initialize scratch registers */
	r600_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	r = radeon_clocks_init(rdev);
	if (r)
		return r;
	/* Initialize power management */
	radeon_pm_init(rdev);
	/* Fence driver */
//   r = radeon_fence_driver_init(rdev);
//   if (r)
//       return r;
	if (rdev->flags & RADEON_IS_AGP) {
		r = radeon_agp_init(rdev);
		if (r)
			radeon_agp_disable(rdev);
	}
	r = rv770_mc_init(rdev);
	if (r)
		return r;
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
 
//   if (!rdev->me_fw || !rdev->pfp_fw) {
//       r = r600_cp_init_microcode(rdev);
//       if (r) {
//           DRM_ERROR("Failed to load firmware!\n");
//           return r;
//       }
//   }
 
	r = r600_pcie_gart_init(rdev);
	if (r)
		return r;
 
	rdev->accel_working = true;
//   r = r600_blit_init(rdev);
//   if (r) {
//       DRM_ERROR("radeon: failled blitter (%d).\n", r);
//       rdev->accel_working = false;
//   }
 
	r = rv770_startup(rdev);
	if (r) {
//       rv770_suspend(rdev);
//       r600_wb_fini(rdev);
//       radeon_ring_fini(rdev);
		rv770_pcie_gart_fini(rdev);
        rdev->accel_working = false;
	}
	if (rdev->accel_working) {
//       r = radeon_ib_pool_init(rdev);
//       if (r) {
//           DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
//           rdev->accel_working = false;
//       }
//       r = r600_ib_test(rdev);
//       if (r) {
//           DRM_ERROR("radeon: failled testing IB (%d).\n", r);
//           rdev->accel_working = false;
//       }
	}
	return 0;
}

Rev 1403	Rev 1404
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	//#include	28	//#include
29	//#include	29	//#include
30	#include "drmP.h"	30	#include "drmP.h"
31	#include "radeon.h"	31	#include "radeon.h"
32	#include "radeon_drm.h"	32	#include "radeon_drm.h"
33	#include "rv770d.h"	33	#include "rv770d.h"
34	#include "atom.h"	34	#include "atom.h"
35	#include "avivod.h"	35	#include "avivod.h"
36		36
37	#define R700_PFP_UCODE_SIZE 848	37	#define R700_PFP_UCODE_SIZE 848
38	#define R700_PM4_UCODE_SIZE 1360	38	#define R700_PM4_UCODE_SIZE 1360
39		39
40	static void rv770_gpu_init(struct radeon_device *rdev);	40	static void rv770_gpu_init(struct radeon_device *rdev);
41	void rv770_fini(struct radeon_device *rdev);	41	void rv770_fini(struct radeon_device *rdev);
42		42
43		43
44	/*	44	/*
45	* GART	45	* GART
46	*/	46	*/
47	int rv770_pcie_gart_enable(struct radeon_device *rdev)	47	int rv770_pcie_gart_enable(struct radeon_device *rdev)
48	{	48	{
49	u32 tmp;	49	u32 tmp;
50	int r, i;	50	int r, i;
51		51
52	if (rdev->gart.table.vram.robj == NULL) {	52	if (rdev->gart.table.vram.robj == NULL) {
53	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");	53	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
54	return -EINVAL;	54	return -EINVAL;
55	}	55	}
56	r = radeon_gart_table_vram_pin(rdev);	56	r = radeon_gart_table_vram_pin(rdev);
57	if (r)	57	if (r)
58	return r;	58	return r;
59	/* Setup L2 cache */	59	/* Setup L2 cache */
60	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|	60	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|
61	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|	61	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|
62	EFFECTIVE_L2_QUEUE_SIZE(7));	62	EFFECTIVE_L2_QUEUE_SIZE(7));
63	WREG32(VM_L2_CNTL2, 0);	63	WREG32(VM_L2_CNTL2, 0);
64	WREG32(VM_L2_CNTL3, BANK_SELECT(0) \| CACHE_UPDATE_MODE(2));	64	WREG32(VM_L2_CNTL3, BANK_SELECT(0) \| CACHE_UPDATE_MODE(2));
65	/* Setup TLB control */	65	/* Setup TLB control */
66	tmp = ENABLE_L1_TLB \| ENABLE_L1_FRAGMENT_PROCESSING \|	66	tmp = ENABLE_L1_TLB \| ENABLE_L1_FRAGMENT_PROCESSING \|
67	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|	67	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|
68	SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU \|	68	SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU \|
69	EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5);	69	EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5);
70	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);	70	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
71	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);	71	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
72	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);	72	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
73	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);	73	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
74	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);	74	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
75	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);	75	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
76	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);	76	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
77	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);	77	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
78	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);	78	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
79	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);	79	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
80	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \|	80	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \|
81	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);	81	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
82	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,	82	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
83	(u32)(rdev->dummy_page.addr >> 12));	83	(u32)(rdev->dummy_page.addr >> 12));
84	for (i = 1; i < 7; i++)	84	for (i = 1; i < 7; i++)
85	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);	85	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
86		86
87	r600_pcie_gart_tlb_flush(rdev);	87	r600_pcie_gart_tlb_flush(rdev);
88	rdev->gart.ready = true;	88	rdev->gart.ready = true;
89	return 0;	89	return 0;
90	}	90	}
91		91
92	void rv770_pcie_gart_disable(struct radeon_device *rdev)	92	void rv770_pcie_gart_disable(struct radeon_device *rdev)
93	{	93	{
94	u32 tmp;	94	u32 tmp;
95	int i, r;	95	int i, r;
96		96
97	/* Disable all tables */	97	/* Disable all tables */
98	for (i = 0; i < 7; i++)	98	for (i = 0; i < 7; i++)
99	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);	99	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
100		100
101	/* Setup L2 cache */	101	/* Setup L2 cache */
102	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING \|	102	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING \|
103	EFFECTIVE_L2_QUEUE_SIZE(7));	103	EFFECTIVE_L2_QUEUE_SIZE(7));
104	WREG32(VM_L2_CNTL2, 0);	104	WREG32(VM_L2_CNTL2, 0);
105	WREG32(VM_L2_CNTL3, BANK_SELECT(0) \| CACHE_UPDATE_MODE(2));	105	WREG32(VM_L2_CNTL3, BANK_SELECT(0) \| CACHE_UPDATE_MODE(2));
106	/* Setup TLB control */	106	/* Setup TLB control */
107	tmp = EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5);	107	tmp = EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5);
108	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);	108	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
109	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);	109	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
110	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);	110	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
111	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);	111	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
112	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);	112	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
113	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);	113	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
114	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);	114	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
115	if (rdev->gart.table.vram.robj) {	115	if (rdev->gart.table.vram.robj) {
-		116	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-		117	if (likely(r == 0)) {
116	// radeon_object_kunmap(rdev->gart.table.vram.robj);	118	radeon_bo_kunmap(rdev->gart.table.vram.robj);
117	// radeon_object_unpin(rdev->gart.table.vram.robj);	119	radeon_bo_unpin(rdev->gart.table.vram.robj);
-		120	radeon_bo_unreserve(rdev->gart.table.vram.robj);
-		121	}
118	}	122	}
119	}	123	}
120		124
121	void rv770_pcie_gart_fini(struct radeon_device *rdev)	125	void rv770_pcie_gart_fini(struct radeon_device *rdev)
122	{	126	{
123	rv770_pcie_gart_disable(rdev);	127	rv770_pcie_gart_disable(rdev);
124	// radeon_gart_table_vram_free(rdev);	128	radeon_gart_table_vram_free(rdev);
125	radeon_gart_fini(rdev);	129	radeon_gart_fini(rdev);
126	}	130	}
127		131
128		132
129	void rv770_agp_enable(struct radeon_device *rdev)	133	void rv770_agp_enable(struct radeon_device *rdev)
130	{	134	{
131	u32 tmp;	135	u32 tmp;
132	int i;	136	int i;
133		137
134	/* Setup L2 cache */	138	/* Setup L2 cache */
135	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|	139	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|
136	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|	140	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|
137	EFFECTIVE_L2_QUEUE_SIZE(7));	141	EFFECTIVE_L2_QUEUE_SIZE(7));
138	WREG32(VM_L2_CNTL2, 0);	142	WREG32(VM_L2_CNTL2, 0);
139	WREG32(VM_L2_CNTL3, BANK_SELECT(0) \| CACHE_UPDATE_MODE(2));	143	WREG32(VM_L2_CNTL3, BANK_SELECT(0) \| CACHE_UPDATE_MODE(2));
140	/* Setup TLB control */	144	/* Setup TLB control */
141	tmp = ENABLE_L1_TLB \| ENABLE_L1_FRAGMENT_PROCESSING \|	145	tmp = ENABLE_L1_TLB \| ENABLE_L1_FRAGMENT_PROCESSING \|
142	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|	146	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|
143	SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU \|	147	SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU \|
144	EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5);	148	EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5);
145	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);	149	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
146	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);	150	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
147	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);	151	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
148	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);	152	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
149	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);	153	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
150	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);	154	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
151	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);	155	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
152	for (i = 0; i < 7; i++)	156	for (i = 0; i < 7; i++)
153	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);	157	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
154	}	158	}
155		159
156	static void rv770_mc_program(struct radeon_device *rdev)	160	static void rv770_mc_program(struct radeon_device *rdev)
157	{	161	{
158	struct rv515_mc_save save;	162	struct rv515_mc_save save;
159	u32 tmp;	163	u32 tmp;
160	int i, j;	164	int i, j;
161		165
162	/* Initialize HDP */	166	/* Initialize HDP */
163	for (i = 0, j = 0; i < 32; i++, j += 0x18) {	167	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
164	WREG32((0x2c14 + j), 0x00000000);	168	WREG32((0x2c14 + j), 0x00000000);
165	WREG32((0x2c18 + j), 0x00000000);	169	WREG32((0x2c18 + j), 0x00000000);
166	WREG32((0x2c1c + j), 0x00000000);	170	WREG32((0x2c1c + j), 0x00000000);
167	WREG32((0x2c20 + j), 0x00000000);	171	WREG32((0x2c20 + j), 0x00000000);
168	WREG32((0x2c24 + j), 0x00000000);	172	WREG32((0x2c24 + j), 0x00000000);
169	}	173	}
170	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);	174	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
171		175
172	rv515_mc_stop(rdev, &save);	176	rv515_mc_stop(rdev, &save);
173	if (r600_mc_wait_for_idle(rdev)) {	177	if (r600_mc_wait_for_idle(rdev)) {
174	dev_warn(rdev->dev, "Wait for MC idle timedout !\n");	178	dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
175	}	179	}
176	/* Lockout access through VGA aperture*/	180	/* Lockout access through VGA aperture*/
177	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);	181	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
178	/* Update configuration */	182	/* Update configuration */
179	if (rdev->flags & RADEON_IS_AGP) {	183	if (rdev->flags & RADEON_IS_AGP) {
180	if (rdev->mc.vram_start < rdev->mc.gtt_start) {	184	if (rdev->mc.vram_start < rdev->mc.gtt_start) {
181	/* VRAM before AGP */	185	/* VRAM before AGP */
182	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,	186	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
183	rdev->mc.vram_start >> 12);	187	rdev->mc.vram_start >> 12);
184	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,	188	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
185	rdev->mc.gtt_end >> 12);	189	rdev->mc.gtt_end >> 12);
186	} else {	190	} else {
187	/* VRAM after AGP */	191	/* VRAM after AGP */
188	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,	192	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
189	rdev->mc.gtt_start >> 12);	193	rdev->mc.gtt_start >> 12);
190	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,	194	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
191	rdev->mc.vram_end >> 12);	195	rdev->mc.vram_end >> 12);
192	}	196	}
193	} else {	197	} else {
194	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,	198	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
195	rdev->mc.vram_start >> 12);	199	rdev->mc.vram_start >> 12);
196	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,	200	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
197	rdev->mc.vram_end >> 12);	201	rdev->mc.vram_end >> 12);
198	}	202	}
199	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);	203	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
200	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;	204	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
201	tmp \|= ((rdev->mc.vram_start >> 24) & 0xFFFF);	205	tmp \|= ((rdev->mc.vram_start >> 24) & 0xFFFF);
202	WREG32(MC_VM_FB_LOCATION, tmp);	206	WREG32(MC_VM_FB_LOCATION, tmp);
203	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));	207	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
204	WREG32(HDP_NONSURFACE_INFO, (2 << 7));	208	WREG32(HDP_NONSURFACE_INFO, (2 << 7));
205	WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) \| 0x3FF);	209	WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) \| 0x3FF);
206	if (rdev->flags & RADEON_IS_AGP) {	210	if (rdev->flags & RADEON_IS_AGP) {
207	WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);	211	WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
208	WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);	212	WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
209	WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);	213	WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
210	} else {	214	} else {
211	WREG32(MC_VM_AGP_BASE, 0);	215	WREG32(MC_VM_AGP_BASE, 0);
212	WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);	216	WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
213	WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);	217	WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
214	}	218	}
215	if (r600_mc_wait_for_idle(rdev)) {	219	if (r600_mc_wait_for_idle(rdev)) {
216	dev_warn(rdev->dev, "Wait for MC idle timedout !\n");	220	dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
217	}	221	}
218	rv515_mc_resume(rdev, &save);	222	rv515_mc_resume(rdev, &save);
219	/* we need to own VRAM, so turn off the VGA renderer here	223	/* we need to own VRAM, so turn off the VGA renderer here
220	* to stop it overwriting our objects */	224	* to stop it overwriting our objects */
221	rv515_vga_render_disable(rdev);	225	rv515_vga_render_disable(rdev);
222	}	226	}
223		227
224		228
225	/*	229	/*
226	* CP.	230	* CP.
227	*/	231	*/
228	void r700_cp_stop(struct radeon_device *rdev)	232	void r700_cp_stop(struct radeon_device *rdev)
229	{	233	{
230	WREG32(CP_ME_CNTL, (CP_ME_HALT \| CP_PFP_HALT));	234	WREG32(CP_ME_CNTL, (CP_ME_HALT \| CP_PFP_HALT));
231	}	235	}
232		236
233	#if 0	237	#if 0
234	static int rv770_cp_load_microcode(struct radeon_device *rdev)	238	static int rv770_cp_load_microcode(struct radeon_device *rdev)
235	{	239	{
236	const __be32 *fw_data;	240	const __be32 *fw_data;
237	int i;	241	int i;
238		242
239	if (!rdev->me_fw \|\| !rdev->pfp_fw)	243	if (!rdev->me_fw \|\| !rdev->pfp_fw)
240	return -EINVAL;	244	return -EINVAL;
241		245
242	r700_cp_stop(rdev);	246	r700_cp_stop(rdev);
243	WREG32(CP_RB_CNTL, RB_NO_UPDATE \| (15 << 8) \| (3 << 0));	247	WREG32(CP_RB_CNTL, RB_NO_UPDATE \| (15 << 8) \| (3 << 0));
244		248
245	/* Reset cp */	249	/* Reset cp */
246	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);	250	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
247	RREG32(GRBM_SOFT_RESET);	251	RREG32(GRBM_SOFT_RESET);
248	mdelay(15);	252	mdelay(15);
249	WREG32(GRBM_SOFT_RESET, 0);	253	WREG32(GRBM_SOFT_RESET, 0);
250		254
251	fw_data = (const __be32 *)rdev->pfp_fw->data;	255	fw_data = (const __be32 *)rdev->pfp_fw->data;
252	WREG32(CP_PFP_UCODE_ADDR, 0);	256	WREG32(CP_PFP_UCODE_ADDR, 0);
253	for (i = 0; i < R700_PFP_UCODE_SIZE; i++)	257	for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
254	WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));	258	WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
255	WREG32(CP_PFP_UCODE_ADDR, 0);	259	WREG32(CP_PFP_UCODE_ADDR, 0);
256		260
257	fw_data = (const __be32 *)rdev->me_fw->data;	261	fw_data = (const __be32 *)rdev->me_fw->data;
258	WREG32(CP_ME_RAM_WADDR, 0);	262	WREG32(CP_ME_RAM_WADDR, 0);
259	for (i = 0; i < R700_PM4_UCODE_SIZE; i++)	263	for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
260	WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));	264	WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
261		265
262	WREG32(CP_PFP_UCODE_ADDR, 0);	266	WREG32(CP_PFP_UCODE_ADDR, 0);
263	WREG32(CP_ME_RAM_WADDR, 0);	267	WREG32(CP_ME_RAM_WADDR, 0);
264	WREG32(CP_ME_RAM_RADDR, 0);	268	WREG32(CP_ME_RAM_RADDR, 0);
265	return 0;	269	return 0;
266	}	270	}
267		271
268	#endif	272	#endif
269		273
270	/*	274	/*
271	* Core functions	275	* Core functions
272	*/	276	*/
273	static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,	277	static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
274	u32 num_backends,	278	u32 num_backends,
275	u32 backend_disable_mask)	279	u32 backend_disable_mask)
276	{	280	{
277	u32 backend_map = 0;	281	u32 backend_map = 0;
278	u32 enabled_backends_mask;	282	u32 enabled_backends_mask;
279	u32 enabled_backends_count;	283	u32 enabled_backends_count;
280	u32 cur_pipe;	284	u32 cur_pipe;
281	u32 swizzle_pipe[R7XX_MAX_PIPES];	285	u32 swizzle_pipe[R7XX_MAX_PIPES];
282	u32 cur_backend;	286	u32 cur_backend;
283	u32 i;	287	u32 i;
284		288
285	if (num_tile_pipes > R7XX_MAX_PIPES)	289	if (num_tile_pipes > R7XX_MAX_PIPES)
286	num_tile_pipes = R7XX_MAX_PIPES;	290	num_tile_pipes = R7XX_MAX_PIPES;
287	if (num_tile_pipes < 1)	291	if (num_tile_pipes < 1)
288	num_tile_pipes = 1;	292	num_tile_pipes = 1;
289	if (num_backends > R7XX_MAX_BACKENDS)	293	if (num_backends > R7XX_MAX_BACKENDS)
290	num_backends = R7XX_MAX_BACKENDS;	294	num_backends = R7XX_MAX_BACKENDS;
291	if (num_backends < 1)	295	if (num_backends < 1)
292	num_backends = 1;	296	num_backends = 1;
293		297
294	enabled_backends_mask = 0;	298	enabled_backends_mask = 0;
295	enabled_backends_count = 0;	299	enabled_backends_count = 0;
296	for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {	300	for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
297	if (((backend_disable_mask >> i) & 1) == 0) {	301	if (((backend_disable_mask >> i) & 1) == 0) {
298	enabled_backends_mask \|= (1 << i);	302	enabled_backends_mask \|= (1 << i);
299	++enabled_backends_count;	303	++enabled_backends_count;
300	}	304	}
301	if (enabled_backends_count == num_backends)	305	if (enabled_backends_count == num_backends)
302	break;	306	break;
303	}	307	}
304		308
305	if (enabled_backends_count == 0) {	309	if (enabled_backends_count == 0) {
306	enabled_backends_mask = 1;	310	enabled_backends_mask = 1;
307	enabled_backends_count = 1;	311	enabled_backends_count = 1;
308	}	312	}
309		313
310	if (enabled_backends_count != num_backends)	314	if (enabled_backends_count != num_backends)
311	num_backends = enabled_backends_count;	315	num_backends = enabled_backends_count;
312		316
313	memset((uint8_t )&swizzle_pipe[0], 0, sizeof(u32) R7XX_MAX_PIPES);	317	memset((uint8_t )&swizzle_pipe[0], 0, sizeof(u32) R7XX_MAX_PIPES);
314	switch (num_tile_pipes) {	318	switch (num_tile_pipes) {
315	case 1:	319	case 1:
316	swizzle_pipe[0] = 0;	320	swizzle_pipe[0] = 0;
317	break;	321	break;
318	case 2:	322	case 2:
319	swizzle_pipe[0] = 0;	323	swizzle_pipe[0] = 0;
320	swizzle_pipe[1] = 1;	324	swizzle_pipe[1] = 1;
321	break;	325	break;
322	case 3:	326	case 3:
323	swizzle_pipe[0] = 0;	327	swizzle_pipe[0] = 0;
324	swizzle_pipe[1] = 2;	328	swizzle_pipe[1] = 2;
325	swizzle_pipe[2] = 1;	329	swizzle_pipe[2] = 1;
326	break;	330	break;
327	case 4:	331	case 4:
328	swizzle_pipe[0] = 0;	332	swizzle_pipe[0] = 0;
329	swizzle_pipe[1] = 2;	333	swizzle_pipe[1] = 2;
330	swizzle_pipe[2] = 3;	334	swizzle_pipe[2] = 3;
331	swizzle_pipe[3] = 1;	335	swizzle_pipe[3] = 1;
332	break;	336	break;
333	case 5:	337	case 5:
334	swizzle_pipe[0] = 0;	338	swizzle_pipe[0] = 0;
335	swizzle_pipe[1] = 2;	339	swizzle_pipe[1] = 2;
336	swizzle_pipe[2] = 4;	340	swizzle_pipe[2] = 4;
337	swizzle_pipe[3] = 1;	341	swizzle_pipe[3] = 1;
338	swizzle_pipe[4] = 3;	342	swizzle_pipe[4] = 3;
339	break;	343	break;
340	case 6:	344	case 6:
341	swizzle_pipe[0] = 0;	345	swizzle_pipe[0] = 0;
342	swizzle_pipe[1] = 2;	346	swizzle_pipe[1] = 2;
343	swizzle_pipe[2] = 4;	347	swizzle_pipe[2] = 4;
344	swizzle_pipe[3] = 5;	348	swizzle_pipe[3] = 5;
345	swizzle_pipe[4] = 3;	349	swizzle_pipe[4] = 3;
346	swizzle_pipe[5] = 1;	350	swizzle_pipe[5] = 1;
347	break;	351	break;
348	case 7:	352	case 7:
349	swizzle_pipe[0] = 0;	353	swizzle_pipe[0] = 0;
350	swizzle_pipe[1] = 2;	354	swizzle_pipe[1] = 2;
351	swizzle_pipe[2] = 4;	355	swizzle_pipe[2] = 4;
352	swizzle_pipe[3] = 6;	356	swizzle_pipe[3] = 6;
353	swizzle_pipe[4] = 3;	357	swizzle_pipe[4] = 3;
354	swizzle_pipe[5] = 1;	358	swizzle_pipe[5] = 1;
355	swizzle_pipe[6] = 5;	359	swizzle_pipe[6] = 5;
356	break;	360	break;
357	case 8:	361	case 8:
358	swizzle_pipe[0] = 0;	362	swizzle_pipe[0] = 0;
359	swizzle_pipe[1] = 2;	363	swizzle_pipe[1] = 2;
360	swizzle_pipe[2] = 4;	364	swizzle_pipe[2] = 4;
361	swizzle_pipe[3] = 6;	365	swizzle_pipe[3] = 6;
362	swizzle_pipe[4] = 3;	366	swizzle_pipe[4] = 3;
363	swizzle_pipe[5] = 1;	367	swizzle_pipe[5] = 1;
364	swizzle_pipe[6] = 7;	368	swizzle_pipe[6] = 7;
365	swizzle_pipe[7] = 5;	369	swizzle_pipe[7] = 5;
366	break;	370	break;
367	}	371	}
368		372
369	cur_backend = 0;	373	cur_backend = 0;
370	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {	374	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
371	while (((1 << cur_backend) & enabled_backends_mask) == 0)	375	while (((1 << cur_backend) & enabled_backends_mask) == 0)
372	cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;	376	cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
373		377
374	backend_map \|= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));	378	backend_map \|= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
375		379
376	cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;	380	cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
377	}	381	}
378		382
379	return backend_map;	383	return backend_map;
380	}	384	}
381		385
382	static void rv770_gpu_init(struct radeon_device *rdev)	386	static void rv770_gpu_init(struct radeon_device *rdev)
383	{	387	{
384	int i, j, num_qd_pipes;	388	int i, j, num_qd_pipes;
385	u32 sx_debug_1;	389	u32 sx_debug_1;
386	u32 smx_dc_ctl0;	390	u32 smx_dc_ctl0;
387	u32 num_gs_verts_per_thread;	391	u32 num_gs_verts_per_thread;
388	u32 vgt_gs_per_es;	392	u32 vgt_gs_per_es;
389	u32 gs_prim_buffer_depth = 0;	393	u32 gs_prim_buffer_depth = 0;
390	u32 sq_ms_fifo_sizes;	394	u32 sq_ms_fifo_sizes;
391	u32 sq_config;	395	u32 sq_config;
392	u32 sq_thread_resource_mgmt;	396	u32 sq_thread_resource_mgmt;
393	u32 hdp_host_path_cntl;	397	u32 hdp_host_path_cntl;
394	u32 sq_dyn_gpr_size_simd_ab_0;	398	u32 sq_dyn_gpr_size_simd_ab_0;
395	u32 backend_map;	399	u32 backend_map;
396	u32 gb_tiling_config = 0;	400	u32 gb_tiling_config = 0;
397	u32 cc_rb_backend_disable = 0;	401	u32 cc_rb_backend_disable = 0;
398	u32 cc_gc_shader_pipe_config = 0;	402	u32 cc_gc_shader_pipe_config = 0;
399	u32 mc_arb_ramcfg;	403	u32 mc_arb_ramcfg;
400	u32 db_debug4;	404	u32 db_debug4;
401		405
402	/* setup chip specs */	406	/* setup chip specs */
403	switch (rdev->family) {	407	switch (rdev->family) {
404	case CHIP_RV770:	408	case CHIP_RV770:
405	rdev->config.rv770.max_pipes = 4;	409	rdev->config.rv770.max_pipes = 4;
406	rdev->config.rv770.max_tile_pipes = 8;	410	rdev->config.rv770.max_tile_pipes = 8;
407	rdev->config.rv770.max_simds = 10;	411	rdev->config.rv770.max_simds = 10;
408	rdev->config.rv770.max_backends = 4;	412	rdev->config.rv770.max_backends = 4;
409	rdev->config.rv770.max_gprs = 256;	413	rdev->config.rv770.max_gprs = 256;
410	rdev->config.rv770.max_threads = 248;	414	rdev->config.rv770.max_threads = 248;
411	rdev->config.rv770.max_stack_entries = 512;	415	rdev->config.rv770.max_stack_entries = 512;
412	rdev->config.rv770.max_hw_contexts = 8;	416	rdev->config.rv770.max_hw_contexts = 8;
413	rdev->config.rv770.max_gs_threads = 16 * 2;	417	rdev->config.rv770.max_gs_threads = 16 * 2;
414	rdev->config.rv770.sx_max_export_size = 128;	418	rdev->config.rv770.sx_max_export_size = 128;
415	rdev->config.rv770.sx_max_export_pos_size = 16;	419	rdev->config.rv770.sx_max_export_pos_size = 16;
416	rdev->config.rv770.sx_max_export_smx_size = 112;	420	rdev->config.rv770.sx_max_export_smx_size = 112;
417	rdev->config.rv770.sq_num_cf_insts = 2;	421	rdev->config.rv770.sq_num_cf_insts = 2;
418		422
419	rdev->config.rv770.sx_num_of_sets = 7;	423	rdev->config.rv770.sx_num_of_sets = 7;
420	rdev->config.rv770.sc_prim_fifo_size = 0xF9;	424	rdev->config.rv770.sc_prim_fifo_size = 0xF9;
421	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;	425	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
422	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;	426	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
423	break;	427	break;
424	case CHIP_RV730:	428	case CHIP_RV730:
425	rdev->config.rv770.max_pipes = 2;	429	rdev->config.rv770.max_pipes = 2;
426	rdev->config.rv770.max_tile_pipes = 4;	430	rdev->config.rv770.max_tile_pipes = 4;
427	rdev->config.rv770.max_simds = 8;	431	rdev->config.rv770.max_simds = 8;
428	rdev->config.rv770.max_backends = 2;	432	rdev->config.rv770.max_backends = 2;
429	rdev->config.rv770.max_gprs = 128;	433	rdev->config.rv770.max_gprs = 128;
430	rdev->config.rv770.max_threads = 248;	434	rdev->config.rv770.max_threads = 248;
431	rdev->config.rv770.max_stack_entries = 256;	435	rdev->config.rv770.max_stack_entries = 256;
432	rdev->config.rv770.max_hw_contexts = 8;	436	rdev->config.rv770.max_hw_contexts = 8;
433	rdev->config.rv770.max_gs_threads = 16 * 2;	437	rdev->config.rv770.max_gs_threads = 16 * 2;
434	rdev->config.rv770.sx_max_export_size = 256;	438	rdev->config.rv770.sx_max_export_size = 256;
435	rdev->config.rv770.sx_max_export_pos_size = 32;	439	rdev->config.rv770.sx_max_export_pos_size = 32;
436	rdev->config.rv770.sx_max_export_smx_size = 224;	440	rdev->config.rv770.sx_max_export_smx_size = 224;
437	rdev->config.rv770.sq_num_cf_insts = 2;	441	rdev->config.rv770.sq_num_cf_insts = 2;
438		442
439	rdev->config.rv770.sx_num_of_sets = 7;	443	rdev->config.rv770.sx_num_of_sets = 7;
440	rdev->config.rv770.sc_prim_fifo_size = 0xf9;	444	rdev->config.rv770.sc_prim_fifo_size = 0xf9;
441	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;	445	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
442	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;	446	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
443	if (rdev->config.rv770.sx_max_export_pos_size > 16) {	447	if (rdev->config.rv770.sx_max_export_pos_size > 16) {
444	rdev->config.rv770.sx_max_export_pos_size -= 16;	448	rdev->config.rv770.sx_max_export_pos_size -= 16;
445	rdev->config.rv770.sx_max_export_smx_size += 16;	449	rdev->config.rv770.sx_max_export_smx_size += 16;
446	}	450	}
447	break;	451	break;
448	case CHIP_RV710:	452	case CHIP_RV710:
449	rdev->config.rv770.max_pipes = 2;	453	rdev->config.rv770.max_pipes = 2;
450	rdev->config.rv770.max_tile_pipes = 2;	454	rdev->config.rv770.max_tile_pipes = 2;
451	rdev->config.rv770.max_simds = 2;	455	rdev->config.rv770.max_simds = 2;
452	rdev->config.rv770.max_backends = 1;	456	rdev->config.rv770.max_backends = 1;
453	rdev->config.rv770.max_gprs = 256;	457	rdev->config.rv770.max_gprs = 256;
454	rdev->config.rv770.max_threads = 192;	458	rdev->config.rv770.max_threads = 192;
455	rdev->config.rv770.max_stack_entries = 256;	459	rdev->config.rv770.max_stack_entries = 256;
456	rdev->config.rv770.max_hw_contexts = 4;	460	rdev->config.rv770.max_hw_contexts = 4;
457	rdev->config.rv770.max_gs_threads = 8 * 2;	461	rdev->config.rv770.max_gs_threads = 8 * 2;
458	rdev->config.rv770.sx_max_export_size = 128;	462	rdev->config.rv770.sx_max_export_size = 128;
459	rdev->config.rv770.sx_max_export_pos_size = 16;	463	rdev->config.rv770.sx_max_export_pos_size = 16;
460	rdev->config.rv770.sx_max_export_smx_size = 112;	464	rdev->config.rv770.sx_max_export_smx_size = 112;
461	rdev->config.rv770.sq_num_cf_insts = 1;	465	rdev->config.rv770.sq_num_cf_insts = 1;
462		466
463	rdev->config.rv770.sx_num_of_sets = 7;	467	rdev->config.rv770.sx_num_of_sets = 7;
464	rdev->config.rv770.sc_prim_fifo_size = 0x40;	468	rdev->config.rv770.sc_prim_fifo_size = 0x40;
465	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;	469	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
466	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;	470	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
467	break;	471	break;
468	case CHIP_RV740:	472	case CHIP_RV740:
469	rdev->config.rv770.max_pipes = 4;	473	rdev->config.rv770.max_pipes = 4;
470	rdev->config.rv770.max_tile_pipes = 4;	474	rdev->config.rv770.max_tile_pipes = 4;
471	rdev->config.rv770.max_simds = 8;	475	rdev->config.rv770.max_simds = 8;
472	rdev->config.rv770.max_backends = 4;	476	rdev->config.rv770.max_backends = 4;
473	rdev->config.rv770.max_gprs = 256;	477	rdev->config.rv770.max_gprs = 256;
474	rdev->config.rv770.max_threads = 248;	478	rdev->config.rv770.max_threads = 248;
475	rdev->config.rv770.max_stack_entries = 512;	479	rdev->config.rv770.max_stack_entries = 512;
476	rdev->config.rv770.max_hw_contexts = 8;	480	rdev->config.rv770.max_hw_contexts = 8;
477	rdev->config.rv770.max_gs_threads = 16 * 2;	481	rdev->config.rv770.max_gs_threads = 16 * 2;
478	rdev->config.rv770.sx_max_export_size = 256;	482	rdev->config.rv770.sx_max_export_size = 256;
479	rdev->config.rv770.sx_max_export_pos_size = 32;	483	rdev->config.rv770.sx_max_export_pos_size = 32;
480	rdev->config.rv770.sx_max_export_smx_size = 224;	484	rdev->config.rv770.sx_max_export_smx_size = 224;
481	rdev->config.rv770.sq_num_cf_insts = 2;	485	rdev->config.rv770.sq_num_cf_insts = 2;
482		486
483	rdev->config.rv770.sx_num_of_sets = 7;	487	rdev->config.rv770.sx_num_of_sets = 7;
484	rdev->config.rv770.sc_prim_fifo_size = 0x100;	488	rdev->config.rv770.sc_prim_fifo_size = 0x100;
485	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;	489	rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
486	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;	490	rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
487		491
488	if (rdev->config.rv770.sx_max_export_pos_size > 16) {	492	if (rdev->config.rv770.sx_max_export_pos_size > 16) {
489	rdev->config.rv770.sx_max_export_pos_size -= 16;	493	rdev->config.rv770.sx_max_export_pos_size -= 16;
490	rdev->config.rv770.sx_max_export_smx_size += 16;	494	rdev->config.rv770.sx_max_export_smx_size += 16;
491	}	495	}
492	break;	496	break;
493	default:	497	default:
494	break;	498	break;
495	}	499	}
496		500

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/rv770.c – Rev 1403 → 1404