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Rev 1246 Rev 1268
Line 529... Line 529...
529 
	}
 529 
	}
Line 530... Line 530...
530 
 
 530 
 
531 
	if (rdev->family == CHIP_RV770)
 531 
	if (rdev->family == CHIP_RV770)
532 
		gb_tiling_config |= BANK_TILING(1);
 532 
		gb_tiling_config |= BANK_TILING(1);
533 
	else
 533 
	else
Line 534... Line 534...
534 
		gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
 534 
		gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
Line 535... Line 535...
535 
 
 535 
 
536 
	gb_tiling_config |= GROUP_SIZE(0);
 536 
	gb_tiling_config |= GROUP_SIZE(0);
537 
 
 537 
 
538 
	if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
 538 
	if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
539 
		gb_tiling_config |= ROW_TILING(3);
 539 
		gb_tiling_config |= ROW_TILING(3);
540 
		gb_tiling_config |= SAMPLE_SPLIT(3);
 540 
		gb_tiling_config |= SAMPLE_SPLIT(3);
Line 774... Line 774...
774 
 
 774 
 
775 
int rv770_mc_init(struct radeon_device *rdev)
 775 
int rv770_mc_init(struct radeon_device *rdev)
776 
{
 776 
{
777 
	fixed20_12 a;
 777 
	fixed20_12 a;
- 
 
 778 
	u32 tmp;
778 
	u32 tmp;
 779 
	int chansize, numchan;
Line 779... Line 780...
779 
	int r;
 780 
	int r;
780 
 
 - 
 
781 
	/* Get VRAM informations */
 - 
 
782 
	/* FIXME: Don't know how to determine vram width, need to check
 - 
 
783 
	 * vram_width usage
 - 
 
784 
	 */
 781 
 
- 
 
 782 
	/* Get VRAM informations */
- 
 
 783 
	rdev->mc.vram_is_ddr = true;
- 
 
 784 
	tmp = RREG32(MC_ARB_RAMCFG);
- 
 
 785 
	if (tmp & CHANSIZE_OVERRIDE) {
- 
 
 786 
		chansize = 16;
- 
 
 787 
	} else if (tmp & CHANSIZE_MASK) {
- 
 
 788 
		chansize = 64;
- 
 
 789 
	} else {
- 
 
 790 
		chansize = 32;
- 
 
 791 
	}
- 
 
 792 
	tmp = RREG32(MC_SHARED_CHMAP);
- 
 
 793 
	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
- 
 
 794 
	case 0:
- 
 
 795 
	default:
- 
 
 796 
		numchan = 1;
- 
 
 797 
		break;
- 
 
 798 
	case 1:
- 
 
 799 
		numchan = 2;
- 
 
 800 
		break;
- 
 
 801 
	case 2:
- 
 
 802 
		numchan = 4;
- 
 
 803 
		break;
- 
 
 804 
	case 3:
- 
 
 805 
		numchan = 8;
- 
 
 806 
		break;
785 
	rdev->mc.vram_width = 128;
 807 
	}
786 
	rdev->mc.vram_is_ddr = true;
 808 
	rdev->mc.vram_width = numchan * chansize;
787 
	/* Could aper size report 0 ? */
 809 
	/* Could aper size report 0 ? */
788 
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 810 
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
789 
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 811 
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
Line 919... Line 941...
919 
	}
 941 
	}
920 
	/* Initialize scratch registers */
 942 
	/* Initialize scratch registers */
921 
	r600_scratch_init(rdev);
 943 
	r600_scratch_init(rdev);
922 
	/* Initialize surface registers */
 944 
	/* Initialize surface registers */
923 
	radeon_surface_init(rdev);
 945 
	radeon_surface_init(rdev);
- 
 
 946 
	/* Initialize clocks */
924 
	radeon_get_clock_info(rdev->ddev);
 947 
	radeon_get_clock_info(rdev->ddev);
925 
	r = radeon_clocks_init(rdev);
 948 
	r = radeon_clocks_init(rdev);
926 
	if (r)
 949 
	if (r)
927 
		return r;
 950 
		return r;
- 
 
 951 
	/* Initialize power management */
- 
 
 952 
	radeon_pm_init(rdev);
928 
	/* Fence driver */
 953 
	/* Fence driver */
929 
//   r = radeon_fence_driver_init(rdev);
 954 
//   r = radeon_fence_driver_init(rdev);
930 
//   if (r)
 955 
//   if (r)
931 
//       return r;
 956 
//       return r;
932 
	r = rv770_mc_init(rdev);
 957 
	r = rv770_mc_init(rdev);