WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/rv515.c

 	radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
 	radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
 	radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
 	radeon_ring_write(ring, PACKET0(0x20C8, 0));
 	radeon_ring_write(ring, 0);
-	radeon_ring_unlock_commit(rdev, ring);
+	radeon_ring_unlock_commit(rdev, ring, false);
+}
 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
+{
 	radeon_update_bandwidth_info(rdev);
+}
 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
+{
 	unsigned long flags;
+	uint32_t r;
 	uint32_t r;
 	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
+	r = RREG32(MC_IND_DATA);
+	WREG32(MC_IND_INDEX, 0);
-	r = RREG32(MC_IND_DATA);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 	WREG32(MC_IND_INDEX, 0);
 	return r;
+}
+void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
 	unsigned long flags;
 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
+	WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
-	WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
+	WREG32(MC_IND_DATA, (v));
-	WREG32(MC_IND_DATA, (v));
+	WREG32(MC_IND_INDEX, 0);
-	WREG32(MC_IND_INDEX, 0);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
+}
 	/* unlock regs and wait for update */
 	for (i = 0; i < rdev->num_crtc; i++) {
 		if (save->crtc_enabled[i]) {
 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
-			if ((tmp & 0x3) != 0) {
+			if ((tmp & 0x7) != 3) {
+				tmp &= ~0x7;
-				tmp &= ~0x3;
+				tmp |= 0x3;
 				WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
+			}
 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
 			if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
 	r = rv370_pcie_gart_init(rdev);
 	if (r)
 		return r;
 	rv515_set_safe_registers(rdev);
+	/* Initialize power management */
+	radeon_pm_init(rdev);
 	rdev->accel_working = true;
 	r = rv515_startup(rdev);
 	if (r) {
 		/* Somethings want wront with the accel init stop accel */
 	fixed20_12 sclk;
 };
 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 				  struct radeon_crtc *crtc,
+					 struct rv515_watermark *wm,
-				  struct rv515_watermark *wm)
+					 bool low)
+{
 	struct drm_display_mode *mode = &crtc->base.mode;
 	fixed20_12 a, b, c;
 	fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
+	fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
+	fixed20_12 sclk;
-	fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
+	u32 selected_sclk;
 	if (!crtc->base.enabled) {
 		/* FIXME: wouldn't it better to set priority mark to maximum */
 		wm->lb_request_fifo_depth = 4;
+		return;
+	}
+	/* rv6xx, rv7xx */
+	if ((rdev->family >= CHIP_RV610) &&
+	    (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
+		selected_sclk = radeon_dpm_get_sclk(rdev, low);
+	else
+		selected_sclk = rdev->pm.current_sclk;
+	/* sclk in Mhz */
+	a.full = dfixed_const(100);
-		return;
+	sclk.full = dfixed_const(selected_sclk);
 	sclk.full = dfixed_div(sclk, a);
 	if (crtc->vsc.full > dfixed_const(2))
 	 * ChunkTime = the time it takes the DCP to send one chunk of data
 	 * to the LB which consists of pipeline delay and inter chunk gap
 	 * sclk = system clock(Mhz)
 	 */
 	a.full = dfixed_const(600 * 1000);
-	chunk_time.full = dfixed_div(a, rdev->pm.sclk);
+	chunk_time.full = dfixed_div(a, sclk);
 	read_delay_latency.full = dfixed_const(1000);
 	/* Determine the worst case latency
 	 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 		wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
 		wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
+	}
+}
+static void rv515_compute_mode_priority(struct radeon_device *rdev,
+					struct rv515_watermark *wm0,
+					struct rv515_watermark *wm1,
+					struct drm_display_mode *mode0,
+					struct drm_display_mode *mode1,
+					u32 *d1mode_priority_a_cnt,
-void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
+					u32 *d2mode_priority_a_cnt)
-{
-	struct drm_display_mode *mode0 = NULL;
-	struct drm_display_mode *mode1 = NULL;
-	struct rv515_watermark wm0;
-	struct rv515_watermark wm1;
-	u32 tmp;
-	u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
 	u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
 	fixed20_12 priority_mark02, priority_mark12, fill_rate;
-	fixed20_12 a, b;
+	fixed20_12 a, b;
-	if (rdev->mode_info.crtcs[0]->base.enabled)
-		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
-	if (rdev->mode_info.crtcs[1]->base.enabled)
-		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
-	rs690_line_buffer_adjust(rdev, mode0, mode1);
-	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
-	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
-	tmp = wm0.lb_request_fifo_depth;
-	tmp |= wm1.lb_request_fifo_depth << 16;
+	*d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
-	WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
+	*d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
 	if (mode0 && mode1) {
-		if (dfixed_trunc(wm0.dbpp) > 64)
+		if (dfixed_trunc(wm0->dbpp) > 64)
-			a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
+			a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
 		else
-			a.full = wm0.num_line_pair.full;
+			a.full = wm0->num_line_pair.full;
-		if (dfixed_trunc(wm1.dbpp) > 64)
+		if (dfixed_trunc(wm1->dbpp) > 64)
-			b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
+			b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
 		else
-			b.full = wm1.num_line_pair.full;
+			b.full = wm1->num_line_pair.full;
 		a.full += b.full;
-		fill_rate.full = dfixed_div(wm0.sclk, a);
+		fill_rate.full = dfixed_div(wm0->sclk, a);
-		if (wm0.consumption_rate.full > fill_rate.full) {
+		if (wm0->consumption_rate.full > fill_rate.full) {
-			b.full = wm0.consumption_rate.full - fill_rate.full;
+			b.full = wm0->consumption_rate.full - fill_rate.full;
-			b.full = dfixed_mul(b, wm0.active_time);
+			b.full = dfixed_mul(b, wm0->active_time);
 			a.full = dfixed_const(16);
 			b.full = dfixed_div(b, a);
-			a.full = dfixed_mul(wm0.worst_case_latency,
+			a.full = dfixed_mul(wm0->worst_case_latency,
-						wm0.consumption_rate);
+						wm0->consumption_rate);
 			priority_mark02.full = a.full + b.full;
 		} else {
-			a.full = dfixed_mul(wm0.worst_case_latency,
+			a.full = dfixed_mul(wm0->worst_case_latency,
-						wm0.consumption_rate);
+						wm0->consumption_rate);
 			b.full = dfixed_const(16 * 1000);
 			priority_mark02.full = dfixed_div(a, b);
 		}
-		if (wm1.consumption_rate.full > fill_rate.full) {
+		if (wm1->consumption_rate.full > fill_rate.full) {
-			b.full = wm1.consumption_rate.full - fill_rate.full;
+			b.full = wm1->consumption_rate.full - fill_rate.full;
-			b.full = dfixed_mul(b, wm1.active_time);
+			b.full = dfixed_mul(b, wm1->active_time);
 			a.full = dfixed_const(16);
 			b.full = dfixed_div(b, a);
-			a.full = dfixed_mul(wm1.worst_case_latency,
+			a.full = dfixed_mul(wm1->worst_case_latency,
-						wm1.consumption_rate);
+						wm1->consumption_rate);
 			priority_mark12.full = a.full + b.full;
 		} else {
-			a.full = dfixed_mul(wm1.worst_case_latency,
+			a.full = dfixed_mul(wm1->worst_case_latency,
-						wm1.consumption_rate);
+						wm1->consumption_rate);
 			b.full = dfixed_const(16 * 1000);
 			priority_mark12.full = dfixed_div(a, b);
-		}
-		if (wm0.priority_mark.full > priority_mark02.full)
-			priority_mark02.full = wm0.priority_mark.full;
+		}
-		if (dfixed_trunc(priority_mark02) < 0)
+		if (wm0->priority_mark.full > priority_mark02.full)
-			priority_mark02.full = 0;
+			priority_mark02.full = wm0->priority_mark.full;
-		if (wm0.priority_mark_max.full > priority_mark02.full)
+		if (wm0->priority_mark_max.full > priority_mark02.full)
-			priority_mark02.full = wm0.priority_mark_max.full;
-		if (wm1.priority_mark.full > priority_mark12.full)
-			priority_mark12.full = wm1.priority_mark.full;
+			priority_mark02.full = wm0->priority_mark_max.full;
-		if (dfixed_trunc(priority_mark12) < 0)
+		if (wm1->priority_mark.full > priority_mark12.full)
-			priority_mark12.full = 0;
+			priority_mark12.full = wm1->priority_mark.full;
-		if (wm1.priority_mark_max.full > priority_mark12.full)
+		if (wm1->priority_mark_max.full > priority_mark12.full)
-			priority_mark12.full = wm1.priority_mark_max.full;
+			priority_mark12.full = wm1->priority_mark_max.full;
-		d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
+		*d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
-		d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
+		*d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
 		if (rdev->disp_priority == 2) {
-			d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+			*d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
-			d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+			*d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
 		}
 	} else if (mode0) {
-		if (dfixed_trunc(wm0.dbpp) > 64)
+		if (dfixed_trunc(wm0->dbpp) > 64)
-			a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
+			a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
 		else
-			a.full = wm0.num_line_pair.full;
+			a.full = wm0->num_line_pair.full;
-		fill_rate.full = dfixed_div(wm0.sclk, a);
+		fill_rate.full = dfixed_div(wm0->sclk, a);
-		if (wm0.consumption_rate.full > fill_rate.full) {
+		if (wm0->consumption_rate.full > fill_rate.full) {
-			b.full = wm0.consumption_rate.full - fill_rate.full;
+			b.full = wm0->consumption_rate.full - fill_rate.full;
-			b.full = dfixed_mul(b, wm0.active_time);
+			b.full = dfixed_mul(b, wm0->active_time);
 			a.full = dfixed_const(16);
 			b.full = dfixed_div(b, a);
-			a.full = dfixed_mul(wm0.worst_case_latency,
+			a.full = dfixed_mul(wm0->worst_case_latency,
-						wm0.consumption_rate);
+						wm0->consumption_rate);
 			priority_mark02.full = a.full + b.full;
 		} else {
-			a.full = dfixed_mul(wm0.worst_case_latency,
+			a.full = dfixed_mul(wm0->worst_case_latency,
-						wm0.consumption_rate);
+						wm0->consumption_rate);
 			b.full = dfixed_const(16);
 			priority_mark02.full = dfixed_div(a, b);
-		}
-		if (wm0.priority_mark.full > priority_mark02.full)
-			priority_mark02.full = wm0.priority_mark.full;
+		}
-		if (dfixed_trunc(priority_mark02) < 0)
+		if (wm0->priority_mark.full > priority_mark02.full)
-			priority_mark02.full = 0;
+			priority_mark02.full = wm0->priority_mark.full;
-		if (wm0.priority_mark_max.full > priority_mark02.full)
+		if (wm0->priority_mark_max.full > priority_mark02.full)
-			priority_mark02.full = wm0.priority_mark_max.full;
+			priority_mark02.full = wm0->priority_mark_max.full;
-		d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
+		*d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
 		if (rdev->disp_priority == 2)
-			d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+			*d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
 	} else if (mode1) {
-		if (dfixed_trunc(wm1.dbpp) > 64)
+		if (dfixed_trunc(wm1->dbpp) > 64)
-			a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
+			a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
 		else
-			a.full = wm1.num_line_pair.full;
+			a.full = wm1->num_line_pair.full;
-		fill_rate.full = dfixed_div(wm1.sclk, a);
+		fill_rate.full = dfixed_div(wm1->sclk, a);
-		if (wm1.consumption_rate.full > fill_rate.full) {
+		if (wm1->consumption_rate.full > fill_rate.full) {
-			b.full = wm1.consumption_rate.full - fill_rate.full;
+			b.full = wm1->consumption_rate.full - fill_rate.full;
-			b.full = dfixed_mul(b, wm1.active_time);
+			b.full = dfixed_mul(b, wm1->active_time);
 			a.full = dfixed_const(16);
 			b.full = dfixed_div(b, a);
-			a.full = dfixed_mul(wm1.worst_case_latency,
+			a.full = dfixed_mul(wm1->worst_case_latency,
-						wm1.consumption_rate);
+						wm1->consumption_rate);
 			priority_mark12.full = a.full + b.full;
 		} else {
-			a.full = dfixed_mul(wm1.worst_case_latency,
+			a.full = dfixed_mul(wm1->worst_case_latency,
-						wm1.consumption_rate);
+						wm1->consumption_rate);
 			b.full = dfixed_const(16 * 1000);
 			priority_mark12.full = dfixed_div(a, b);
-		}
-		if (wm1.priority_mark.full > priority_mark12.full)
-			priority_mark12.full = wm1.priority_mark.full;
+		}
-		if (dfixed_trunc(priority_mark12) < 0)
+		if (wm1->priority_mark.full > priority_mark12.full)
-			priority_mark12.full = 0;
+			priority_mark12.full = wm1->priority_mark.full;
-		if (wm1.priority_mark_max.full > priority_mark12.full)
+		if (wm1->priority_mark_max.full > priority_mark12.full)
-			priority_mark12.full = wm1.priority_mark_max.full;
+			priority_mark12.full = wm1->priority_mark_max.full;
-		d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
+		*d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
+		if (rdev->disp_priority == 2)
+			*d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+	}
+}
+void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
+{
+	struct drm_display_mode *mode0 = NULL;
+	struct drm_display_mode *mode1 = NULL;
+	struct rv515_watermark wm0_high, wm0_low;
+	struct rv515_watermark wm1_high, wm1_low;
+	u32 tmp;
+	u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
+	u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
+	if (rdev->mode_info.crtcs[0]->base.enabled)
+		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
+	if (rdev->mode_info.crtcs[1]->base.enabled)
+		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
+	rs690_line_buffer_adjust(rdev, mode0, mode1);
+	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
+	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
+	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
+	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
+	tmp = wm0_high.lb_request_fifo_depth;
+	tmp |= wm1_high.lb_request_fifo_depth << 16;
+	WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
+	rv515_compute_mode_priority(rdev,
+				    &wm0_high, &wm1_high,
+				    mode0, mode1,
+				    &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
+	rv515_compute_mode_priority(rdev,
-		if (rdev->disp_priority == 2)
+				    &wm0_low, &wm1_low,
-			d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+				    mode0, mode1,
 				    &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
 	WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
-	WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
+	WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
 		WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
-		WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
+	WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/rv515.c – Rev 3764 → 5078