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Rev 1268 Rev 1313
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	return -1;
 140 
	return -1;
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}
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}
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void rv515_vga_render_disable(struct radeon_device *rdev)
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void rv515_vga_render_disable(struct radeon_device *rdev)
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{
 - 
 
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	WREG32(R_000330_D1VGA_CONTROL, 0);
 - 
 
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	WREG32(R_000338_D2VGA_CONTROL, 0);
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{
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	WREG32(R_000300_VGA_RENDER_CONTROL,
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	WREG32(R_000300_VGA_RENDER_CONTROL,
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		RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
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		RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
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}
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}
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	save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
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	save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
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	save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
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	save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
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	save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
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	save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
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 390 
 
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	/* Stop all video */
 - 
 
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	WREG32(R_000330_D1VGA_CONTROL, 0);
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	/* Stop all video */
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	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
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	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
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	WREG32(R_000300_VGA_RENDER_CONTROL, 0);
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	WREG32(R_000300_VGA_RENDER_CONTROL, 0);
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	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
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	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
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	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
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	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
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	WREG32(R_006080_D1CRTC_CONTROL, 0);
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	WREG32(R_006080_D1CRTC_CONTROL, 0);
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	WREG32(R_006880_D2CRTC_CONTROL, 0);
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	WREG32(R_006880_D2CRTC_CONTROL, 0);
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	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
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	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
- 
 
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	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
- 
 
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	WREG32(R_000330_D1VGA_CONTROL, 0);
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	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
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	WREG32(R_000338_D2VGA_CONTROL, 0);
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}
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}
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void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
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void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
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	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
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	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
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	/* Unlock host access */
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	/* Unlock host access */
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	WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
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	WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
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	mdelay(1);
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	mdelay(1);
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	/* Restore video state */
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	/* Restore video state */
- 
 
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	WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
- 
 
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	WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
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	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
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	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
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	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
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	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
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	WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
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	WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
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	WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
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	WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
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	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
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	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
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	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
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	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
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	WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
 - 
 
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	WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
 - 
 
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	WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
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	WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
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}
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}
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void rv515_mc_program(struct radeon_device *rdev)
 426 
void rv515_mc_program(struct radeon_device *rdev)