WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/rv515.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include 
#include "drmP.h"
#include "rv515d.h"
#include "radeon.h"
#include "atom.h"
#include "rv515_reg_safe.h"
 
/* This files gather functions specifics to: rv515 */
int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
void rv515_gpu_init(struct radeon_device *rdev);
int rv515_mc_wait_for_idle(struct radeon_device *rdev);
 
void rv515_debugfs(struct radeon_device *rdev)
{
	if (r100_debugfs_rbbm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
	}
	if (rv515_debugfs_pipes_info_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
	}
	if (rv515_debugfs_ga_info_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
	}
}
 
void rv515_ring_start(struct radeon_device *rdev)
{
	int r;
 
    ENTER();
 
	r = radeon_ring_lock(rdev, 64);
	if (r) {
		return;
	}
	radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
	radeon_ring_write(rdev,
			  ISYNC_ANY2D_IDLE3D |
			  ISYNC_ANY3D_IDLE2D |
			  ISYNC_WAIT_IDLEGUI |
			  ISYNC_CPSCRATCH_IDLEGUI);
	radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
	radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
	radeon_ring_write(rdev, PACKET0(0x170C, 0));
	radeon_ring_write(rdev, 1 << 31);
	radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, PACKET0(0x42C8, 0));
	radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
	radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
	radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
	radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
	radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
	radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
	radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
	radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
	radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
	radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
	radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
	radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
	radeon_ring_write(rdev,
			  ((6 << MS_X0_SHIFT) |
			   (6 << MS_Y0_SHIFT) |
			   (6 << MS_X1_SHIFT) |
			   (6 << MS_Y1_SHIFT) |
			   (6 << MS_X2_SHIFT) |
			   (6 << MS_Y2_SHIFT) |
			   (6 << MSBD0_Y_SHIFT) |
			   (6 << MSBD0_X_SHIFT)));
	radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
	radeon_ring_write(rdev,
			  ((6 << MS_X3_SHIFT) |
			   (6 << MS_Y3_SHIFT) |
			   (6 << MS_X4_SHIFT) |
			   (6 << MS_Y4_SHIFT) |
			   (6 << MS_X5_SHIFT) |
			   (6 << MS_Y5_SHIFT) |
			   (6 << MSBD1_SHIFT)));
	radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
	radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
	radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
	radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
	radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
	radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
	radeon_ring_write(rdev, PACKET0(0x20C8, 0));
	radeon_ring_write(rdev, 0);
	radeon_ring_unlock_commit(rdev);
 
    LEAVE();
 
}
 
int rv515_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
	uint32_t tmp;
 
	for (i = 0; i < rdev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32_MC(MC_STATUS);
		if (tmp & MC_STATUS_IDLE) {
			return 0;
		}
		DRM_UDELAY(1);
	}
	return -1;
}
 
void rv515_vga_render_disable(struct radeon_device *rdev)
{
	WREG32(R_000330_D1VGA_CONTROL, 0);
	WREG32(R_000338_D2VGA_CONTROL, 0);
	WREG32(R_000300_VGA_RENDER_CONTROL,
		RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
}
 
void rv515_gpu_init(struct radeon_device *rdev)
{
	unsigned pipe_select_current, gb_pipe_select, tmp;
 
	r100_hdp_reset(rdev);
	r100_rb2d_reset(rdev);
 
	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "reseting GPU. Bad things might happen.\n");
	}
 
	rv515_vga_render_disable(rdev);
 
	r420_pipes_init(rdev);
	gb_pipe_select = RREG32(0x402C);
	tmp = RREG32(0x170C);
	pipe_select_current = (tmp >> 2) & 3;
	tmp = (1 << pipe_select_current) |
	      (((gb_pipe_select >> 8) & 0xF) << 4);
	WREG32_PLL(0x000D, tmp);
	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "reseting GPU. Bad things might happen.\n");
	}
	if (rv515_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait MC idle while "
		       "programming pipes. Bad things might happen.\n");
	}
}
 
int rv515_ga_reset(struct radeon_device *rdev)
{
	uint32_t tmp;
	bool reinit_cp;
	int i;
 
    ENTER();
 
	reinit_cp = rdev->cp.ready;
	rdev->cp.ready = false;
	for (i = 0; i < rdev->usec_timeout; i++) {
		WREG32(CP_CSQ_MODE, 0);
		WREG32(CP_CSQ_CNTL, 0);
		WREG32(RBBM_SOFT_RESET, 0x32005);
		(void)RREG32(RBBM_SOFT_RESET);
		udelay(200);
		WREG32(RBBM_SOFT_RESET, 0);
		/* Wait to prevent race in RBBM_STATUS */
		mdelay(1);
		tmp = RREG32(RBBM_STATUS);
		if (tmp & ((1 << 20) | (1 << 26))) {
			DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
			/* GA still busy soft reset it */
			WREG32(0x429C, 0x200);
			WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
			WREG32(0x43E0, 0);
			WREG32(0x43E4, 0);
			WREG32(0x24AC, 0);
		}
		/* Wait to prevent race in RBBM_STATUS */
		mdelay(1);
		tmp = RREG32(RBBM_STATUS);
		if (!(tmp & ((1 << 20) | (1 << 26)))) {
			break;
		}
	}
	for (i = 0; i < rdev->usec_timeout; i++) {
		tmp = RREG32(RBBM_STATUS);
		if (!(tmp & ((1 << 20) | (1 << 26)))) {
			DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
				 tmp);
			DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
			DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
			DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
			if (reinit_cp) {
				return r100_cp_init(rdev, rdev->cp.ring_size);
			}
			return 0;
		}
		DRM_UDELAY(1);
	}
	tmp = RREG32(RBBM_STATUS);
	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
	return -1;
}
 
int rv515_gpu_reset(struct radeon_device *rdev)
{
	uint32_t status;
 
    ENTER();
 
	/* reset order likely matter */
	status = RREG32(RBBM_STATUS);
	/* reset HDP */
	r100_hdp_reset(rdev);
	/* reset rb2d */
	if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
		r100_rb2d_reset(rdev);
	}
	/* reset GA */
	if (status & ((1 << 20) | (1 << 26))) {
		rv515_ga_reset(rdev);
	}
	/* reset CP */
	status = RREG32(RBBM_STATUS);
	if (status & (1 << 16)) {
		r100_cp_reset(rdev);
	}
	/* Check if GPU is idle */
	status = RREG32(RBBM_STATUS);
	if (status & (1 << 31)) {
		DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		return -1;
	}
	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
	return 0;
}
 
static void rv515_vram_get_type(struct radeon_device *rdev)
{
	uint32_t tmp;
 
	rdev->mc.vram_width = 128;
	rdev->mc.vram_is_ddr = true;
	tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
	switch (tmp) {
	case 0:
		rdev->mc.vram_width = 64;
		break;
	case 1:
		rdev->mc.vram_width = 128;
		break;
	default:
		rdev->mc.vram_width = 128;
		break;
	}
}
 
void rv515_vram_info(struct radeon_device *rdev)
{
	fixed20_12 a;
 
	rv515_vram_get_type(rdev);
 
	r100_vram_init_sizes(rdev);
	/* FIXME: we should enforce default clock in case GPU is not in
	 * default setup
	 */
	a.full = rfixed_const(100);
	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
}
 
uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
{
	uint32_t r;
 
	WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
	r = RREG32(MC_IND_DATA);
	WREG32(MC_IND_INDEX, 0);
	return r;
}
 
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
	WREG32(MC_IND_DATA, (v));
	WREG32(MC_IND_INDEX, 0);
}
 
#if defined(CONFIG_DEBUG_FS)
static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t tmp;
 
	tmp = RREG32(GB_PIPE_SELECT);
	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
	tmp = RREG32(SU_REG_DEST);
	seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
	tmp = RREG32(GB_TILE_CONFIG);
	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
	tmp = RREG32(DST_PIPE_CONFIG);
	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
	return 0;
}
 
static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t tmp;
 
	tmp = RREG32(0x2140);
	seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
	radeon_gpu_reset(rdev);
	tmp = RREG32(0x425C);
	seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
	return 0;
}
 
static struct drm_info_list rv515_pipes_info_list[] = {
	{"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
};
 
static struct drm_info_list rv515_ga_info_list[] = {
	{"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
};
#endif
 
int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
#else
	return 0;
#endif
}
 
int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
#else
	return 0;
#endif
}
 
void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
{
	save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
	save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
	save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
	save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
	save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
	save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
 
	/* Stop all video */
	WREG32(R_000330_D1VGA_CONTROL, 0);
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
	WREG32(R_000300_VGA_RENDER_CONTROL, 0);
	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
	WREG32(R_006080_D1CRTC_CONTROL, 0);
	WREG32(R_006880_D2CRTC_CONTROL, 0);
	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
}
 
void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
{
	WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
	WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
	WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
	WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
	/* Unlock host access */
	WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
	mdelay(1);
	/* Restore video state */
	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
	WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
	WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
	WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
	WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
	WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
}
 
void rv515_mc_program(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
 
	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);
 
	/* Wait for mc idle */
	if (rv515_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
	/* Write VRAM size in case we are limiting it */
	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
	/* Program MC, should be a 32bits limited address space */
	WREG32_MC(R_000001_MC_FB_LOCATION,
			S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
			S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
	WREG32(R_000134_HDP_FB_LOCATION,
		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
	if (rdev->flags & RADEON_IS_AGP) {
		WREG32_MC(R_000002_MC_AGP_LOCATION,
			S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
			S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		WREG32_MC(R_000004_MC_AGP_BASE_2,
			S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
	} else {
		WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
		WREG32_MC(R_000003_MC_AGP_BASE, 0);
		WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
	}
 
	rv515_mc_resume(rdev, &save);
}
 
void rv515_clock_startup(struct radeon_device *rdev)
{
	if (radeon_dynclks != -1 && radeon_dynclks)
		radeon_atom_set_clock_gating(rdev, 1);
	/* We need to force on some of the block */
	WREG32_PLL(R_00000F_CP_DYN_CNTL,
		RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
	WREG32_PLL(R_000011_E2_DYN_CNTL,
		RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
	WREG32_PLL(R_000013_IDCT_DYN_CNTL,
		RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
}
 
static int rv515_startup(struct radeon_device *rdev)
{
	int r;
 
	rv515_mc_program(rdev);
	/* Resume clock */
	rv515_clock_startup(rdev);
	/* Initialize GPU configuration (# pipes, ...) */
	rv515_gpu_init(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	if (rdev->flags & RADEON_IS_PCIE) {
		r = rv370_pcie_gart_enable(rdev);
		if (r)
			return r;
	}
	/* Enable IRQ */
//	rdev->irq.sw_int = true;
//	rs600_irq_set(rdev);
	/* 1M ring buffer */
//	r = r100_cp_init(rdev, 1024 * 1024);
//	if (r) {
//		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
//		return r;
//	}
//	r = r100_wb_init(rdev);
//	if (r)
//		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
//	r = r100_ib_init(rdev);
//	if (r) {
//		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
//		return r;
//	}
	return 0;
}
 
 
void rv515_set_safe_registers(struct radeon_device *rdev)
{
	rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
}
 
int rv515_init(struct radeon_device *rdev)
{
	int r;
 
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* TODO: disable VGA need to use VGA request */
	/* BIOS*/
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r)
			return r;
	} else {
		dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
		return -EINVAL;
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (!radeon_card_posted(rdev) && rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		atom_asic_init(rdev->mode_info.atom_context);
	}
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* Initialize power management */
	radeon_pm_init(rdev);
	/* Get vram informations */
	rv515_vram_info(rdev);
	/* Initialize memory controller (also test AGP) */
	r = r420_mc_init(rdev);
    dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
	if (r)
		return r;
	rv515_debugfs(rdev);
	/* Fence driver */
//   r = radeon_fence_driver_init(rdev);
//   if (r)
//       return r;
//	r = radeon_irq_kms_init(rdev);
//	if (r)
//		return r;
	/* Memory manager */
	r = radeon_object_init(rdev);
	if (r)
		return r;
	r = rv370_pcie_gart_init(rdev);
	if (r)
		return r;
	rv515_set_safe_registers(rdev);
	rdev->accel_working = true;
	r = rv515_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
//		rv515_suspend(rdev);
//		r100_cp_fini(rdev);
//		r100_wb_fini(rdev);
//		r100_ib_fini(rdev);
		rv370_pcie_gart_fini(rdev);
//		radeon_agp_fini(rdev);
//		radeon_irq_kms_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}
 
void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
{
	int index_reg = 0x6578 + crtc->crtc_offset;
	int data_reg = 0x657c + crtc->crtc_offset;
 
	WREG32(0x659C + crtc->crtc_offset, 0x0);
	WREG32(0x6594 + crtc->crtc_offset, 0x705);
	WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
	WREG32(0x65D8 + crtc->crtc_offset, 0x0);
	WREG32(0x65B0 + crtc->crtc_offset, 0x0);
	WREG32(0x65C0 + crtc->crtc_offset, 0x0);
	WREG32(0x65D4 + crtc->crtc_offset, 0x0);
	WREG32(index_reg, 0x0);
	WREG32(data_reg, 0x841880A8);
	WREG32(index_reg, 0x1);
	WREG32(data_reg, 0x84208680);
	WREG32(index_reg, 0x2);
	WREG32(data_reg, 0xBFF880B0);
	WREG32(index_reg, 0x100);
	WREG32(data_reg, 0x83D88088);
	WREG32(index_reg, 0x101);
	WREG32(data_reg, 0x84608680);
	WREG32(index_reg, 0x102);
	WREG32(data_reg, 0xBFF080D0);
	WREG32(index_reg, 0x200);
	WREG32(data_reg, 0x83988068);
	WREG32(index_reg, 0x201);
	WREG32(data_reg, 0x84A08680);
	WREG32(index_reg, 0x202);
	WREG32(data_reg, 0xBFF080F8);
	WREG32(index_reg, 0x300);
	WREG32(data_reg, 0x83588058);
	WREG32(index_reg, 0x301);
	WREG32(data_reg, 0x84E08660);
	WREG32(index_reg, 0x302);
	WREG32(data_reg, 0xBFF88120);
	WREG32(index_reg, 0x400);
	WREG32(data_reg, 0x83188040);
	WREG32(index_reg, 0x401);
	WREG32(data_reg, 0x85008660);
	WREG32(index_reg, 0x402);
	WREG32(data_reg, 0xBFF88150);
	WREG32(index_reg, 0x500);
	WREG32(data_reg, 0x82D88030);
	WREG32(index_reg, 0x501);
	WREG32(data_reg, 0x85408640);
	WREG32(index_reg, 0x502);
	WREG32(data_reg, 0xBFF88180);
	WREG32(index_reg, 0x600);
	WREG32(data_reg, 0x82A08018);
	WREG32(index_reg, 0x601);
	WREG32(data_reg, 0x85808620);
	WREG32(index_reg, 0x602);
	WREG32(data_reg, 0xBFF081B8);
	WREG32(index_reg, 0x700);
	WREG32(data_reg, 0x82608010);
	WREG32(index_reg, 0x701);
	WREG32(data_reg, 0x85A08600);
	WREG32(index_reg, 0x702);
	WREG32(data_reg, 0x800081F0);
	WREG32(index_reg, 0x800);
	WREG32(data_reg, 0x8228BFF8);
	WREG32(index_reg, 0x801);
	WREG32(data_reg, 0x85E085E0);
	WREG32(index_reg, 0x802);
	WREG32(data_reg, 0xBFF88228);
	WREG32(index_reg, 0x10000);
	WREG32(data_reg, 0x82A8BF00);
	WREG32(index_reg, 0x10001);
	WREG32(data_reg, 0x82A08CC0);
	WREG32(index_reg, 0x10002);
	WREG32(data_reg, 0x8008BEF8);
	WREG32(index_reg, 0x10100);
	WREG32(data_reg, 0x81F0BF28);
	WREG32(index_reg, 0x10101);
	WREG32(data_reg, 0x83608CA0);
	WREG32(index_reg, 0x10102);
	WREG32(data_reg, 0x8018BED0);
	WREG32(index_reg, 0x10200);
	WREG32(data_reg, 0x8148BF38);
	WREG32(index_reg, 0x10201);
	WREG32(data_reg, 0x84408C80);
	WREG32(index_reg, 0x10202);
	WREG32(data_reg, 0x8008BEB8);
	WREG32(index_reg, 0x10300);
	WREG32(data_reg, 0x80B0BF78);
	WREG32(index_reg, 0x10301);
	WREG32(data_reg, 0x85008C20);
	WREG32(index_reg, 0x10302);
	WREG32(data_reg, 0x8020BEA0);
	WREG32(index_reg, 0x10400);
	WREG32(data_reg, 0x8028BF90);
	WREG32(index_reg, 0x10401);
	WREG32(data_reg, 0x85E08BC0);
	WREG32(index_reg, 0x10402);
	WREG32(data_reg, 0x8018BE90);
	WREG32(index_reg, 0x10500);
	WREG32(data_reg, 0xBFB8BFB0);
	WREG32(index_reg, 0x10501);
	WREG32(data_reg, 0x86C08B40);
	WREG32(index_reg, 0x10502);
	WREG32(data_reg, 0x8010BE90);
	WREG32(index_reg, 0x10600);
	WREG32(data_reg, 0xBF58BFC8);
	WREG32(index_reg, 0x10601);
	WREG32(data_reg, 0x87A08AA0);
	WREG32(index_reg, 0x10602);
	WREG32(data_reg, 0x8010BE98);
	WREG32(index_reg, 0x10700);
	WREG32(data_reg, 0xBF10BFF0);
	WREG32(index_reg, 0x10701);
	WREG32(data_reg, 0x886089E0);
	WREG32(index_reg, 0x10702);
	WREG32(data_reg, 0x8018BEB0);
	WREG32(index_reg, 0x10800);
	WREG32(data_reg, 0xBED8BFE8);
	WREG32(index_reg, 0x10801);
	WREG32(data_reg, 0x89408940);
	WREG32(index_reg, 0x10802);
	WREG32(data_reg, 0xBFE8BED8);
	WREG32(index_reg, 0x20000);
	WREG32(data_reg, 0x80008000);
	WREG32(index_reg, 0x20001);
	WREG32(data_reg, 0x90008000);
	WREG32(index_reg, 0x20002);
	WREG32(data_reg, 0x80008000);
	WREG32(index_reg, 0x20003);
	WREG32(data_reg, 0x80008000);
	WREG32(index_reg, 0x20100);
	WREG32(data_reg, 0x80108000);
	WREG32(index_reg, 0x20101);
	WREG32(data_reg, 0x8FE0BF70);
	WREG32(index_reg, 0x20102);
	WREG32(data_reg, 0xBFE880C0);
	WREG32(index_reg, 0x20103);
	WREG32(data_reg, 0x80008000);
	WREG32(index_reg, 0x20200);
	WREG32(data_reg, 0x8018BFF8);
	WREG32(index_reg, 0x20201);
	WREG32(data_reg, 0x8F80BF08);
	WREG32(index_reg, 0x20202);
	WREG32(data_reg, 0xBFD081A0);
	WREG32(index_reg, 0x20203);
	WREG32(data_reg, 0xBFF88000);
	WREG32(index_reg, 0x20300);
	WREG32(data_reg, 0x80188000);
	WREG32(index_reg, 0x20301);
	WREG32(data_reg, 0x8EE0BEC0);
	WREG32(index_reg, 0x20302);
	WREG32(data_reg, 0xBFB082A0);
	WREG32(index_reg, 0x20303);
	WREG32(data_reg, 0x80008000);
	WREG32(index_reg, 0x20400);
	WREG32(data_reg, 0x80188000);
	WREG32(index_reg, 0x20401);
	WREG32(data_reg, 0x8E00BEA0);
	WREG32(index_reg, 0x20402);
	WREG32(data_reg, 0xBF8883C0);
	WREG32(index_reg, 0x20403);
	WREG32(data_reg, 0x80008000);
	WREG32(index_reg, 0x20500);
	WREG32(data_reg, 0x80188000);
	WREG32(index_reg, 0x20501);
	WREG32(data_reg, 0x8D00BE90);
	WREG32(index_reg, 0x20502);
	WREG32(data_reg, 0xBF588500);
	WREG32(index_reg, 0x20503);
	WREG32(data_reg, 0x80008008);
	WREG32(index_reg, 0x20600);
	WREG32(data_reg, 0x80188000);
	WREG32(index_reg, 0x20601);
	WREG32(data_reg, 0x8BC0BE98);
	WREG32(index_reg, 0x20602);
	WREG32(data_reg, 0xBF308660);
	WREG32(index_reg, 0x20603);
	WREG32(data_reg, 0x80008008);
	WREG32(index_reg, 0x20700);
	WREG32(data_reg, 0x80108000);
	WREG32(index_reg, 0x20701);
	WREG32(data_reg, 0x8A80BEB0);
	WREG32(index_reg, 0x20702);
	WREG32(data_reg, 0xBF0087C0);
	WREG32(index_reg, 0x20703);
	WREG32(data_reg, 0x80008008);
	WREG32(index_reg, 0x20800);
	WREG32(data_reg, 0x80108000);
	WREG32(index_reg, 0x20801);
	WREG32(data_reg, 0x8920BED0);
	WREG32(index_reg, 0x20802);
	WREG32(data_reg, 0xBED08920);
	WREG32(index_reg, 0x20803);
	WREG32(data_reg, 0x80008010);
	WREG32(index_reg, 0x30000);
	WREG32(data_reg, 0x90008000);
	WREG32(index_reg, 0x30001);
	WREG32(data_reg, 0x80008000);
	WREG32(index_reg, 0x30100);
	WREG32(data_reg, 0x8FE0BF90);
	WREG32(index_reg, 0x30101);
	WREG32(data_reg, 0xBFF880A0);
	WREG32(index_reg, 0x30200);
	WREG32(data_reg, 0x8F60BF40);
	WREG32(index_reg, 0x30201);
	WREG32(data_reg, 0xBFE88180);
	WREG32(index_reg, 0x30300);
	WREG32(data_reg, 0x8EC0BF00);
	WREG32(index_reg, 0x30301);
	WREG32(data_reg, 0xBFC88280);
	WREG32(index_reg, 0x30400);
	WREG32(data_reg, 0x8DE0BEE0);
	WREG32(index_reg, 0x30401);
	WREG32(data_reg, 0xBFA083A0);
	WREG32(index_reg, 0x30500);
	WREG32(data_reg, 0x8CE0BED0);
	WREG32(index_reg, 0x30501);
	WREG32(data_reg, 0xBF7884E0);
	WREG32(index_reg, 0x30600);
	WREG32(data_reg, 0x8BA0BED8);
	WREG32(index_reg, 0x30601);
	WREG32(data_reg, 0xBF508640);
	WREG32(index_reg, 0x30700);
	WREG32(data_reg, 0x8A60BEE8);
	WREG32(index_reg, 0x30701);
	WREG32(data_reg, 0xBF2087A0);
	WREG32(index_reg, 0x30800);
	WREG32(data_reg, 0x8900BF00);
	WREG32(index_reg, 0x30801);
	WREG32(data_reg, 0xBF008900);
}
 
struct rv515_watermark {
	u32        lb_request_fifo_depth;
	fixed20_12 num_line_pair;
	fixed20_12 estimated_width;
	fixed20_12 worst_case_latency;
	fixed20_12 consumption_rate;
	fixed20_12 active_time;
	fixed20_12 dbpp;
	fixed20_12 priority_mark_max;
	fixed20_12 priority_mark;
	fixed20_12 sclk;
};
 
void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
				  struct radeon_crtc *crtc,
				  struct rv515_watermark *wm)
{
	struct drm_display_mode *mode = &crtc->base.mode;
	fixed20_12 a, b, c;
	fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
	fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 
	if (!crtc->base.enabled) {
		/* FIXME: wouldn't it better to set priority mark to maximum */
		wm->lb_request_fifo_depth = 4;
		return;
	}
 
	if (crtc->vsc.full > rfixed_const(2))
		wm->num_line_pair.full = rfixed_const(2);
	else
		wm->num_line_pair.full = rfixed_const(1);
 
	b.full = rfixed_const(mode->crtc_hdisplay);
	c.full = rfixed_const(256);
	a.full = rfixed_mul(wm->num_line_pair, b);
	request_fifo_depth.full = rfixed_div(a, c);
	if (a.full < rfixed_const(4)) {
		wm->lb_request_fifo_depth = 4;
	} else {
		wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
	}
 
	/* Determine consumption rate
	 *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
	 *  vtaps = number of vertical taps,
	 *  vsc = vertical scaling ratio, defined as source/destination
	 *  hsc = horizontal scaling ration, defined as source/destination
	 */
	a.full = rfixed_const(mode->clock);
	b.full = rfixed_const(1000);
	a.full = rfixed_div(a, b);
	pclk.full = rfixed_div(b, a);
	if (crtc->rmx_type != RMX_OFF) {
		b.full = rfixed_const(2);
		if (crtc->vsc.full > b.full)
			b.full = crtc->vsc.full;
		b.full = rfixed_mul(b, crtc->hsc);
		c.full = rfixed_const(2);
		b.full = rfixed_div(b, c);
		consumption_time.full = rfixed_div(pclk, b);
	} else {
		consumption_time.full = pclk.full;
	}
	a.full = rfixed_const(1);
	wm->consumption_rate.full = rfixed_div(a, consumption_time);
 
 
	/* Determine line time
	 *  LineTime = total time for one line of displayhtotal
	 *  LineTime = total number of horizontal pixels
	 *  pclk = pixel clock period(ns)
	 */
	a.full = rfixed_const(crtc->base.mode.crtc_htotal);
	line_time.full = rfixed_mul(a, pclk);
 
	/* Determine active time
	 *  ActiveTime = time of active region of display within one line,
	 *  hactive = total number of horizontal active pixels
	 *  htotal = total number of horizontal pixels
	 */
	a.full = rfixed_const(crtc->base.mode.crtc_htotal);
	b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
	wm->active_time.full = rfixed_mul(line_time, b);
	wm->active_time.full = rfixed_div(wm->active_time, a);
 
	/* Determine chunk time
	 * ChunkTime = the time it takes the DCP to send one chunk of data
	 * to the LB which consists of pipeline delay and inter chunk gap
	 * sclk = system clock(Mhz)
	 */
	a.full = rfixed_const(600 * 1000);
	chunk_time.full = rfixed_div(a, rdev->pm.sclk);
	read_delay_latency.full = rfixed_const(1000);
 
	/* Determine the worst case latency
	 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
	 * WorstCaseLatency = worst case time from urgent to when the MC starts
	 *                    to return data
	 * READ_DELAY_IDLE_MAX = constant of 1us
	 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
	 *             which consists of pipeline delay and inter chunk gap
	 */
	if (rfixed_trunc(wm->num_line_pair) > 1) {
		a.full = rfixed_const(3);
		wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
		wm->worst_case_latency.full += read_delay_latency.full;
	} else {
		wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
	}
 
	/* Determine the tolerable latency
	 * TolerableLatency = Any given request has only 1 line time
	 *                    for the data to be returned
	 * LBRequestFifoDepth = Number of chunk requests the LB can
	 *                      put into the request FIFO for a display
	 *  LineTime = total time for one line of display
	 *  ChunkTime = the time it takes the DCP to send one chunk
	 *              of data to the LB which consists of
	 *  pipeline delay and inter chunk gap
	 */
	if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
		tolerable_latency.full = line_time.full;
	} else {
		tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
		tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
		tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
		tolerable_latency.full = line_time.full - tolerable_latency.full;
	}
	/* We assume worst case 32bits (4 bytes) */
	wm->dbpp.full = rfixed_const(2 * 16);
 
	/* Determine the maximum priority mark
	 *  width = viewport width in pixels
	 */
	a.full = rfixed_const(16);
	wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
	wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
 
	/* Determine estimated width */
	estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
	estimated_width.full = rfixed_div(estimated_width, consumption_time);
	if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
		wm->priority_mark.full = rfixed_const(10);
	} else {
		a.full = rfixed_const(16);
		wm->priority_mark.full = rfixed_div(estimated_width, a);
		wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
	}
}
 
void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
{
	struct drm_display_mode *mode0 = NULL;
	struct drm_display_mode *mode1 = NULL;
	struct rv515_watermark wm0;
	struct rv515_watermark wm1;
	u32 tmp;
	fixed20_12 priority_mark02, priority_mark12, fill_rate;
	fixed20_12 a, b;
 
	if (rdev->mode_info.crtcs[0]->base.enabled)
		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
	if (rdev->mode_info.crtcs[1]->base.enabled)
		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
	rs690_line_buffer_adjust(rdev, mode0, mode1);
 
	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 
	tmp = wm0.lb_request_fifo_depth;
	tmp |= wm1.lb_request_fifo_depth << 16;
	WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
 
	if (mode0 && mode1) {
		if (rfixed_trunc(wm0.dbpp) > 64)
			a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
		else
			a.full = wm0.num_line_pair.full;
		if (rfixed_trunc(wm1.dbpp) > 64)
			b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
		else
			b.full = wm1.num_line_pair.full;
		a.full += b.full;
		fill_rate.full = rfixed_div(wm0.sclk, a);
		if (wm0.consumption_rate.full > fill_rate.full) {
			b.full = wm0.consumption_rate.full - fill_rate.full;
			b.full = rfixed_mul(b, wm0.active_time);
			a.full = rfixed_const(16);
			b.full = rfixed_div(b, a);
			a.full = rfixed_mul(wm0.worst_case_latency,
						wm0.consumption_rate);
			priority_mark02.full = a.full + b.full;
		} else {
			a.full = rfixed_mul(wm0.worst_case_latency,
						wm0.consumption_rate);
			b.full = rfixed_const(16 * 1000);
			priority_mark02.full = rfixed_div(a, b);
		}
		if (wm1.consumption_rate.full > fill_rate.full) {
			b.full = wm1.consumption_rate.full - fill_rate.full;
			b.full = rfixed_mul(b, wm1.active_time);
			a.full = rfixed_const(16);
			b.full = rfixed_div(b, a);
			a.full = rfixed_mul(wm1.worst_case_latency,
						wm1.consumption_rate);
			priority_mark12.full = a.full + b.full;
		} else {
			a.full = rfixed_mul(wm1.worst_case_latency,
						wm1.consumption_rate);
			b.full = rfixed_const(16 * 1000);
			priority_mark12.full = rfixed_div(a, b);
		}
		if (wm0.priority_mark.full > priority_mark02.full)
			priority_mark02.full = wm0.priority_mark.full;
		if (rfixed_trunc(priority_mark02) < 0)
			priority_mark02.full = 0;
		if (wm0.priority_mark_max.full > priority_mark02.full)
			priority_mark02.full = wm0.priority_mark_max.full;
		if (wm1.priority_mark.full > priority_mark12.full)
			priority_mark12.full = wm1.priority_mark.full;
		if (rfixed_trunc(priority_mark12) < 0)
			priority_mark12.full = 0;
		if (wm1.priority_mark_max.full > priority_mark12.full)
			priority_mark12.full = wm1.priority_mark_max.full;
		WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
		WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
		WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
		WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
	} else if (mode0) {
		if (rfixed_trunc(wm0.dbpp) > 64)
			a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
		else
			a.full = wm0.num_line_pair.full;
		fill_rate.full = rfixed_div(wm0.sclk, a);
		if (wm0.consumption_rate.full > fill_rate.full) {
			b.full = wm0.consumption_rate.full - fill_rate.full;
			b.full = rfixed_mul(b, wm0.active_time);
			a.full = rfixed_const(16);
			b.full = rfixed_div(b, a);
			a.full = rfixed_mul(wm0.worst_case_latency,
						wm0.consumption_rate);
			priority_mark02.full = a.full + b.full;
		} else {
			a.full = rfixed_mul(wm0.worst_case_latency,
						wm0.consumption_rate);
			b.full = rfixed_const(16);
			priority_mark02.full = rfixed_div(a, b);
		}
		if (wm0.priority_mark.full > priority_mark02.full)
			priority_mark02.full = wm0.priority_mark.full;
		if (rfixed_trunc(priority_mark02) < 0)
			priority_mark02.full = 0;
		if (wm0.priority_mark_max.full > priority_mark02.full)
			priority_mark02.full = wm0.priority_mark_max.full;
		WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
		WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
		WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
		WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
	} else {
		if (rfixed_trunc(wm1.dbpp) > 64)
			a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
		else
			a.full = wm1.num_line_pair.full;
		fill_rate.full = rfixed_div(wm1.sclk, a);
		if (wm1.consumption_rate.full > fill_rate.full) {
			b.full = wm1.consumption_rate.full - fill_rate.full;
			b.full = rfixed_mul(b, wm1.active_time);
			a.full = rfixed_const(16);
			b.full = rfixed_div(b, a);
			a.full = rfixed_mul(wm1.worst_case_latency,
						wm1.consumption_rate);
			priority_mark12.full = a.full + b.full;
		} else {
			a.full = rfixed_mul(wm1.worst_case_latency,
						wm1.consumption_rate);
			b.full = rfixed_const(16 * 1000);
			priority_mark12.full = rfixed_div(a, b);
		}
		if (wm1.priority_mark.full > priority_mark12.full)
			priority_mark12.full = wm1.priority_mark.full;
		if (rfixed_trunc(priority_mark12) < 0)
			priority_mark12.full = 0;
		if (wm1.priority_mark_max.full > priority_mark12.full)
			priority_mark12.full = wm1.priority_mark_max.full;
		WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
		WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
		WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
		WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
	}
}
 
void rv515_bandwidth_update(struct radeon_device *rdev)
{
	uint32_t tmp;
	struct drm_display_mode *mode0 = NULL;
	struct drm_display_mode *mode1 = NULL;
 
	if (rdev->mode_info.crtcs[0]->base.enabled)
		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
	if (rdev->mode_info.crtcs[1]->base.enabled)
		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
	/*
	 * Set display0/1 priority up in the memory controller for
	 * modes if the user specifies HIGH for displaypriority
	 * option.
	 */
	if (rdev->disp_priority == 2) {
		tmp = RREG32_MC(MC_MISC_LAT_TIMER);
		tmp &= ~MC_DISP1R_INIT_LAT_MASK;
		tmp &= ~MC_DISP0R_INIT_LAT_MASK;
		if (mode1)
			tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
		if (mode0)
			tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
		WREG32_MC(MC_MISC_LAT_TIMER, tmp);
	}
	rv515_bandwidth_avivo_update(rdev);
}

Rev 1246	Rev 1268
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#include	28	#include
29	#include "drmP.h"	29	#include "drmP.h"
30	#include "rv515d.h"	30	#include "rv515d.h"
31	#include "radeon.h"	31	#include "radeon.h"
32	#include "atom.h"	32	#include "atom.h"
33	#include "rv515_reg_safe.h"	33	#include "rv515_reg_safe.h"
34		34
35	/* This files gather functions specifics to: rv515 */	35	/* This files gather functions specifics to: rv515 */
36	int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);	36	int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
37	int rv515_debugfs_ga_info_init(struct radeon_device *rdev);	37	int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
38	void rv515_gpu_init(struct radeon_device *rdev);	38	void rv515_gpu_init(struct radeon_device *rdev);
39	int rv515_mc_wait_for_idle(struct radeon_device *rdev);	39	int rv515_mc_wait_for_idle(struct radeon_device *rdev);
40		40
41	void rv515_debugfs(struct radeon_device *rdev)	41	void rv515_debugfs(struct radeon_device *rdev)
42	{	42	{
43	if (r100_debugfs_rbbm_init(rdev)) {	43	if (r100_debugfs_rbbm_init(rdev)) {
44	DRM_ERROR("Failed to register debugfs file for RBBM !\n");	44	DRM_ERROR("Failed to register debugfs file for RBBM !\n");
45	}	45	}
46	if (rv515_debugfs_pipes_info_init(rdev)) {	46	if (rv515_debugfs_pipes_info_init(rdev)) {
47	DRM_ERROR("Failed to register debugfs file for pipes !\n");	47	DRM_ERROR("Failed to register debugfs file for pipes !\n");
48	}	48	}
49	if (rv515_debugfs_ga_info_init(rdev)) {	49	if (rv515_debugfs_ga_info_init(rdev)) {
50	DRM_ERROR("Failed to register debugfs file for pipes !\n");	50	DRM_ERROR("Failed to register debugfs file for pipes !\n");
51	}	51	}
52	}	52	}
53		53
54	void rv515_ring_start(struct radeon_device *rdev)	54	void rv515_ring_start(struct radeon_device *rdev)
55	{	55	{
56	int r;	56	int r;
57		57
58	ENTER();	58	ENTER();
59		59
60	r = radeon_ring_lock(rdev, 64);	60	r = radeon_ring_lock(rdev, 64);
61	if (r) {	61	if (r) {
62	return;	62	return;
63	}	63	}
64	radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));	64	radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
65	radeon_ring_write(rdev,	65	radeon_ring_write(rdev,
66	ISYNC_ANY2D_IDLE3D \|	66	ISYNC_ANY2D_IDLE3D \|
67	ISYNC_ANY3D_IDLE2D \|	67	ISYNC_ANY3D_IDLE2D \|
68	ISYNC_WAIT_IDLEGUI \|	68	ISYNC_WAIT_IDLEGUI \|
69	ISYNC_CPSCRATCH_IDLEGUI);	69	ISYNC_CPSCRATCH_IDLEGUI);
70	radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));	70	radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
71	radeon_ring_write(rdev, WAIT_2D_IDLECLEAN \| WAIT_3D_IDLECLEAN);	71	radeon_ring_write(rdev, WAIT_2D_IDLECLEAN \| WAIT_3D_IDLECLEAN);
72	radeon_ring_write(rdev, PACKET0(0x170C, 0));	72	radeon_ring_write(rdev, PACKET0(0x170C, 0));
73	radeon_ring_write(rdev, 1 << 31);	73	radeon_ring_write(rdev, 1 << 31);
74	radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));	74	radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
75	radeon_ring_write(rdev, 0);	75	radeon_ring_write(rdev, 0);
76	radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));	76	radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
77	radeon_ring_write(rdev, 0);	77	radeon_ring_write(rdev, 0);
78	radeon_ring_write(rdev, PACKET0(0x42C8, 0));	78	radeon_ring_write(rdev, PACKET0(0x42C8, 0));
79	radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);	79	radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
80	radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));	80	radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
81	radeon_ring_write(rdev, 0);	81	radeon_ring_write(rdev, 0);
82	radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));	82	radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
83	radeon_ring_write(rdev, RB3D_DC_FLUSH \| RB3D_DC_FREE);	83	radeon_ring_write(rdev, RB3D_DC_FLUSH \| RB3D_DC_FREE);
84	radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));	84	radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
85	radeon_ring_write(rdev, ZC_FLUSH \| ZC_FREE);	85	radeon_ring_write(rdev, ZC_FLUSH \| ZC_FREE);
86	radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));	86	radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
87	radeon_ring_write(rdev, WAIT_2D_IDLECLEAN \| WAIT_3D_IDLECLEAN);	87	radeon_ring_write(rdev, WAIT_2D_IDLECLEAN \| WAIT_3D_IDLECLEAN);
88	radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));	88	radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
89	radeon_ring_write(rdev, 0);	89	radeon_ring_write(rdev, 0);
90	radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));	90	radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
91	radeon_ring_write(rdev, RB3D_DC_FLUSH \| RB3D_DC_FREE);	91	radeon_ring_write(rdev, RB3D_DC_FLUSH \| RB3D_DC_FREE);
92	radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));	92	radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
93	radeon_ring_write(rdev, ZC_FLUSH \| ZC_FREE);	93	radeon_ring_write(rdev, ZC_FLUSH \| ZC_FREE);
94	radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));	94	radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
95	radeon_ring_write(rdev,	95	radeon_ring_write(rdev,
96	((6 << MS_X0_SHIFT) \|	96	((6 << MS_X0_SHIFT) \|
97	(6 << MS_Y0_SHIFT) \|	97	(6 << MS_Y0_SHIFT) \|
98	(6 << MS_X1_SHIFT) \|	98	(6 << MS_X1_SHIFT) \|
99	(6 << MS_Y1_SHIFT) \|	99	(6 << MS_Y1_SHIFT) \|
100	(6 << MS_X2_SHIFT) \|	100	(6 << MS_X2_SHIFT) \|
101	(6 << MS_Y2_SHIFT) \|	101	(6 << MS_Y2_SHIFT) \|
102	(6 << MSBD0_Y_SHIFT) \|	102	(6 << MSBD0_Y_SHIFT) \|
103	(6 << MSBD0_X_SHIFT)));	103	(6 << MSBD0_X_SHIFT)));
104	radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));	104	radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
105	radeon_ring_write(rdev,	105	radeon_ring_write(rdev,
106	((6 << MS_X3_SHIFT) \|	106	((6 << MS_X3_SHIFT) \|
107	(6 << MS_Y3_SHIFT) \|	107	(6 << MS_Y3_SHIFT) \|
108	(6 << MS_X4_SHIFT) \|	108	(6 << MS_X4_SHIFT) \|
109	(6 << MS_Y4_SHIFT) \|	109	(6 << MS_Y4_SHIFT) \|
110	(6 << MS_X5_SHIFT) \|	110	(6 << MS_X5_SHIFT) \|
111	(6 << MS_Y5_SHIFT) \|	111	(6 << MS_Y5_SHIFT) \|
112	(6 << MSBD1_SHIFT)));	112	(6 << MSBD1_SHIFT)));
113	radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));	113	radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
114	radeon_ring_write(rdev, GA_DEADLOCK_CNTL \| GA_FASTSYNC_CNTL);	114	radeon_ring_write(rdev, GA_DEADLOCK_CNTL \| GA_FASTSYNC_CNTL);
115	radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));	115	radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
116	radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE \| BACK_PTYPE_TRIANGE);	116	radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE \| BACK_PTYPE_TRIANGE);
117	radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));	117	radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
118	radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST \| COLOR_ROUND_NEAREST);	118	radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST \| COLOR_ROUND_NEAREST);
119	radeon_ring_write(rdev, PACKET0(0x20C8, 0));	119	radeon_ring_write(rdev, PACKET0(0x20C8, 0));
120	radeon_ring_write(rdev, 0);	120	radeon_ring_write(rdev, 0);
121	radeon_ring_unlock_commit(rdev);	121	radeon_ring_unlock_commit(rdev);
122		122
123	LEAVE();	123	LEAVE();
124		124
125	}	125	}
126		126
127	int rv515_mc_wait_for_idle(struct radeon_device *rdev)	127	int rv515_mc_wait_for_idle(struct radeon_device *rdev)
128	{	128	{
129	unsigned i;	129	unsigned i;
130	uint32_t tmp;	130	uint32_t tmp;
131		131
132	for (i = 0; i < rdev->usec_timeout; i++) {	132	for (i = 0; i < rdev->usec_timeout; i++) {
133	/* read MC_STATUS */	133	/* read MC_STATUS */
134	tmp = RREG32_MC(MC_STATUS);	134	tmp = RREG32_MC(MC_STATUS);
135	if (tmp & MC_STATUS_IDLE) {	135	if (tmp & MC_STATUS_IDLE) {
136	return 0;	136	return 0;
137	}	137	}
138	DRM_UDELAY(1);	138	DRM_UDELAY(1);
139	}	139	}
140	return -1;	140	return -1;
141	}	141	}
142		142
143	void rv515_vga_render_disable(struct radeon_device *rdev)	143	void rv515_vga_render_disable(struct radeon_device *rdev)
144	{	144	{
-		145	WREG32(R_000330_D1VGA_CONTROL, 0);
-		146	WREG32(R_000338_D2VGA_CONTROL, 0);
145	WREG32(R_000300_VGA_RENDER_CONTROL,	147	WREG32(R_000300_VGA_RENDER_CONTROL,
146	RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);	148	RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
147	}	149	}
148		150
149	void rv515_gpu_init(struct radeon_device *rdev)	151	void rv515_gpu_init(struct radeon_device *rdev)
150	{	152	{
151	unsigned pipe_select_current, gb_pipe_select, tmp;	153	unsigned pipe_select_current, gb_pipe_select, tmp;
152		154
153	r100_hdp_reset(rdev);	155	r100_hdp_reset(rdev);
154	r100_rb2d_reset(rdev);	156	r100_rb2d_reset(rdev);
155		157
156	if (r100_gui_wait_for_idle(rdev)) {	158	if (r100_gui_wait_for_idle(rdev)) {
157	printk(KERN_WARNING "Failed to wait GUI idle while "	159	printk(KERN_WARNING "Failed to wait GUI idle while "
158	"reseting GPU. Bad things might happen.\n");	160	"reseting GPU. Bad things might happen.\n");
159	}	161	}
160		162
161	rv515_vga_render_disable(rdev);	163	rv515_vga_render_disable(rdev);
162		164
163	r420_pipes_init(rdev);	165	r420_pipes_init(rdev);
164	gb_pipe_select = RREG32(0x402C);	166	gb_pipe_select = RREG32(0x402C);
165	tmp = RREG32(0x170C);	167	tmp = RREG32(0x170C);
166	pipe_select_current = (tmp >> 2) & 3;	168	pipe_select_current = (tmp >> 2) & 3;
167	tmp = (1 << pipe_select_current) \|	169	tmp = (1 << pipe_select_current) \|
168	(((gb_pipe_select >> 8) & 0xF) << 4);	170	(((gb_pipe_select >> 8) & 0xF) << 4);
169	WREG32_PLL(0x000D, tmp);	171	WREG32_PLL(0x000D, tmp);
170	if (r100_gui_wait_for_idle(rdev)) {	172	if (r100_gui_wait_for_idle(rdev)) {
171	printk(KERN_WARNING "Failed to wait GUI idle while "	173	printk(KERN_WARNING "Failed to wait GUI idle while "
172	"reseting GPU. Bad things might happen.\n");	174	"reseting GPU. Bad things might happen.\n");
173	}	175	}
174	if (rv515_mc_wait_for_idle(rdev)) {	176	if (rv515_mc_wait_for_idle(rdev)) {
175	printk(KERN_WARNING "Failed to wait MC idle while "	177	printk(KERN_WARNING "Failed to wait MC idle while "
176	"programming pipes. Bad things might happen.\n");	178	"programming pipes. Bad things might happen.\n");
177	}	179	}
178	}	180	}
179		181
180	int rv515_ga_reset(struct radeon_device *rdev)	182	int rv515_ga_reset(struct radeon_device *rdev)
181	{	183	{
182	uint32_t tmp;	184	uint32_t tmp;
183	bool reinit_cp;	185	bool reinit_cp;
184	int i;	186	int i;
185		187
186	ENTER();	188	ENTER();
187		189
188	reinit_cp = rdev->cp.ready;	190	reinit_cp = rdev->cp.ready;
189	rdev->cp.ready = false;	191	rdev->cp.ready = false;
190	for (i = 0; i < rdev->usec_timeout; i++) {	192	for (i = 0; i < rdev->usec_timeout; i++) {
191	WREG32(CP_CSQ_MODE, 0);	193	WREG32(CP_CSQ_MODE, 0);
192	WREG32(CP_CSQ_CNTL, 0);	194	WREG32(CP_CSQ_CNTL, 0);
193	WREG32(RBBM_SOFT_RESET, 0x32005);	195	WREG32(RBBM_SOFT_RESET, 0x32005);
194	(void)RREG32(RBBM_SOFT_RESET);	196	(void)RREG32(RBBM_SOFT_RESET);
195	udelay(200);	197	udelay(200);
196	WREG32(RBBM_SOFT_RESET, 0);	198	WREG32(RBBM_SOFT_RESET, 0);
197	/* Wait to prevent race in RBBM_STATUS */	199	/* Wait to prevent race in RBBM_STATUS */
198	mdelay(1);	200	mdelay(1);
199	tmp = RREG32(RBBM_STATUS);	201	tmp = RREG32(RBBM_STATUS);
200	if (tmp & ((1 << 20) \| (1 << 26))) {	202	if (tmp & ((1 << 20) \| (1 << 26))) {
201	DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);	203	DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
202	/* GA still busy soft reset it */	204	/* GA still busy soft reset it */
203	WREG32(0x429C, 0x200);	205	WREG32(0x429C, 0x200);
204	WREG32(VAP_PVS_STATE_FLUSH_REG, 0);	206	WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
205	WREG32(0x43E0, 0);	207	WREG32(0x43E0, 0);
206	WREG32(0x43E4, 0);	208	WREG32(0x43E4, 0);
207	WREG32(0x24AC, 0);	209	WREG32(0x24AC, 0);
208	}	210	}
209	/* Wait to prevent race in RBBM_STATUS */	211	/* Wait to prevent race in RBBM_STATUS */
210	mdelay(1);	212	mdelay(1);
211	tmp = RREG32(RBBM_STATUS);	213	tmp = RREG32(RBBM_STATUS);
212	if (!(tmp & ((1 << 20) \| (1 << 26)))) {	214	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
213	break;	215	break;
214	}	216	}
215	}	217	}
216	for (i = 0; i < rdev->usec_timeout; i++) {	218	for (i = 0; i < rdev->usec_timeout; i++) {
217	tmp = RREG32(RBBM_STATUS);	219	tmp = RREG32(RBBM_STATUS);
218	if (!(tmp & ((1 << 20) \| (1 << 26)))) {	220	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
219	DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",	221	DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
220	tmp);	222	tmp);
221	DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));	223	DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
222	DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));	224	DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
223	DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));	225	DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
224	if (reinit_cp) {	226	if (reinit_cp) {
225	return r100_cp_init(rdev, rdev->cp.ring_size);	227	return r100_cp_init(rdev, rdev->cp.ring_size);
226	}	228	}
227	return 0;	229	return 0;
228	}	230	}
229	DRM_UDELAY(1);	231	DRM_UDELAY(1);
230	}	232	}
231	tmp = RREG32(RBBM_STATUS);	233	tmp = RREG32(RBBM_STATUS);
232	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);	234	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
233	return -1;	235	return -1;
234	}	236	}
235		237
236	int rv515_gpu_reset(struct radeon_device *rdev)	238	int rv515_gpu_reset(struct radeon_device *rdev)
237	{	239	{
238	uint32_t status;	240	uint32_t status;
239		241
240	ENTER();	242	ENTER();
241		243
242	/* reset order likely matter */	244	/* reset order likely matter */
243	status = RREG32(RBBM_STATUS);	245	status = RREG32(RBBM_STATUS);
244	/* reset HDP */	246	/* reset HDP */
245	r100_hdp_reset(rdev);	247	r100_hdp_reset(rdev);
246	/* reset rb2d */	248	/* reset rb2d */
247	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {	249	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
248	r100_rb2d_reset(rdev);	250	r100_rb2d_reset(rdev);
249	}	251	}
250	/* reset GA */	252	/* reset GA */
251	if (status & ((1 << 20) \| (1 << 26))) {	253	if (status & ((1 << 20) \| (1 << 26))) {
252	rv515_ga_reset(rdev);	254	rv515_ga_reset(rdev);
253	}	255	}
254	/* reset CP */	256	/* reset CP */
255	status = RREG32(RBBM_STATUS);	257	status = RREG32(RBBM_STATUS);
256	if (status & (1 << 16)) {	258	if (status & (1 << 16)) {
257	r100_cp_reset(rdev);	259	r100_cp_reset(rdev);
258	}	260	}
259	/* Check if GPU is idle */	261	/* Check if GPU is idle */
260	status = RREG32(RBBM_STATUS);	262	status = RREG32(RBBM_STATUS);
261	if (status & (1 << 31)) {	263	if (status & (1 << 31)) {
262	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);	264	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
263	return -1;	265	return -1;
264	}	266	}
265	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);	267	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
266	return 0;	268	return 0;
267	}	269	}
268		270
269	static void rv515_vram_get_type(struct radeon_device *rdev)	271	static void rv515_vram_get_type(struct radeon_device *rdev)
270	{	272	{
271	uint32_t tmp;	273	uint32_t tmp;
272		274
273	rdev->mc.vram_width = 128;	275	rdev->mc.vram_width = 128;
274	rdev->mc.vram_is_ddr = true;	276	rdev->mc.vram_is_ddr = true;
275	tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;	277	tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
276	switch (tmp) {	278	switch (tmp) {
277	case 0:	279	case 0:
278	rdev->mc.vram_width = 64;	280	rdev->mc.vram_width = 64;
279	break;	281	break;
280	case 1:	282	case 1:
281	rdev->mc.vram_width = 128;	283	rdev->mc.vram_width = 128;
282	break;	284	break;
283	default:	285	default:
284	rdev->mc.vram_width = 128;	286	rdev->mc.vram_width = 128;
285	break;	287	break;
286	}	288	}
287	}	289	}
288		290
289	void rv515_vram_info(struct radeon_device *rdev)	291	void rv515_vram_info(struct radeon_device *rdev)
290	{	292	{
291	fixed20_12 a;	293	fixed20_12 a;
292		294
293	rv515_vram_get_type(rdev);	295	rv515_vram_get_type(rdev);
294		296
295	r100_vram_init_sizes(rdev);	297	r100_vram_init_sizes(rdev);
296	/* FIXME: we should enforce default clock in case GPU is not in	298	/* FIXME: we should enforce default clock in case GPU is not in
297	* default setup	299	* default setup
298	*/	300	*/
299	a.full = rfixed_const(100);	301	a.full = rfixed_const(100);
300	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);	302	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
301	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);	303	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
302	}	304	}
303		305
304	uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)	306	uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
305	{	307	{
306	uint32_t r;	308	uint32_t r;
307		309
308	WREG32(MC_IND_INDEX, 0x7f0000 \| (reg & 0xffff));	310	WREG32(MC_IND_INDEX, 0x7f0000 \| (reg & 0xffff));
309	r = RREG32(MC_IND_DATA);	311	r = RREG32(MC_IND_DATA);
310	WREG32(MC_IND_INDEX, 0);	312	WREG32(MC_IND_INDEX, 0);
311	return r;	313	return r;
312	}	314	}
313		315
314	void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)	316	void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
315	{	317	{
316	WREG32(MC_IND_INDEX, 0xff0000 \| ((reg) & 0xffff));	318	WREG32(MC_IND_INDEX, 0xff0000 \| ((reg) & 0xffff));
317	WREG32(MC_IND_DATA, (v));	319	WREG32(MC_IND_DATA, (v));
318	WREG32(MC_IND_INDEX, 0);	320	WREG32(MC_IND_INDEX, 0);
319	}	321	}
320		322
321	#if defined(CONFIG_DEBUG_FS)	323	#if defined(CONFIG_DEBUG_FS)
322	static int rv515_debugfs_pipes_info(struct seq_file m, void data)	324	static int rv515_debugfs_pipes_info(struct seq_file m, void data)
323	{	325	{
324	struct drm_info_node node = (struct drm_info_node ) m->private;	326	struct drm_info_node node = (struct drm_info_node ) m->private;
325	struct drm_device *dev = node->minor->dev;	327	struct drm_device *dev = node->minor->dev;
326	struct radeon_device *rdev = dev->dev_private;	328	struct radeon_device *rdev = dev->dev_private;
327	uint32_t tmp;	329	uint32_t tmp;
328		330
329	tmp = RREG32(GB_PIPE_SELECT);	331	tmp = RREG32(GB_PIPE_SELECT);
330	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);	332	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
331	tmp = RREG32(SU_REG_DEST);	333	tmp = RREG32(SU_REG_DEST);
332	seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);	334	seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
333	tmp = RREG32(GB_TILE_CONFIG);	335	tmp = RREG32(GB_TILE_CONFIG);
334	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);	336	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
335	tmp = RREG32(DST_PIPE_CONFIG);	337	tmp = RREG32(DST_PIPE_CONFIG);
336	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);	338	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
337	return 0;	339	return 0;
338	}	340	}
339		341
340	static int rv515_debugfs_ga_info(struct seq_file m, void data)	342	static int rv515_debugfs_ga_info(struct seq_file m, void data)
341	{	343	{
342	struct drm_info_node node = (struct drm_info_node ) m->private;	344	struct drm_info_node node = (struct drm_info_node ) m->private;
343	struct drm_device *dev = node->minor->dev;	345	struct drm_device *dev = node->minor->dev;
344	struct radeon_device *rdev = dev->dev_private;	346	struct radeon_device *rdev = dev->dev_private;
345	uint32_t tmp;	347	uint32_t tmp;
346		348
347	tmp = RREG32(0x2140);	349	tmp = RREG32(0x2140);
348	seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);	350	seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
349	radeon_gpu_reset(rdev);	351	radeon_gpu_reset(rdev);
350	tmp = RREG32(0x425C);	352	tmp = RREG32(0x425C);
351	seq_printf(m, "GA_IDLE 0x%08x\n", tmp);	353	seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
352	return 0;	354	return 0;
353	}	355	}
354		356
355	static struct drm_info_list rv515_pipes_info_list[] = {	357	static struct drm_info_list rv515_pipes_info_list[] = {
356	{"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},	358	{"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
357	};	359	};
358		360
359	static struct drm_info_list rv515_ga_info_list[] = {	361	static struct drm_info_list rv515_ga_info_list[] = {
360	{"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},	362	{"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
361	};	363	};
362	#endif	364	#endif
363		365
364	int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)	366	int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
365	{	367	{
366	#if defined(CONFIG_DEBUG_FS)	368	#if defined(CONFIG_DEBUG_FS)
367	return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);	369	return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
368	#else	370	#else
369	return 0;	371	return 0;
370	#endif	372	#endif
371	}	373	}
372		374
373	int rv515_debugfs_ga_info_init(struct radeon_device *rdev)	375	int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
374	{	376	{
375	#if defined(CONFIG_DEBUG_FS)	377	#if defined(CONFIG_DEBUG_FS)
376	return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);	378	return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
377	#else	379	#else
378	return 0;	380	return 0;
379	#endif	381	#endif
380	}	382	}
381		383
382	void rv515_mc_stop(struct radeon_device rdev, struct rv515_mc_save save)	384	void rv515_mc_stop(struct radeon_device rdev, struct rv515_mc_save save)
383	{	385	{
384	save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);	386	save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
385	save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);	387	save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
386	save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);	388	save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
387	save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);	389	save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
388	save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);	390	save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
389	save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);	391	save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
390		392
391	/* Stop all video */	393	/* Stop all video */
392	WREG32(R_000330_D1VGA_CONTROL, 0);	394	WREG32(R_000330_D1VGA_CONTROL, 0);
393	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);	395	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
394	WREG32(R_000300_VGA_RENDER_CONTROL, 0);	396	WREG32(R_000300_VGA_RENDER_CONTROL, 0);
395	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);	397	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
396	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);	398	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
397	WREG32(R_006080_D1CRTC_CONTROL, 0);	399	WREG32(R_006080_D1CRTC_CONTROL, 0);
398	WREG32(R_006880_D2CRTC_CONTROL, 0);	400	WREG32(R_006880_D2CRTC_CONTROL, 0);
399	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);	401	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
400	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);	402	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
401	}	403	}
402		404
403	void rv515_mc_resume(struct radeon_device rdev, struct rv515_mc_save save)	405	void rv515_mc_resume(struct radeon_device rdev, struct rv515_mc_save save)
404	{	406	{
405	WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);	407	WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
406	WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);	408	WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
407	WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);	409	WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
408	WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);	410	WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
409	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);	411	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
410	/* Unlock host access */	412	/* Unlock host access */
411	WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);	413	WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
412	mdelay(1);	414	mdelay(1);
413	/* Restore video state */	415	/* Restore video state */
414	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);	416	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
415	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);	417	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
416	WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);	418	WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
417	WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);	419	WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
418	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);	420	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
419	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);	421	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
420	WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);	422	WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
421	WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);	423	WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
422	WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);	424	WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
423	}	425	}
424		426
425	void rv515_mc_program(struct radeon_device *rdev)	427	void rv515_mc_program(struct radeon_device *rdev)
426	{	428	{
427	struct rv515_mc_save save;	429	struct rv515_mc_save save;
428		430
429	/* Stops all mc clients */	431	/* Stops all mc clients */
430	rv515_mc_stop(rdev, &save);	432	rv515_mc_stop(rdev, &save);
431		433
432	/* Wait for mc idle */	434	/* Wait for mc idle */
433	if (rv515_mc_wait_for_idle(rdev))	435	if (rv515_mc_wait_for_idle(rdev))
434	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");	436	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
435	/* Write VRAM size in case we are limiting it */	437	/* Write VRAM size in case we are limiting it */
436	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);	438	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
437	/* Program MC, should be a 32bits limited address space */	439	/* Program MC, should be a 32bits limited address space */
438	WREG32_MC(R_000001_MC_FB_LOCATION,	440	WREG32_MC(R_000001_MC_FB_LOCATION,
439	S_000001_MC_FB_START(rdev->mc.vram_start >> 16) \|	441	S_000001_MC_FB_START(rdev->mc.vram_start >> 16) \|
440	S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));	442	S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
441	WREG32(R_000134_HDP_FB_LOCATION,	443	WREG32(R_000134_HDP_FB_LOCATION,
442	S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));	444	S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
443	if (rdev->flags & RADEON_IS_AGP) {	445	if (rdev->flags & RADEON_IS_AGP) {
444	WREG32_MC(R_000002_MC_AGP_LOCATION,	446	WREG32_MC(R_000002_MC_AGP_LOCATION,
445	S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) \|	447	S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
446	S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));	448	S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
447	WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));	449	WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
448	WREG32_MC(R_000004_MC_AGP_BASE_2,	450	WREG32_MC(R_000004_MC_AGP_BASE_2,
449	S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));	451	S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
450	} else {	452	} else {
451	WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);	453	WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
452	WREG32_MC(R_000003_MC_AGP_BASE, 0);	454	WREG32_MC(R_000003_MC_AGP_BASE, 0);
453	WREG32_MC(R_000004_MC_AGP_BASE_2, 0);	455	WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
454	}	456	}
455		457
456	rv515_mc_resume(rdev, &save);	458	rv515_mc_resume(rdev, &save);
457	}	459	}
458		460
459	void rv515_clock_startup(struct radeon_device *rdev)	461	void rv515_clock_startup(struct radeon_device *rdev)
460	{	462	{
461	if (radeon_dynclks != -1 && radeon_dynclks)	463	if (radeon_dynclks != -1 && radeon_dynclks)
462	radeon_atom_set_clock_gating(rdev, 1);	464	radeon_atom_set_clock_gating(rdev, 1);
463	/* We need to force on some of the block */	465	/* We need to force on some of the block */
464	WREG32_PLL(R_00000F_CP_DYN_CNTL,	466	WREG32_PLL(R_00000F_CP_DYN_CNTL,
465	RREG32_PLL(R_00000F_CP_DYN_CNTL) \| S_00000F_CP_FORCEON(1));	467	RREG32_PLL(R_00000F_CP_DYN_CNTL) \| S_00000F_CP_FORCEON(1));
466	WREG32_PLL(R_000011_E2_DYN_CNTL,	468	WREG32_PLL(R_000011_E2_DYN_CNTL,
467	RREG32_PLL(R_000011_E2_DYN_CNTL) \| S_000011_E2_FORCEON(1));	469	RREG32_PLL(R_000011_E2_DYN_CNTL) \| S_000011_E2_FORCEON(1));
468	WREG32_PLL(R_000013_IDCT_DYN_CNTL,	470	WREG32_PLL(R_000013_IDCT_DYN_CNTL,
469	RREG32_PLL(R_000013_IDCT_DYN_CNTL) \| S_000013_IDCT_FORCEON(1));	471	RREG32_PLL(R_000013_IDCT_DYN_CNTL) \| S_000013_IDCT_FORCEON(1));
470	}	472	}
471		473
472	static int rv515_startup(struct radeon_device *rdev)	474	static int rv515_startup(struct radeon_device *rdev)
473	{	475	{
474	int r;	476	int r;
475		477
476	rv515_mc_program(rdev);	478	rv515_mc_program(rdev);
477	/* Resume clock */	479	/* Resume clock */
478	rv515_clock_startup(rdev);	480	rv515_clock_startup(rdev);
479	/* Initialize GPU configuration (# pipes, ...) */	481	/* Initialize GPU configuration (# pipes, ...) */
480	rv515_gpu_init(rdev);	482	rv515_gpu_init(rdev);
481	/* Initialize GART (initialize after TTM so we can allocate	483	/* Initialize GART (initialize after TTM so we can allocate
482	* memory through TTM but finalize after TTM) */	484	* memory through TTM but finalize after TTM) */
483	if (rdev->flags & RADEON_IS_PCIE) {	485	if (rdev->flags & RADEON_IS_PCIE) {
484	r = rv370_pcie_gart_enable(rdev);	486	r = rv370_pcie_gart_enable(rdev);
485	if (r)	487	if (r)
486	return r;	488	return r;
487	}	489	}
488	/* Enable IRQ */	490	/* Enable IRQ */
489	// rdev->irq.sw_int = true;	491	// rdev->irq.sw_int = true;
490	// rs600_irq_set(rdev);	492	// rs600_irq_set(rdev);
491	/* 1M ring buffer */	493	/* 1M ring buffer */
492	// r = r100_cp_init(rdev, 1024 * 1024);	494	// r = r100_cp_init(rdev, 1024 * 1024);
493	// if (r) {	495	// if (r) {
494	// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);	496	// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
495	// return r;	497	// return r;
496	// }	498	// }
497	// r = r100_wb_init(rdev);	499	// r = r100_wb_init(rdev);
498	// if (r)	500	// if (r)

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/rv515.c – Rev 1246 → 1268