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Rev 3192 Rev 3764
Line 146... Line 146...
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}
 146 
}
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 147 
 
148 
static void rs690_mc_init(struct radeon_device *rdev)
 148 
static void rs690_mc_init(struct radeon_device *rdev)
149 
{
 149 
{
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 150 
	u64 base;
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 151 
	uint32_t h_addr, l_addr;
Line 150... Line 152...
150 
	u64 base;
 152 
	unsigned long long k8_addr;
151 
 
 153 
 
152 
	rs400_gart_adjust_size(rdev);
 154 
	rs400_gart_adjust_size(rdev);
153 
	rdev->mc.vram_is_ddr = true;
 155 
	rdev->mc.vram_is_ddr = true;
Line 158... Line 160...
158 
	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 160 
	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
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	rdev->mc.visible_vram_size = rdev->mc.aper_size;
 161 
	rdev->mc.visible_vram_size = rdev->mc.aper_size;
160 
	base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
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	base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 
	base = G_000100_MC_FB_START(base) << 16;
 163 
	base = G_000100_MC_FB_START(base) << 16;
162 
	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 164 
	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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 165 
 
- 
 
 166 
	/* Use K8 direct mapping for fast fb access. */
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 167 
	rdev->fastfb_working = false;
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 168 
	h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
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 169 
	l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
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 170 
	k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
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 171 
#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
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 172 
	if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
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 173 
#endif
- 
 
 174 
	{
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 175 
		/* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
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 176 
		 * memory is present.
- 
 
 177 
		 */
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 178 
		if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
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 179 
			DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
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 180 
					(unsigned long long)rdev->mc.aper_base, k8_addr);
- 
 
 181 
			rdev->mc.aper_base = (resource_size_t)k8_addr;
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 182 
			rdev->fastfb_working = true;
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 183 
		}
- 
 
 184 
	}
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 185 
 
163 
	rs690_pm_info(rdev);
 186 
	rs690_pm_info(rdev);
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	radeon_vram_location(rdev, &rdev->mc, base);
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	radeon_vram_location(rdev, &rdev->mc, base);
165 
	rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
 188 
	rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
166 
	radeon_gtt_location(rdev, &rdev->mc);
 189 
	radeon_gtt_location(rdev, &rdev->mc);
167 
	radeon_update_bandwidth_info(rdev);
 190 
	radeon_update_bandwidth_info(rdev);
Line 626... Line 649...
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		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 649 
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
627 
		return r;
 650 
		return r;
628 
	}
 651 
	}
Line 629... Line 652...
629 
 
 652 
 
- 
 
 653 
	/* Enable IRQ */
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 654 
	if (!rdev->irq.installed) {
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 655 
		r = radeon_irq_kms_init(rdev);
- 
 
 656 
		if (r)
- 
 
 657 
			return r;
- 
 
 658 
	}
630 
	/* Enable IRQ */
 659 
 
631 
	rs600_irq_set(rdev);
 660 
	rs600_irq_set(rdev);
632 
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 661 
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
633 
	/* 1M ring buffer */
 662 
	/* 1M ring buffer */
634 
	r = r100_cp_init(rdev, 1024 * 1024);
 663 
	r = r100_cp_init(rdev, 1024 * 1024);
Line 694... Line 723...
694 
	rv515_debugfs(rdev);
 723 
	rv515_debugfs(rdev);
695 
	/* Fence driver */
 724 
	/* Fence driver */
696 
	r = radeon_fence_driver_init(rdev);
 725 
	r = radeon_fence_driver_init(rdev);
697 
	if (r)
 726 
	if (r)
698 
		return r;
 727 
		return r;
699 
	r = radeon_irq_kms_init(rdev);
 - 
 
700 
	if (r)
 - 
 
701 
		return r;
 - 
 
702 
	/* Memory manager */
 728 
	/* Memory manager */
703 
	r = radeon_bo_init(rdev);
 729 
	r = radeon_bo_init(rdev);
704 
	if (r)
 730 
	if (r)
705 
		return r;
 731 
		return r;
706 
	r = rs400_gart_init(rdev);
 732 
	r = rs400_gart_init(rdev);