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Rev 1268 Rev 1403
Line 129... Line 129...
129 
	rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
 129 
	rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
130 
}
 130 
}
Line 131... Line 131...
131 
 
 131 
 
132 
void rs690_vram_info(struct radeon_device *rdev)
 132 
void rs690_vram_info(struct radeon_device *rdev)
133 
{
 - 
 
134 
	uint32_t tmp;
 133 
{
Line 135... Line 134...
135 
	fixed20_12 a;
 134 
	fixed20_12 a;
136 
 
 - 
 
- 
 
 135 
 
137 
	rs400_gart_adjust_size(rdev);
 136 
	rs400_gart_adjust_size(rdev);
138 
	/* DDR for all card after R300 & IGP */
 - 
 
139 
	rdev->mc.vram_is_ddr = true;
 - 
 
140 
	/* FIXME: is this correct for RS690/RS740 ? */
 - 
 
141 
	tmp = RREG32(RADEON_MEM_CNTL);
 137 
 
142 
	if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
 - 
 
143 
		rdev->mc.vram_width = 128;
 - 
 
144 
	} else {
 138 
	rdev->mc.vram_is_ddr = true;
145 
		rdev->mc.vram_width = 64;
 139 
		rdev->mc.vram_width = 128;
146 
	}
 140 
 
Line 147... Line 141...
147 
	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 141 
	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
148 
	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 142 
	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
- 
 
 143 
 
- 
 
 144 
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
- 
 
 145 
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
- 
 
 146 
 
- 
 
 147 
	if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
- 
 
 148 
		rdev->mc.mc_vram_size = rdev->mc.aper_size;
- 
 
 149 
 
149 
 
 150 
	if (rdev->mc.real_vram_size > rdev->mc.aper_size)
150 
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 151 
		rdev->mc.real_vram_size = rdev->mc.aper_size;
151 
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 152 
 
152 
	rs690_pm_info(rdev);
 153 
	rs690_pm_info(rdev);
153 
	/* FIXME: we should enforce default clock in case GPU is not in
 154 
	/* FIXME: we should enforce default clock in case GPU is not in
Line 159... Line 160...
159 
	a.full = rfixed_const(16);
 160 
	a.full = rfixed_const(16);
160 
	/* core_bandwidth = sclk(Mhz) * 16 */
 161 
	/* core_bandwidth = sclk(Mhz) * 16 */
161 
	rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
 162 
	rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
162 
}
 163 
}
Line -... Line 164...
- 
 
 164 
 
- 
 
 165 
static int rs690_mc_init(struct radeon_device *rdev)
- 
 
 166 
{
- 
 
 167 
	int r;
- 
 
 168 
	u32 tmp;
- 
 
 169 
 
- 
 
 170 
	/* Setup GPU memory space */
- 
 
 171 
	tmp = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
- 
 
 172 
	rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
- 
 
 173 
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
- 
 
 174 
	r = radeon_mc_setup(rdev);
- 
 
 175 
	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
- 
 
 176 
	if (r)
- 
 
 177 
		return r;
- 
 
 178 
	return 0;
- 
 
 179 
}
163 
 
 180 
 
164 
void rs690_line_buffer_adjust(struct radeon_device *rdev,
 181 
void rs690_line_buffer_adjust(struct radeon_device *rdev,
165 
			      struct drm_display_mode *mode1,
 182 
			      struct drm_display_mode *mode1,
166 
			      struct drm_display_mode *mode2)
 183 
			      struct drm_display_mode *mode2)
167 
{
 184 
{
Line 242... Line 259...
242 
	else
 259 
	else
243 
		wm->num_line_pair.full = rfixed_const(1);
 260 
		wm->num_line_pair.full = rfixed_const(1);
Line 244... Line 261...
244 
 
 261 
 
245 
	b.full = rfixed_const(mode->crtc_hdisplay);
 262 
	b.full = rfixed_const(mode->crtc_hdisplay);
- 
 
 263 
	c.full = rfixed_const(256);
246 
	c.full = rfixed_const(256);
 264 
	a.full = rfixed_div(b, c);
247 
	a.full = rfixed_mul(wm->num_line_pair, b);
 265 
	request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
248 
	request_fifo_depth.full = rfixed_div(a, c);
 266 
	request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
249 
	if (a.full < rfixed_const(4)) {
 267 
	if (a.full < rfixed_const(4)) {
250 
		wm->lb_request_fifo_depth = 4;
 268 
		wm->lb_request_fifo_depth = 4;
251 
	} else {
 269 
	} else {
252 
		wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
 270 
		wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
Line 372... Line 390...
372 
	 *  width = viewport width in pixels
 390 
	 *  width = viewport width in pixels
373 
	 */
 391 
	 */
374 
	a.full = rfixed_const(16);
 392 
	a.full = rfixed_const(16);
375 
	wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 393 
	wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
376 
	wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
 394 
	wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
- 
 
 395 
	wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
Line 377... Line 396...
377 
 
 396 
 
378 
	/* Determine estimated width */
 397 
	/* Determine estimated width */
379 
	estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 398 
	estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
380 
	estimated_width.full = rfixed_div(estimated_width, consumption_time);
 399 
	estimated_width.full = rfixed_div(estimated_width, consumption_time);
381 
	if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 400 
	if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
382 
		wm->priority_mark.full = rfixed_const(10);
 401 
		wm->priority_mark.full = rfixed_const(10);
383 
	} else {
 402 
	} else {
384 
		a.full = rfixed_const(16);
 403 
		a.full = rfixed_const(16);
- 
 
 404 
		wm->priority_mark.full = rfixed_div(estimated_width, a);
385 
		wm->priority_mark.full = rfixed_div(estimated_width, a);
 405 
		wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
386 
		wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 406 
		wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
387 
	}
 407 
	}
Line 388... Line 408...
388 
}
 408 
}
Line 605... Line 625...
605 
	if (r)
 625 
	if (r)
606 
		return r;
 626 
		return r;
607 
	/* Enable IRQ */
 627 
	/* Enable IRQ */
608 
//	rdev->irq.sw_int = true;
 628 
//	rdev->irq.sw_int = true;
609 
//	rs600_irq_set(rdev);
 629 
//	rs600_irq_set(rdev);
- 
 
 630 
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
610 
	/* 1M ring buffer */
 631 
	/* 1M ring buffer */
611 
//	r = r100_cp_init(rdev, 1024 * 1024);
 632 
//	r = r100_cp_init(rdev, 1024 * 1024);
612 
//	if (r) {
 633 
//	if (r) {
613 
//		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 634 
//		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
614 
//		return r;
 635 
//		return r;
Line 657... Line 678...
657 
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 678 
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
658 
			RREG32(R_000E40_RBBM_STATUS),
 679 
			RREG32(R_000E40_RBBM_STATUS),
659 
			RREG32(R_0007C0_CP_STAT));
 680 
			RREG32(R_0007C0_CP_STAT));
660 
	}
 681 
	}
661 
	/* check if cards are posted or not */
 682 
	/* check if cards are posted or not */
662 
	if (!radeon_card_posted(rdev) && rdev->bios) {
 683 
	if (radeon_boot_test_post_card(rdev) == false)
663 
		DRM_INFO("GPU not posted. posting now...\n");
 - 
 
664 
		atom_asic_init(rdev->mode_info.atom_context);
 684 
		return -EINVAL;
665 
	}
 685 
 
666 
	/* Initialize clocks */
 686 
	/* Initialize clocks */
667 
	radeon_get_clock_info(rdev->ddev);
 687 
	radeon_get_clock_info(rdev->ddev);
668 
	/* Initialize power management */
 688 
	/* Initialize power management */
669 
	radeon_pm_init(rdev);
 689 
	radeon_pm_init(rdev);
670 
	/* Get vram informations */
 690 
	/* Get vram informations */
671 
	rs690_vram_info(rdev);
 691 
	rs690_vram_info(rdev);
672 
	/* Initialize memory controller (also test AGP) */
 692 
	/* Initialize memory controller (also test AGP) */
673 
	r = r420_mc_init(rdev);
 693 
	r = rs690_mc_init(rdev);
674 
	if (r)
 694 
	if (r)
675 
		return r;
 695 
		return r;
676 
	rv515_debugfs(rdev);
 696 
	rv515_debugfs(rdev);
677 
	/* Fence driver */
 697 
	/* Fence driver */
678 
//	r = radeon_fence_driver_init(rdev);
 698 
//	r = radeon_fence_driver_init(rdev);
Line 680... Line 700...
680 
//		return r;
 700 
//		return r;
681 
//	r = radeon_irq_kms_init(rdev);
 701 
//	r = radeon_irq_kms_init(rdev);
682 
//	if (r)
 702 
//	if (r)
683 
//		return r;
 703 
//		return r;
684 
	/* Memory manager */
 704 
	/* Memory manager */
685 
	r = radeon_object_init(rdev);
 705 
	r = radeon_bo_init(rdev);
686 
	if (r)
 706 
	if (r)
687 
		return r;
 707 
		return r;
688 
	r = rs400_gart_init(rdev);
 708 
	r = rs400_gart_init(rdev);
689 
	if (r)
 709 
	if (r)
690 
		return r;
 710 
		return r;