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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * |
29 | * |
30 | * This file gather function specific to RS600 which is the IGP of |
30 | * This file gather function specific to RS600 which is the IGP of |
31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
33 | * the avivo one, bios is an atombios, 3D block are the one of the |
33 | * the avivo one, bios is an atombios, 3D block are the one of the |
34 | * R4XX family. The GART is different from the RS400 one and is very |
34 | * R4XX family. The GART is different from the RS400 one and is very |
35 | * close to the one of the R600 family (R600 likely being an evolution |
35 | * close to the one of the R600 family (R600 likely being an evolution |
36 | * of the RS600 GART block). |
36 | * of the RS600 GART block). |
37 | */ |
37 | */ |
38 | #include |
38 | #include |
39 | #include "radeon.h" |
39 | #include "radeon.h" |
40 | #include "radeon_asic.h" |
40 | #include "radeon_asic.h" |
41 | #include "atom.h" |
41 | #include "atom.h" |
42 | #include "rs600d.h" |
42 | #include "rs600d.h" |
43 | 43 | ||
44 | #include "rs600_reg_safe.h" |
44 | #include "rs600_reg_safe.h" |
45 | 45 | ||
46 | static void rs600_gpu_init(struct radeon_device *rdev); |
46 | static void rs600_gpu_init(struct radeon_device *rdev); |
47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
48 | 48 | ||
49 | static const u32 crtc_offsets[2] = |
49 | static const u32 crtc_offsets[2] = |
50 | { |
50 | { |
51 | 0, |
51 | 0, |
52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
53 | }; |
53 | }; |
54 | 54 | ||
55 | static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) |
55 | static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) |
56 | { |
56 | { |
57 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
57 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
58 | return true; |
58 | return true; |
59 | else |
59 | else |
60 | return false; |
60 | return false; |
61 | } |
61 | } |
62 | 62 | ||
63 | static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) |
63 | static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) |
64 | { |
64 | { |
65 | u32 pos1, pos2; |
65 | u32 pos1, pos2; |
66 | 66 | ||
67 | pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
67 | pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
68 | pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
68 | pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
69 | 69 | ||
70 | if (pos1 != pos2) |
70 | if (pos1 != pos2) |
71 | return true; |
71 | return true; |
72 | else |
72 | else |
73 | return false; |
73 | return false; |
74 | } |
74 | } |
75 | 75 | ||
76 | /** |
76 | /** |
77 | * avivo_wait_for_vblank - vblank wait asic callback. |
77 | * avivo_wait_for_vblank - vblank wait asic callback. |
78 | * |
78 | * |
79 | * @rdev: radeon_device pointer |
79 | * @rdev: radeon_device pointer |
80 | * @crtc: crtc to wait for vblank on |
80 | * @crtc: crtc to wait for vblank on |
81 | * |
81 | * |
82 | * Wait for vblank on the requested crtc (r5xx-r7xx). |
82 | * Wait for vblank on the requested crtc (r5xx-r7xx). |
83 | */ |
83 | */ |
84 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
84 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
85 | { |
85 | { |
86 | unsigned i = 0; |
86 | unsigned i = 0; |
87 | 87 | ||
88 | if (crtc >= rdev->num_crtc) |
88 | if (crtc >= rdev->num_crtc) |
89 | return; |
89 | return; |
90 | 90 | ||
91 | if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) |
91 | if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) |
92 | return; |
92 | return; |
93 | 93 | ||
94 | /* depending on when we hit vblank, we may be close to active; if so, |
94 | /* depending on when we hit vblank, we may be close to active; if so, |
95 | * wait for another frame. |
95 | * wait for another frame. |
96 | */ |
96 | */ |
97 | while (avivo_is_in_vblank(rdev, crtc)) { |
97 | while (avivo_is_in_vblank(rdev, crtc)) { |
98 | if (i++ % 100 == 0) { |
98 | if (i++ % 100 == 0) { |
99 | if (!avivo_is_counter_moving(rdev, crtc)) |
99 | if (!avivo_is_counter_moving(rdev, crtc)) |
100 | break; |
100 | break; |
101 | } |
101 | } |
102 | } |
102 | } |
103 | 103 | ||
104 | while (!avivo_is_in_vblank(rdev, crtc)) { |
104 | while (!avivo_is_in_vblank(rdev, crtc)) { |
105 | if (i++ % 100 == 0) { |
105 | if (i++ % 100 == 0) { |
106 | if (!avivo_is_counter_moving(rdev, crtc)) |
106 | if (!avivo_is_counter_moving(rdev, crtc)) |
107 | break; |
107 | break; |
108 | } |
108 | } |
- | 109 | } |
|
- | 110 | } |
|
- | 111 | void avivo_program_fmt(struct drm_encoder *encoder) |
|
- | 112 | { |
|
- | 113 | struct drm_device *dev = encoder->dev; |
|
- | 114 | struct radeon_device *rdev = dev->dev_private; |
|
- | 115 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
- | 116 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
|
- | 117 | int bpc = 0; |
|
- | 118 | u32 tmp = 0; |
|
- | 119 | enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; |
|
- | 120 | ||
- | 121 | if (connector) { |
|
- | 122 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 123 | bpc = radeon_get_monitor_bpc(connector); |
|
- | 124 | dither = radeon_connector->dither; |
|
- | 125 | } |
|
- | 126 | ||
- | 127 | /* LVDS FMT is set up by atom */ |
|
- | 128 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) |
|
- | 129 | return; |
|
- | 130 | ||
- | 131 | if (bpc == 0) |
|
- | 132 | return; |
|
- | 133 | ||
- | 134 | switch (bpc) { |
|
- | 135 | case 6: |
|
- | 136 | if (dither == RADEON_FMT_DITHER_ENABLE) |
|
109 | for (i = 0; i < rdev->usec_timeout; i++) { |
137 | /* XXX sort out optimal dither settings */ |
110 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
138 | tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
- | 139 | else |
|
- | 140 | tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
|
111 | break; |
141 | break; |
- | 142 | case 8: |
|
- | 143 | if (dither == RADEON_FMT_DITHER_ENABLE) |
|
- | 144 | /* XXX sort out optimal dither settings */ |
|
- | 145 | tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN | |
|
- | 146 | AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH); |
|
- | 147 | else |
|
- | 148 | tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN | |
|
- | 149 | AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH); |
|
112 | udelay(1); |
150 | break; |
- | 151 | case 10: |
|
- | 152 | default: |
|
- | 153 | /* not needed */ |
|
- | 154 | break; |
|
- | 155 | } |
|
- | 156 | ||
- | 157 | switch (radeon_encoder->encoder_id) { |
|
- | 158 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
|
- | 159 | WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); |
|
- | 160 | break; |
|
- | 161 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
|
- | 162 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); |
|
- | 163 | break; |
|
- | 164 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
|
- | 165 | WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); |
|
- | 166 | break; |
|
- | 167 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
|
- | 168 | WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); |
|
- | 169 | break; |
|
- | 170 | default: |
|
- | 171 | break; |
|
- | 172 | } |
|
- | 173 | } |
|
- | 174 | ||
- | 175 | void rs600_pm_misc(struct radeon_device *rdev) |
|
- | 176 | { |
|
- | 177 | int requested_index = rdev->pm.requested_power_state_index; |
|
- | 178 | struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; |
|
- | 179 | struct radeon_voltage *voltage = &ps->clock_info[0].voltage; |
|
- | 180 | u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; |
|
- | 181 | u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; |
|
- | 182 | ||
- | 183 | if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { |
|
- | 184 | if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { |
|
- | 185 | tmp = RREG32(voltage->gpio.reg); |
|
- | 186 | if (voltage->active_high) |
|
- | 187 | tmp |= voltage->gpio.mask; |
|
- | 188 | else |
|
- | 189 | tmp &= ~(voltage->gpio.mask); |
|
- | 190 | WREG32(voltage->gpio.reg, tmp); |
|
- | 191 | if (voltage->delay) |
|
- | 192 | udelay(voltage->delay); |
|
- | 193 | } else { |
|
- | 194 | tmp = RREG32(voltage->gpio.reg); |
|
- | 195 | if (voltage->active_high) |
|
- | 196 | tmp &= ~voltage->gpio.mask; |
|
- | 197 | else |
|
- | 198 | tmp |= voltage->gpio.mask; |
|
- | 199 | WREG32(voltage->gpio.reg, tmp); |
|
- | 200 | if (voltage->delay) |
|
- | 201 | udelay(voltage->delay); |
|
- | 202 | } |
|
- | 203 | } else if (voltage->type == VOLTAGE_VDDC) |
|
- | 204 | radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); |
|
- | 205 | ||
- | 206 | dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); |
|
- | 207 | dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); |
|
- | 208 | dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); |
|
- | 209 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { |
|
- | 210 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { |
|
- | 211 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); |
|
- | 212 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); |
|
- | 213 | } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { |
|
- | 214 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); |
|
- | 215 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); |
|
- | 216 | } |
|
- | 217 | } else { |
|
- | 218 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); |
|
- | 219 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); |
|
- | 220 | } |
|
- | 221 | WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); |
|
- | 222 | ||
- | 223 | dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); |
|
- | 224 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { |
|
- | 225 | dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; |
|
- | 226 | if (voltage->delay) { |
|
- | 227 | dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; |
|
- | 228 | dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); |
|
- | 229 | } else |
|
- | 230 | dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; |
|
- | 231 | } else |
|
- | 232 | dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; |
|
- | 233 | WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); |
|
- | 234 | ||
- | 235 | hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); |
|
- | 236 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) |
|
- | 237 | hdp_dyn_cntl &= ~HDP_FORCEON; |
|
- | 238 | else |
|
- | 239 | hdp_dyn_cntl |= HDP_FORCEON; |
|
- | 240 | WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); |
|
- | 241 | #if 0 |
|
- | 242 | /* mc_host_dyn seems to cause hangs from time to time */ |
|
- | 243 | mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); |
|
- | 244 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) |
|
- | 245 | mc_host_dyn_cntl &= ~MC_HOST_FORCEON; |
|
- | 246 | else |
|
- | 247 | mc_host_dyn_cntl |= MC_HOST_FORCEON; |
|
- | 248 | WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); |
|
- | 249 | #endif |
|
- | 250 | dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); |
|
- | 251 | if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) |
|
- | 252 | dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; |
|
- | 253 | else |
|
- | 254 | dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; |
|
- | 255 | WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); |
|
- | 256 | ||
- | 257 | /* set pcie lanes */ |
|
- | 258 | if ((rdev->flags & RADEON_IS_PCIE) && |
|
- | 259 | !(rdev->flags & RADEON_IS_IGP) && |
|
- | 260 | rdev->asic->pm.set_pcie_lanes && |
|
- | 261 | (ps->pcie_lanes != |
|
- | 262 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { |
|
- | 263 | radeon_set_pcie_lanes(rdev, |
|
- | 264 | ps->pcie_lanes); |
|
- | 265 | DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); |
|
- | 266 | } |
|
- | 267 | } |
|
- | 268 | ||
- | 269 | void rs600_pm_prepare(struct radeon_device *rdev) |
|
- | 270 | { |
|
- | 271 | struct drm_device *ddev = rdev->ddev; |
|
- | 272 | struct drm_crtc *crtc; |
|
- | 273 | struct radeon_crtc *radeon_crtc; |
|
- | 274 | u32 tmp; |
|
- | 275 | ||
- | 276 | /* disable any active CRTCs */ |
|
- | 277 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
|
- | 278 | radeon_crtc = to_radeon_crtc(crtc); |
|
- | 279 | if (radeon_crtc->enabled) { |
|
- | 280 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); |
|
- | 281 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
|
- | 282 | WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); |
|
- | 283 | } |
|
- | 284 | } |
|
- | 285 | } |
|
- | 286 | ||
- | 287 | void rs600_pm_finish(struct radeon_device *rdev) |
|
- | 288 | { |
|
- | 289 | struct drm_device *ddev = rdev->ddev; |
|
- | 290 | struct drm_crtc *crtc; |
|
- | 291 | struct radeon_crtc *radeon_crtc; |
|
- | 292 | u32 tmp; |
|
- | 293 | ||
- | 294 | /* enable any active CRTCs */ |
|
- | 295 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
|
- | 296 | radeon_crtc = to_radeon_crtc(crtc); |
|
- | 297 | if (radeon_crtc->enabled) { |
|
- | 298 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); |
|
- | 299 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
|
- | 300 | WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); |
|
113 | } |
301 | } |
114 | } |
302 | } |
115 | } |
303 | } |
- | 304 | ||
116 | /* hpd for digital panel detect/disconnect */ |
305 | /* hpd for digital panel detect/disconnect */ |
117 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
306 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
118 | { |
307 | { |
119 | u32 tmp; |
308 | u32 tmp; |
120 | bool connected = false; |
309 | bool connected = false; |
121 | 310 | ||
122 | switch (hpd) { |
311 | switch (hpd) { |
123 | case RADEON_HPD_1: |
312 | case RADEON_HPD_1: |
124 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
313 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
125 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
314 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
126 | connected = true; |
315 | connected = true; |
127 | break; |
316 | break; |
128 | case RADEON_HPD_2: |
317 | case RADEON_HPD_2: |
129 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
318 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
130 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
319 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
131 | connected = true; |
320 | connected = true; |
132 | break; |
321 | break; |
133 | default: |
322 | default: |
134 | break; |
323 | break; |
135 | } |
324 | } |
136 | return connected; |
325 | return connected; |
137 | } |
326 | } |
138 | 327 | ||
139 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
328 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
140 | enum radeon_hpd_id hpd) |
329 | enum radeon_hpd_id hpd) |
141 | { |
330 | { |
142 | u32 tmp; |
331 | u32 tmp; |
143 | bool connected = rs600_hpd_sense(rdev, hpd); |
332 | bool connected = rs600_hpd_sense(rdev, hpd); |
144 | 333 | ||
145 | switch (hpd) { |
334 | switch (hpd) { |
146 | case RADEON_HPD_1: |
335 | case RADEON_HPD_1: |
147 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
336 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
148 | if (connected) |
337 | if (connected) |
149 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
338 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
150 | else |
339 | else |
151 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
340 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
152 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
341 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
153 | break; |
342 | break; |
154 | case RADEON_HPD_2: |
343 | case RADEON_HPD_2: |
155 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
344 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
156 | if (connected) |
345 | if (connected) |
157 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
346 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
158 | else |
347 | else |
159 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
348 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
160 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
349 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
161 | break; |
350 | break; |
162 | default: |
351 | default: |
163 | break; |
352 | break; |
164 | } |
353 | } |
165 | } |
354 | } |
166 | 355 | ||
167 | void rs600_hpd_init(struct radeon_device *rdev) |
356 | void rs600_hpd_init(struct radeon_device *rdev) |
168 | { |
357 | { |
169 | struct drm_device *dev = rdev->ddev; |
358 | struct drm_device *dev = rdev->ddev; |
170 | struct drm_connector *connector; |
359 | struct drm_connector *connector; |
171 | unsigned enable = 0; |
360 | unsigned enable = 0; |
172 | 361 | ||
173 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
362 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
174 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
363 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
175 | switch (radeon_connector->hpd.hpd) { |
364 | switch (radeon_connector->hpd.hpd) { |
176 | case RADEON_HPD_1: |
365 | case RADEON_HPD_1: |
177 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
366 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
178 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
367 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
179 | break; |
368 | break; |
180 | case RADEON_HPD_2: |
369 | case RADEON_HPD_2: |
181 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
370 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
182 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
371 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
183 | break; |
372 | break; |
184 | default: |
373 | default: |
185 | break; |
374 | break; |
186 | } |
375 | } |
187 | enable |= 1 << radeon_connector->hpd.hpd; |
376 | enable |= 1 << radeon_connector->hpd.hpd; |
188 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
377 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
189 | } |
378 | } |
190 | // radeon_irq_kms_enable_hpd(rdev, enable); |
379 | // radeon_irq_kms_enable_hpd(rdev, enable); |
191 | } |
380 | } |
192 | 381 | ||
193 | void rs600_hpd_fini(struct radeon_device *rdev) |
382 | void rs600_hpd_fini(struct radeon_device *rdev) |
194 | { |
383 | { |
195 | struct drm_device *dev = rdev->ddev; |
384 | struct drm_device *dev = rdev->ddev; |
196 | struct drm_connector *connector; |
385 | struct drm_connector *connector; |
197 | unsigned disable = 0; |
386 | unsigned disable = 0; |
198 | 387 | ||
199 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
388 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
200 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
389 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
201 | switch (radeon_connector->hpd.hpd) { |
390 | switch (radeon_connector->hpd.hpd) { |
202 | case RADEON_HPD_1: |
391 | case RADEON_HPD_1: |
203 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
392 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
204 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
393 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
205 | break; |
394 | break; |
206 | case RADEON_HPD_2: |
395 | case RADEON_HPD_2: |
207 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
396 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
208 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
397 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
209 | break; |
398 | break; |
210 | default: |
399 | default: |
211 | break; |
400 | break; |
212 | } |
401 | } |
213 | disable |= 1 << radeon_connector->hpd.hpd; |
402 | disable |= 1 << radeon_connector->hpd.hpd; |
214 | } |
403 | } |
215 | // radeon_irq_kms_disable_hpd(rdev, disable); |
404 | // radeon_irq_kms_disable_hpd(rdev, disable); |
216 | } |
405 | } |
217 | 406 | ||
218 | int rs600_asic_reset(struct radeon_device *rdev) |
407 | int rs600_asic_reset(struct radeon_device *rdev) |
219 | { |
408 | { |
220 | struct rv515_mc_save save; |
409 | struct rv515_mc_save save; |
221 | u32 status, tmp; |
410 | u32 status, tmp; |
222 | int ret = 0; |
411 | int ret = 0; |
223 | 412 | ||
224 | status = RREG32(R_000E40_RBBM_STATUS); |
413 | status = RREG32(R_000E40_RBBM_STATUS); |
225 | if (!G_000E40_GUI_ACTIVE(status)) { |
414 | if (!G_000E40_GUI_ACTIVE(status)) { |
226 | return 0; |
415 | return 0; |
227 | } |
416 | } |
228 | /* Stops all mc clients */ |
417 | /* Stops all mc clients */ |
229 | rv515_mc_stop(rdev, &save); |
418 | rv515_mc_stop(rdev, &save); |
230 | status = RREG32(R_000E40_RBBM_STATUS); |
419 | status = RREG32(R_000E40_RBBM_STATUS); |
231 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
420 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
232 | /* stop CP */ |
421 | /* stop CP */ |
233 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
422 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
234 | tmp = RREG32(RADEON_CP_RB_CNTL); |
423 | tmp = RREG32(RADEON_CP_RB_CNTL); |
235 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
424 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
236 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
425 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
237 | WREG32(RADEON_CP_RB_WPTR, 0); |
426 | WREG32(RADEON_CP_RB_WPTR, 0); |
238 | WREG32(RADEON_CP_RB_CNTL, tmp); |
427 | WREG32(RADEON_CP_RB_CNTL, tmp); |
239 | // pci_save_state(rdev->pdev); |
428 | // pci_save_state(rdev->pdev); |
240 | /* disable bus mastering */ |
429 | /* disable bus mastering */ |
241 | // pci_clear_master(rdev->pdev); |
430 | // pci_clear_master(rdev->pdev); |
242 | mdelay(1); |
431 | mdelay(1); |
243 | /* reset GA+VAP */ |
432 | /* reset GA+VAP */ |
244 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
433 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
245 | S_0000F0_SOFT_RESET_GA(1)); |
434 | S_0000F0_SOFT_RESET_GA(1)); |
246 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
435 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
247 | mdelay(500); |
436 | mdelay(500); |
248 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
437 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
249 | mdelay(1); |
438 | mdelay(1); |
250 | status = RREG32(R_000E40_RBBM_STATUS); |
439 | status = RREG32(R_000E40_RBBM_STATUS); |
251 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
440 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
252 | /* reset CP */ |
441 | /* reset CP */ |
253 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
442 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
254 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
443 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
255 | mdelay(500); |
444 | mdelay(500); |
256 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
445 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
257 | mdelay(1); |
446 | mdelay(1); |
258 | status = RREG32(R_000E40_RBBM_STATUS); |
447 | status = RREG32(R_000E40_RBBM_STATUS); |
259 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
448 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
260 | /* reset MC */ |
449 | /* reset MC */ |
261 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); |
450 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); |
262 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
451 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
263 | mdelay(500); |
452 | mdelay(500); |
264 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
453 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
265 | mdelay(1); |
454 | mdelay(1); |
266 | status = RREG32(R_000E40_RBBM_STATUS); |
455 | status = RREG32(R_000E40_RBBM_STATUS); |
267 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
456 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
268 | /* restore PCI & busmastering */ |
457 | /* restore PCI & busmastering */ |
269 | // pci_restore_state(rdev->pdev); |
458 | // pci_restore_state(rdev->pdev); |
270 | /* Check if GPU is idle */ |
459 | /* Check if GPU is idle */ |
271 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
460 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
272 | dev_err(rdev->dev, "failed to reset GPU\n"); |
461 | dev_err(rdev->dev, "failed to reset GPU\n"); |
273 | ret = -1; |
462 | ret = -1; |
274 | } else |
463 | } else |
275 | dev_info(rdev->dev, "GPU reset succeed\n"); |
464 | dev_info(rdev->dev, "GPU reset succeed\n"); |
276 | rv515_mc_resume(rdev, &save); |
465 | rv515_mc_resume(rdev, &save); |
277 | return ret; |
466 | return ret; |
278 | } |
467 | } |
279 | 468 | ||
280 | /* |
469 | /* |
281 | * GART. |
470 | * GART. |
282 | */ |
471 | */ |
283 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
472 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
284 | { |
473 | { |
285 | uint32_t tmp; |
474 | uint32_t tmp; |
286 | 475 | ||
287 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
476 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
288 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
477 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
289 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
478 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
290 | 479 | ||
291 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
480 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
292 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
481 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
293 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
482 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
294 | 483 | ||
295 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
484 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
296 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
485 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
297 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
486 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
298 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
487 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
299 | } |
488 | } |
300 | 489 | ||
301 | static int rs600_gart_init(struct radeon_device *rdev) |
490 | static int rs600_gart_init(struct radeon_device *rdev) |
302 | { |
491 | { |
303 | int r; |
492 | int r; |
304 | 493 | ||
305 | if (rdev->gart.robj) { |
494 | if (rdev->gart.robj) { |
306 | WARN(1, "RS600 GART already initialized\n"); |
495 | WARN(1, "RS600 GART already initialized\n"); |
307 | return 0; |
496 | return 0; |
308 | } |
497 | } |
309 | /* Initialize common gart structure */ |
498 | /* Initialize common gart structure */ |
310 | r = radeon_gart_init(rdev); |
499 | r = radeon_gart_init(rdev); |
311 | if (r) { |
500 | if (r) { |
312 | return r; |
501 | return r; |
313 | } |
502 | } |
314 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
503 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
315 | return radeon_gart_table_vram_alloc(rdev); |
504 | return radeon_gart_table_vram_alloc(rdev); |
316 | } |
505 | } |
317 | 506 | ||
318 | static int rs600_gart_enable(struct radeon_device *rdev) |
507 | static int rs600_gart_enable(struct radeon_device *rdev) |
319 | { |
508 | { |
320 | u32 tmp; |
509 | u32 tmp; |
321 | int r, i; |
510 | int r, i; |
322 | 511 | ||
323 | if (rdev->gart.robj == NULL) { |
512 | if (rdev->gart.robj == NULL) { |
324 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
513 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
325 | return -EINVAL; |
514 | return -EINVAL; |
326 | } |
515 | } |
327 | r = radeon_gart_table_vram_pin(rdev); |
516 | r = radeon_gart_table_vram_pin(rdev); |
328 | if (r) |
517 | if (r) |
329 | return r; |
518 | return r; |
330 | radeon_gart_restore(rdev); |
- | |
331 | /* Enable bus master */ |
519 | /* Enable bus master */ |
332 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
520 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
333 | WREG32(RADEON_BUS_CNTL, tmp); |
521 | WREG32(RADEON_BUS_CNTL, tmp); |
334 | /* FIXME: setup default page */ |
522 | /* FIXME: setup default page */ |
335 | WREG32_MC(R_000100_MC_PT0_CNTL, |
523 | WREG32_MC(R_000100_MC_PT0_CNTL, |
336 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
524 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
337 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
525 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
338 | 526 | ||
339 | for (i = 0; i < 19; i++) { |
527 | for (i = 0; i < 19; i++) { |
340 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
528 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
341 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
529 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
342 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
530 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
343 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
531 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
344 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
532 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
345 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
533 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
346 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
534 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
347 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
535 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
348 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
536 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
349 | } |
537 | } |
350 | /* enable first context */ |
538 | /* enable first context */ |
351 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
539 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
352 | S_000102_ENABLE_PAGE_TABLE(1) | |
540 | S_000102_ENABLE_PAGE_TABLE(1) | |
353 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
541 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
354 | 542 | ||
355 | /* disable all other contexts */ |
543 | /* disable all other contexts */ |
356 | for (i = 1; i < 8; i++) |
544 | for (i = 1; i < 8; i++) |
357 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
545 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
358 | 546 | ||
359 | /* setup the page table */ |
547 | /* setup the page table */ |
360 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
548 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
361 | rdev->gart.table_addr); |
549 | rdev->gart.table_addr); |
362 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
550 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
363 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
551 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
364 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
552 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
365 | 553 | ||
366 | /* System context maps to VRAM space */ |
554 | /* System context maps to VRAM space */ |
367 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
555 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
368 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
556 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
369 | 557 | ||
370 | /* enable page tables */ |
558 | /* enable page tables */ |
371 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
559 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
372 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
560 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
373 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
561 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
374 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
562 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
375 | rs600_gart_tlb_flush(rdev); |
563 | rs600_gart_tlb_flush(rdev); |
376 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
564 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
377 | (unsigned)(rdev->mc.gtt_size >> 20), |
565 | (unsigned)(rdev->mc.gtt_size >> 20), |
378 | (unsigned long long)rdev->gart.table_addr); |
566 | (unsigned long long)rdev->gart.table_addr); |
379 | rdev->gart.ready = true; |
567 | rdev->gart.ready = true; |
380 | return 0; |
568 | return 0; |
381 | } |
569 | } |
382 | 570 | ||
383 | static void rs600_gart_disable(struct radeon_device *rdev) |
571 | static void rs600_gart_disable(struct radeon_device *rdev) |
384 | { |
572 | { |
385 | u32 tmp; |
573 | u32 tmp; |
386 | 574 | ||
387 | /* FIXME: disable out of gart access */ |
575 | /* FIXME: disable out of gart access */ |
388 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
576 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
389 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
577 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
390 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
578 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
391 | radeon_gart_table_vram_unpin(rdev); |
579 | radeon_gart_table_vram_unpin(rdev); |
392 | } |
580 | } |
393 | 581 | ||
394 | static void rs600_gart_fini(struct radeon_device *rdev) |
582 | static void rs600_gart_fini(struct radeon_device *rdev) |
395 | { |
583 | { |
396 | radeon_gart_fini(rdev); |
584 | radeon_gart_fini(rdev); |
397 | rs600_gart_disable(rdev); |
585 | rs600_gart_disable(rdev); |
398 | radeon_gart_table_vram_free(rdev); |
586 | radeon_gart_table_vram_free(rdev); |
399 | } |
587 | } |
400 | - | ||
401 | #define R600_PTE_VALID (1 << 0) |
- | |
402 | #define R600_PTE_SYSTEM (1 << 1) |
- | |
403 | #define R600_PTE_SNOOPED (1 << 2) |
- | |
404 | #define R600_PTE_READABLE (1 << 5) |
- | |
405 | #define R600_PTE_WRITEABLE (1 << 6) |
- | |
406 | 588 | ||
- | 589 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, |
|
407 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
590 | uint64_t addr, uint32_t flags) |
408 | { |
591 | { |
409 | void __iomem *ptr = (void *)rdev->gart.ptr; |
592 | void __iomem *ptr = (void *)rdev->gart.ptr; |
410 | - | ||
411 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
- | |
412 | return -EINVAL; |
- | |
413 | } |
593 | |
414 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
594 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
- | 595 | addr |= R600_PTE_SYSTEM; |
|
- | 596 | if (flags & RADEON_GART_PAGE_VALID) |
|
- | 597 | addr |= R600_PTE_VALID; |
|
- | 598 | if (flags & RADEON_GART_PAGE_READ) |
|
- | 599 | addr |= R600_PTE_READABLE; |
|
415 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
600 | if (flags & RADEON_GART_PAGE_WRITE) |
- | 601 | addr |= R600_PTE_WRITEABLE; |
|
- | 602 | if (flags & RADEON_GART_PAGE_SNOOP) |
|
416 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
603 | addr |= R600_PTE_SNOOPED; |
417 | writeq(addr, ptr + (i * 8)); |
- | |
418 | return 0; |
604 | writeq(addr, ptr + (i * 8)); |
419 | } |
605 | } |
420 | 606 | ||
421 | int rs600_irq_set(struct radeon_device *rdev) |
607 | int rs600_irq_set(struct radeon_device *rdev) |
422 | { |
608 | { |
423 | uint32_t tmp = 0; |
609 | uint32_t tmp = 0; |
424 | uint32_t mode_int = 0; |
610 | uint32_t mode_int = 0; |
425 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
611 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
426 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
612 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
427 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
613 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
428 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
614 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
429 | u32 hdmi0; |
615 | u32 hdmi0; |
430 | if (ASIC_IS_DCE2(rdev)) |
616 | if (ASIC_IS_DCE2(rdev)) |
431 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
617 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
432 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
618 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
433 | else |
619 | else |
434 | hdmi0 = 0; |
620 | hdmi0 = 0; |
435 | 621 | ||
436 | if (!rdev->irq.installed) { |
622 | if (!rdev->irq.installed) { |
437 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
623 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
438 | WREG32(R_000040_GEN_INT_CNTL, 0); |
624 | WREG32(R_000040_GEN_INT_CNTL, 0); |
439 | return -EINVAL; |
625 | return -EINVAL; |
440 | } |
626 | } |
441 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
627 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
442 | tmp |= S_000040_SW_INT_EN(1); |
628 | tmp |= S_000040_SW_INT_EN(1); |
443 | } |
629 | } |
444 | if (rdev->irq.crtc_vblank_int[0] || |
630 | if (rdev->irq.crtc_vblank_int[0] || |
445 | atomic_read(&rdev->irq.pflip[0])) { |
631 | atomic_read(&rdev->irq.pflip[0])) { |
446 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
632 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
447 | } |
633 | } |
448 | if (rdev->irq.crtc_vblank_int[1] || |
634 | if (rdev->irq.crtc_vblank_int[1] || |
449 | atomic_read(&rdev->irq.pflip[1])) { |
635 | atomic_read(&rdev->irq.pflip[1])) { |
450 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
636 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
451 | } |
637 | } |
452 | if (rdev->irq.hpd[0]) { |
638 | if (rdev->irq.hpd[0]) { |
453 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
639 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
454 | } |
640 | } |
455 | if (rdev->irq.hpd[1]) { |
641 | if (rdev->irq.hpd[1]) { |
456 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
642 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
457 | } |
643 | } |
458 | if (rdev->irq.afmt[0]) { |
644 | if (rdev->irq.afmt[0]) { |
459 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
645 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
460 | } |
646 | } |
461 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
647 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
462 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
648 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
463 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
649 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
464 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
650 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
465 | if (ASIC_IS_DCE2(rdev)) |
651 | if (ASIC_IS_DCE2(rdev)) |
466 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
652 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
467 | return 0; |
653 | return 0; |
468 | } |
654 | } |
469 | 655 | ||
470 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
656 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
471 | { |
657 | { |
472 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
658 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
473 | uint32_t irq_mask = S_000044_SW_INT(1); |
659 | uint32_t irq_mask = S_000044_SW_INT(1); |
474 | u32 tmp; |
660 | u32 tmp; |
475 | 661 | ||
476 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
662 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
477 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
663 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
478 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
664 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
479 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
665 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
480 | S_006534_D1MODE_VBLANK_ACK(1)); |
666 | S_006534_D1MODE_VBLANK_ACK(1)); |
481 | } |
667 | } |
482 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
668 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
483 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
669 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
484 | S_006D34_D2MODE_VBLANK_ACK(1)); |
670 | S_006D34_D2MODE_VBLANK_ACK(1)); |
485 | } |
671 | } |
486 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
672 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
487 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
673 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
488 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
674 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
489 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
675 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
490 | } |
676 | } |
491 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
677 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
492 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
678 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
493 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
679 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
494 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
680 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
495 | } |
681 | } |
496 | } else { |
682 | } else { |
497 | rdev->irq.stat_regs.r500.disp_int = 0; |
683 | rdev->irq.stat_regs.r500.disp_int = 0; |
498 | } |
684 | } |
499 | 685 | ||
500 | if (ASIC_IS_DCE2(rdev)) { |
686 | if (ASIC_IS_DCE2(rdev)) { |
501 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & |
687 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & |
502 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); |
688 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); |
503 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
689 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
504 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); |
690 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); |
505 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); |
691 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); |
506 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); |
692 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); |
507 | } |
693 | } |
508 | } else |
694 | } else |
509 | rdev->irq.stat_regs.r500.hdmi0_status = 0; |
695 | rdev->irq.stat_regs.r500.hdmi0_status = 0; |
510 | 696 | ||
511 | if (irqs) { |
697 | if (irqs) { |
512 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
698 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
513 | } |
699 | } |
514 | return irqs & irq_mask; |
700 | return irqs & irq_mask; |
515 | } |
701 | } |
516 | 702 | ||
517 | void rs600_irq_disable(struct radeon_device *rdev) |
703 | void rs600_irq_disable(struct radeon_device *rdev) |
518 | { |
704 | { |
519 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
705 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
520 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
706 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
521 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
707 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
522 | WREG32(R_000040_GEN_INT_CNTL, 0); |
708 | WREG32(R_000040_GEN_INT_CNTL, 0); |
523 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
709 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
524 | /* Wait and acknowledge irq */ |
710 | /* Wait and acknowledge irq */ |
525 | mdelay(1); |
711 | mdelay(1); |
526 | rs600_irq_ack(rdev); |
712 | rs600_irq_ack(rdev); |
527 | } |
713 | } |
528 | 714 | ||
529 | int rs600_irq_process(struct radeon_device *rdev) |
715 | int rs600_irq_process(struct radeon_device *rdev) |
530 | { |
716 | { |
531 | u32 status, msi_rearm; |
717 | u32 status, msi_rearm; |
532 | bool queue_hotplug = false; |
718 | bool queue_hotplug = false; |
533 | bool queue_hdmi = false; |
719 | bool queue_hdmi = false; |
534 | 720 | ||
535 | status = rs600_irq_ack(rdev); |
721 | status = rs600_irq_ack(rdev); |
536 | if (!status && |
722 | if (!status && |
537 | !rdev->irq.stat_regs.r500.disp_int && |
723 | !rdev->irq.stat_regs.r500.disp_int && |
538 | !rdev->irq.stat_regs.r500.hdmi0_status) { |
724 | !rdev->irq.stat_regs.r500.hdmi0_status) { |
539 | return IRQ_NONE; |
725 | return IRQ_NONE; |
540 | } |
726 | } |
541 | while (status || |
727 | while (status || |
542 | rdev->irq.stat_regs.r500.disp_int || |
728 | rdev->irq.stat_regs.r500.disp_int || |
543 | rdev->irq.stat_regs.r500.hdmi0_status) { |
729 | rdev->irq.stat_regs.r500.hdmi0_status) { |
544 | /* SW interrupt */ |
730 | /* SW interrupt */ |
545 | if (G_000044_SW_INT(status)) { |
731 | if (G_000044_SW_INT(status)) { |
546 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
732 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
547 | } |
733 | } |
548 | /* Vertical blank interrupts */ |
734 | /* Vertical blank interrupts */ |
549 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
735 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
550 | if (rdev->irq.crtc_vblank_int[0]) { |
736 | if (rdev->irq.crtc_vblank_int[0]) { |
551 | // drm_handle_vblank(rdev->ddev, 0); |
737 | // drm_handle_vblank(rdev->ddev, 0); |
552 | rdev->pm.vblank_sync = true; |
738 | rdev->pm.vblank_sync = true; |
553 | // wake_up(&rdev->irq.vblank_queue); |
739 | // wake_up(&rdev->irq.vblank_queue); |
554 | } |
740 | } |
555 | // if (rdev->irq.pflip[0]) |
741 | // if (rdev->irq.pflip[0]) |
556 | // radeon_crtc_handle_flip(rdev, 0); |
742 | // radeon_crtc_handle_flip(rdev, 0); |
557 | } |
743 | } |
558 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
744 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
559 | if (rdev->irq.crtc_vblank_int[1]) { |
745 | if (rdev->irq.crtc_vblank_int[1]) { |
560 | // drm_handle_vblank(rdev->ddev, 1); |
746 | // drm_handle_vblank(rdev->ddev, 1); |
561 | rdev->pm.vblank_sync = true; |
747 | rdev->pm.vblank_sync = true; |
562 | // wake_up(&rdev->irq.vblank_queue); |
748 | // wake_up(&rdev->irq.vblank_queue); |
563 | } |
749 | } |
564 | // if (rdev->irq.pflip[1]) |
750 | // if (rdev->irq.pflip[1]) |
565 | // radeon_crtc_handle_flip(rdev, 1); |
751 | // radeon_crtc_handle_flip(rdev, 1); |
566 | } |
752 | } |
567 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
753 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
568 | queue_hotplug = true; |
754 | queue_hotplug = true; |
569 | DRM_DEBUG("HPD1\n"); |
755 | DRM_DEBUG("HPD1\n"); |
570 | } |
756 | } |
571 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
757 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
572 | queue_hotplug = true; |
758 | queue_hotplug = true; |
573 | DRM_DEBUG("HPD2\n"); |
759 | DRM_DEBUG("HPD2\n"); |
574 | } |
760 | } |
575 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
761 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
576 | queue_hdmi = true; |
762 | queue_hdmi = true; |
577 | DRM_DEBUG("HDMI0\n"); |
763 | DRM_DEBUG("HDMI0\n"); |
578 | } |
764 | } |
579 | status = rs600_irq_ack(rdev); |
765 | status = rs600_irq_ack(rdev); |
580 | } |
766 | } |
581 | // if (queue_hotplug) |
767 | // if (queue_hotplug) |
582 | // schedule_work(&rdev->hotplug_work); |
768 | // schedule_work(&rdev->hotplug_work); |
583 | // if (queue_hdmi) |
769 | // if (queue_hdmi) |
584 | // schedule_work(&rdev->audio_work); |
770 | // schedule_work(&rdev->audio_work); |
585 | if (rdev->msi_enabled) { |
771 | if (rdev->msi_enabled) { |
586 | switch (rdev->family) { |
772 | switch (rdev->family) { |
587 | case CHIP_RS600: |
773 | case CHIP_RS600: |
588 | case CHIP_RS690: |
774 | case CHIP_RS690: |
589 | case CHIP_RS740: |
775 | case CHIP_RS740: |
590 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
776 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
591 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
777 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
592 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
778 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
593 | break; |
779 | break; |
594 | default: |
780 | default: |
595 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
781 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
596 | break; |
782 | break; |
597 | } |
783 | } |
598 | } |
784 | } |
599 | return IRQ_HANDLED; |
785 | return IRQ_HANDLED; |
600 | } |
786 | } |
601 | 787 | ||
602 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
788 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
603 | { |
789 | { |
604 | if (crtc == 0) |
790 | if (crtc == 0) |
605 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
791 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
606 | else |
792 | else |
607 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
793 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
608 | } |
794 | } |
609 | 795 | ||
610 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
796 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
611 | { |
797 | { |
612 | unsigned i; |
798 | unsigned i; |
613 | 799 | ||
614 | for (i = 0; i < rdev->usec_timeout; i++) { |
800 | for (i = 0; i < rdev->usec_timeout; i++) { |
615 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
801 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
616 | return 0; |
802 | return 0; |
617 | udelay(1); |
803 | udelay(1); |
618 | } |
804 | } |
619 | return -1; |
805 | return -1; |
620 | } |
806 | } |
621 | 807 | ||
622 | static void rs600_gpu_init(struct radeon_device *rdev) |
808 | static void rs600_gpu_init(struct radeon_device *rdev) |
623 | { |
809 | { |
624 | r420_pipes_init(rdev); |
810 | r420_pipes_init(rdev); |
625 | /* Wait for mc idle */ |
811 | /* Wait for mc idle */ |
626 | if (rs600_mc_wait_for_idle(rdev)) |
812 | if (rs600_mc_wait_for_idle(rdev)) |
627 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
813 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
628 | } |
814 | } |
629 | 815 | ||
630 | static void rs600_mc_init(struct radeon_device *rdev) |
816 | static void rs600_mc_init(struct radeon_device *rdev) |
631 | { |
817 | { |
632 | u64 base; |
818 | u64 base; |
633 | 819 | ||
634 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
820 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
635 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
821 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
636 | rdev->mc.vram_is_ddr = true; |
822 | rdev->mc.vram_is_ddr = true; |
637 | rdev->mc.vram_width = 128; |
823 | rdev->mc.vram_width = 128; |
638 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
824 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
639 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
825 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
640 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
826 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
641 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
827 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
642 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
828 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
643 | base = G_000004_MC_FB_START(base) << 16; |
829 | base = G_000004_MC_FB_START(base) << 16; |
644 | radeon_vram_location(rdev, &rdev->mc, base); |
830 | radeon_vram_location(rdev, &rdev->mc, base); |
645 | rdev->mc.gtt_base_align = 0; |
831 | rdev->mc.gtt_base_align = 0; |
646 | radeon_gtt_location(rdev, &rdev->mc); |
832 | radeon_gtt_location(rdev, &rdev->mc); |
647 | radeon_update_bandwidth_info(rdev); |
833 | radeon_update_bandwidth_info(rdev); |
648 | } |
834 | } |
649 | 835 | ||
650 | void rs600_bandwidth_update(struct radeon_device *rdev) |
836 | void rs600_bandwidth_update(struct radeon_device *rdev) |
651 | { |
837 | { |
652 | struct drm_display_mode *mode0 = NULL; |
838 | struct drm_display_mode *mode0 = NULL; |
653 | struct drm_display_mode *mode1 = NULL; |
839 | struct drm_display_mode *mode1 = NULL; |
654 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
840 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
655 | /* FIXME: implement full support */ |
841 | /* FIXME: implement full support */ |
656 | 842 | ||
657 | radeon_update_display_priority(rdev); |
843 | radeon_update_display_priority(rdev); |
658 | 844 | ||
659 | if (rdev->mode_info.crtcs[0]->base.enabled) |
845 | if (rdev->mode_info.crtcs[0]->base.enabled) |
660 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
846 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
661 | if (rdev->mode_info.crtcs[1]->base.enabled) |
847 | if (rdev->mode_info.crtcs[1]->base.enabled) |
662 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
848 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
663 | 849 | ||
664 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
850 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
665 | 851 | ||
666 | if (rdev->disp_priority == 2) { |
852 | if (rdev->disp_priority == 2) { |
667 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
853 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
668 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
854 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
669 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
855 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
670 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
856 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
671 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
857 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
672 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
858 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
673 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
859 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
674 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
860 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
675 | } |
861 | } |
676 | } |
862 | } |
677 | 863 | ||
678 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
864 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
679 | { |
865 | { |
- | 866 | unsigned long flags; |
|
- | 867 | u32 r; |
|
- | 868 | ||
- | 869 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
|
680 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
870 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
681 | S_000070_MC_IND_CITF_ARB0(1)); |
871 | S_000070_MC_IND_CITF_ARB0(1)); |
682 | return RREG32(R_000074_MC_IND_DATA); |
872 | r = RREG32(R_000074_MC_IND_DATA); |
- | 873 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
|
- | 874 | return r; |
|
683 | } |
875 | } |
684 | 876 | ||
685 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
877 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
686 | { |
878 | { |
- | 879 | unsigned long flags; |
|
- | 880 | ||
- | 881 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
|
687 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
882 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
688 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
883 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
689 | WREG32(R_000074_MC_IND_DATA, v); |
884 | WREG32(R_000074_MC_IND_DATA, v); |
- | 885 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
|
690 | } |
886 | } |
691 | 887 | ||
692 | static void rs600_debugfs(struct radeon_device *rdev) |
888 | static void rs600_debugfs(struct radeon_device *rdev) |
693 | { |
889 | { |
694 | if (r100_debugfs_rbbm_init(rdev)) |
890 | if (r100_debugfs_rbbm_init(rdev)) |
695 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
891 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
696 | } |
892 | } |
697 | 893 | ||
698 | void rs600_set_safe_registers(struct radeon_device *rdev) |
894 | void rs600_set_safe_registers(struct radeon_device *rdev) |
699 | { |
895 | { |
700 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
896 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
701 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
897 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
702 | } |
898 | } |
703 | 899 | ||
704 | static void rs600_mc_program(struct radeon_device *rdev) |
900 | static void rs600_mc_program(struct radeon_device *rdev) |
705 | { |
901 | { |
706 | struct rv515_mc_save save; |
902 | struct rv515_mc_save save; |
707 | 903 | ||
708 | /* Stops all mc clients */ |
904 | /* Stops all mc clients */ |
709 | rv515_mc_stop(rdev, &save); |
905 | rv515_mc_stop(rdev, &save); |
710 | 906 | ||
711 | /* Wait for mc idle */ |
907 | /* Wait for mc idle */ |
712 | if (rs600_mc_wait_for_idle(rdev)) |
908 | if (rs600_mc_wait_for_idle(rdev)) |
713 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
909 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
714 | 910 | ||
715 | /* FIXME: What does AGP means for such chipset ? */ |
911 | /* FIXME: What does AGP means for such chipset ? */ |
716 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
912 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
717 | WREG32_MC(R_000006_AGP_BASE, 0); |
913 | WREG32_MC(R_000006_AGP_BASE, 0); |
718 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
914 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
719 | /* Program MC */ |
915 | /* Program MC */ |
720 | WREG32_MC(R_000004_MC_FB_LOCATION, |
916 | WREG32_MC(R_000004_MC_FB_LOCATION, |
721 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
917 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
722 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
918 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
723 | WREG32(R_000134_HDP_FB_LOCATION, |
919 | WREG32(R_000134_HDP_FB_LOCATION, |
724 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
920 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
725 | 921 | ||
726 | rv515_mc_resume(rdev, &save); |
922 | rv515_mc_resume(rdev, &save); |
727 | } |
923 | } |
728 | 924 | ||
729 | static int rs600_startup(struct radeon_device *rdev) |
925 | static int rs600_startup(struct radeon_device *rdev) |
730 | { |
926 | { |
731 | int r; |
927 | int r; |
732 | 928 | ||
733 | rs600_mc_program(rdev); |
929 | rs600_mc_program(rdev); |
734 | /* Resume clock */ |
930 | /* Resume clock */ |
735 | rv515_clock_startup(rdev); |
931 | rv515_clock_startup(rdev); |
736 | /* Initialize GPU configuration (# pipes, ...) */ |
932 | /* Initialize GPU configuration (# pipes, ...) */ |
737 | rs600_gpu_init(rdev); |
933 | rs600_gpu_init(rdev); |
738 | /* Initialize GART (initialize after TTM so we can allocate |
934 | /* Initialize GART (initialize after TTM so we can allocate |
739 | * memory through TTM but finalize after TTM) */ |
935 | * memory through TTM but finalize after TTM) */ |
740 | r = rs600_gart_enable(rdev); |
936 | r = rs600_gart_enable(rdev); |
741 | if (r) |
937 | if (r) |
742 | return r; |
938 | return r; |
743 | 939 | ||
744 | /* allocate wb buffer */ |
940 | /* allocate wb buffer */ |
745 | r = radeon_wb_init(rdev); |
941 | r = radeon_wb_init(rdev); |
746 | if (r) |
942 | if (r) |
747 | return r; |
943 | return r; |
748 | 944 | ||
749 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
945 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
750 | if (r) { |
946 | if (r) { |
751 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
947 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
752 | return r; |
948 | return r; |
753 | } |
949 | } |
754 | 950 | ||
755 | /* Enable IRQ */ |
951 | /* Enable IRQ */ |
756 | if (!rdev->irq.installed) { |
952 | if (!rdev->irq.installed) { |
757 | r = radeon_irq_kms_init(rdev); |
953 | r = radeon_irq_kms_init(rdev); |
758 | if (r) |
954 | if (r) |
759 | return r; |
955 | return r; |
760 | } |
956 | } |
761 | 957 | ||
762 | rs600_irq_set(rdev); |
958 | rs600_irq_set(rdev); |
763 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
959 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
764 | /* 1M ring buffer */ |
960 | /* 1M ring buffer */ |
765 | r = r100_cp_init(rdev, 1024 * 1024); |
961 | r = r100_cp_init(rdev, 1024 * 1024); |
766 | if (r) { |
962 | if (r) { |
767 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
963 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
768 | return r; |
964 | return r; |
769 | } |
965 | } |
770 | 966 | ||
771 | r = radeon_ib_pool_init(rdev); |
967 | r = radeon_ib_pool_init(rdev); |
772 | if (r) { |
968 | if (r) { |
773 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
969 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
774 | return r; |
970 | return r; |
775 | } |
971 | } |
- | 972 | ||
- | 973 | r = r600_audio_init(rdev); |
|
- | 974 | if (r) { |
|
- | 975 | dev_err(rdev->dev, "failed initializing audio\n"); |
|
- | 976 | return r; |
|
776 | 977 | } |
|
777 | 978 | ||
778 | return 0; |
979 | return 0; |
779 | } |
980 | } |
780 | 981 | ||
781 | 982 | ||
782 | 983 | ||
783 | int rs600_init(struct radeon_device *rdev) |
984 | int rs600_init(struct radeon_device *rdev) |
784 | { |
985 | { |
785 | int r; |
986 | int r; |
786 | 987 | ||
787 | /* Disable VGA */ |
988 | /* Disable VGA */ |
788 | rv515_vga_render_disable(rdev); |
989 | rv515_vga_render_disable(rdev); |
789 | /* Initialize scratch registers */ |
990 | /* Initialize scratch registers */ |
790 | radeon_scratch_init(rdev); |
991 | radeon_scratch_init(rdev); |
791 | /* Initialize surface registers */ |
992 | /* Initialize surface registers */ |
792 | radeon_surface_init(rdev); |
993 | radeon_surface_init(rdev); |
793 | /* restore some register to sane defaults */ |
994 | /* restore some register to sane defaults */ |
794 | r100_restore_sanity(rdev); |
995 | r100_restore_sanity(rdev); |
795 | /* BIOS */ |
996 | /* BIOS */ |
796 | if (!radeon_get_bios(rdev)) { |
997 | if (!radeon_get_bios(rdev)) { |
797 | if (ASIC_IS_AVIVO(rdev)) |
998 | if (ASIC_IS_AVIVO(rdev)) |
798 | return -EINVAL; |
999 | return -EINVAL; |
799 | } |
1000 | } |
800 | if (rdev->is_atom_bios) { |
1001 | if (rdev->is_atom_bios) { |
801 | r = radeon_atombios_init(rdev); |
1002 | r = radeon_atombios_init(rdev); |
802 | if (r) |
1003 | if (r) |
803 | return r; |
1004 | return r; |
804 | } else { |
1005 | } else { |
805 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
1006 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
806 | return -EINVAL; |
1007 | return -EINVAL; |
807 | } |
1008 | } |
808 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
1009 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
809 | if (radeon_asic_reset(rdev)) { |
1010 | if (radeon_asic_reset(rdev)) { |
810 | dev_warn(rdev->dev, |
1011 | dev_warn(rdev->dev, |
811 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
1012 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
812 | RREG32(R_000E40_RBBM_STATUS), |
1013 | RREG32(R_000E40_RBBM_STATUS), |
813 | RREG32(R_0007C0_CP_STAT)); |
1014 | RREG32(R_0007C0_CP_STAT)); |
814 | } |
1015 | } |
815 | /* check if cards are posted or not */ |
1016 | /* check if cards are posted or not */ |
816 | if (radeon_boot_test_post_card(rdev) == false) |
1017 | if (radeon_boot_test_post_card(rdev) == false) |
817 | return -EINVAL; |
1018 | return -EINVAL; |
818 | 1019 | ||
819 | /* Initialize clocks */ |
1020 | /* Initialize clocks */ |
820 | radeon_get_clock_info(rdev->ddev); |
1021 | radeon_get_clock_info(rdev->ddev); |
821 | /* initialize memory controller */ |
1022 | /* initialize memory controller */ |
822 | rs600_mc_init(rdev); |
1023 | rs600_mc_init(rdev); |
823 | rs600_debugfs(rdev); |
1024 | rs600_debugfs(rdev); |
824 | /* Fence driver */ |
1025 | /* Fence driver */ |
825 | r = radeon_fence_driver_init(rdev); |
1026 | r = radeon_fence_driver_init(rdev); |
826 | if (r) |
1027 | if (r) |
827 | return r; |
1028 | return r; |
828 | /* Memory manager */ |
1029 | /* Memory manager */ |
829 | r = radeon_bo_init(rdev); |
1030 | r = radeon_bo_init(rdev); |
830 | if (r) |
1031 | if (r) |
831 | return r; |
1032 | return r; |
832 | r = rs600_gart_init(rdev); |
1033 | r = rs600_gart_init(rdev); |
833 | if (r) |
1034 | if (r) |
834 | return r; |
1035 | return r; |
835 | rs600_set_safe_registers(rdev); |
1036 | rs600_set_safe_registers(rdev); |
- | 1037 | ||
- | 1038 | /* Initialize power management */ |
|
- | 1039 | radeon_pm_init(rdev); |
|
836 | 1040 | ||
837 | rdev->accel_working = true; |
1041 | rdev->accel_working = true; |
838 | r = rs600_startup(rdev); |
1042 | r = rs600_startup(rdev); |
839 | if (r) { |
1043 | if (r) { |
840 | /* Somethings want wront with the accel init stop accel */ |
1044 | /* Somethings want wront with the accel init stop accel */ |
841 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
1045 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
842 | // r100_cp_fini(rdev); |
1046 | // r100_cp_fini(rdev); |
843 | // r100_wb_fini(rdev); |
1047 | // r100_wb_fini(rdev); |
844 | // r100_ib_fini(rdev); |
1048 | // r100_ib_fini(rdev); |
845 | rs600_gart_fini(rdev); |
1049 | rs600_gart_fini(rdev); |
846 | // radeon_irq_kms_fini(rdev); |
1050 | // radeon_irq_kms_fini(rdev); |
847 | rdev->accel_working = false; |
1051 | rdev->accel_working = false; |
848 | } |
1052 | } |
849 | return 0; |
1053 | return 0; |
850 | }><>>>><>><>><>><>><>>>><>><>> |
1054 | }><>>>>><>><> |