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Rev 2160 | Rev 2997 | ||
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Line 33... | Line 33... | ||
33 | * the avivo one, bios is an atombios, 3D block are the one of the |
33 | * the avivo one, bios is an atombios, 3D block are the one of the |
34 | * R4XX family. The GART is different from the RS400 one and is very |
34 | * R4XX family. The GART is different from the RS400 one and is very |
35 | * close to the one of the R600 family (R600 likely being an evolution |
35 | * close to the one of the R600 family (R600 likely being an evolution |
36 | * of the RS600 GART block). |
36 | * of the RS600 GART block). |
37 | */ |
37 | */ |
38 | #include "drmP.h" |
38 | #include |
39 | #include "radeon.h" |
39 | #include "radeon.h" |
40 | #include "radeon_asic.h" |
40 | #include "radeon_asic.h" |
41 | #include "atom.h" |
41 | #include "atom.h" |
42 | #include "rs600d.h" |
42 | #include "rs600d.h" |
Line 43... | Line 43... | ||
43 | 43 | ||
Line 44... | Line 44... | ||
44 | #include "rs600_reg_safe.h" |
44 | #include "rs600_reg_safe.h" |
45 | 45 | ||
Line -... | Line 46... | ||
- | 46 | static void rs600_gpu_init(struct radeon_device *rdev); |
|
- | 47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
|
- | 48 | ||
- | 49 | static const u32 crtc_offsets[2] = |
|
- | 50 | { |
|
- | 51 | 0, |
|
- | 52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
|
- | 53 | }; |
|
- | 54 | ||
- | 55 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
|
- | 56 | { |
|
- | 57 | int i; |
|
- | 58 | ||
- | 59 | if (crtc >= rdev->num_crtc) |
|
- | 60 | return; |
|
- | 61 | ||
- | 62 | if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) { |
|
- | 63 | for (i = 0; i < rdev->usec_timeout; i++) { |
|
- | 64 | if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)) |
|
- | 65 | break; |
|
- | 66 | udelay(1); |
|
- | 67 | } |
|
- | 68 | for (i = 0; i < rdev->usec_timeout; i++) { |
|
- | 69 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
|
- | 70 | break; |
|
- | 71 | udelay(1); |
|
46 | void rs600_gpu_init(struct radeon_device *rdev); |
72 | } |
47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
73 | } |
48 | 74 | } |
|
49 | /* hpd for digital panel detect/disconnect */ |
75 | /* hpd for digital panel detect/disconnect */ |
50 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
76 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
Line 99... | Line 125... | ||
99 | 125 | ||
100 | void rs600_hpd_init(struct radeon_device *rdev) |
126 | void rs600_hpd_init(struct radeon_device *rdev) |
101 | { |
127 | { |
102 | struct drm_device *dev = rdev->ddev; |
128 | struct drm_device *dev = rdev->ddev; |
- | 129 | struct drm_connector *connector; |
|
Line 103... | Line 130... | ||
103 | struct drm_connector *connector; |
130 | unsigned enable = 0; |
104 | 131 | ||
105 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
132 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
106 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
133 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
107 | switch (radeon_connector->hpd.hpd) { |
134 | switch (radeon_connector->hpd.hpd) { |
108 | case RADEON_HPD_1: |
135 | case RADEON_HPD_1: |
109 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
- | |
110 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
136 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
111 | rdev->irq.hpd[0] = true; |
137 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
112 | break; |
138 | break; |
113 | case RADEON_HPD_2: |
139 | case RADEON_HPD_2: |
114 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
- | |
115 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
140 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
116 | rdev->irq.hpd[1] = true; |
141 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
117 | break; |
142 | break; |
118 | default: |
143 | default: |
- | 144 | break; |
|
- | 145 | } |
|
119 | break; |
146 | enable |= 1 << radeon_connector->hpd.hpd; |
120 | } |
- | |
121 | } |
147 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
122 | if (rdev->irq.installed) |
148 | } |
Line 123... | Line 149... | ||
123 | rs600_irq_set(rdev); |
149 | // radeon_irq_kms_enable_hpd(rdev, enable); |
124 | } |
150 | } |
125 | 151 | ||
126 | void rs600_hpd_fini(struct radeon_device *rdev) |
152 | void rs600_hpd_fini(struct radeon_device *rdev) |
- | 153 | { |
|
Line 127... | Line 154... | ||
127 | { |
154 | struct drm_device *dev = rdev->ddev; |
128 | struct drm_device *dev = rdev->ddev; |
155 | struct drm_connector *connector; |
129 | struct drm_connector *connector; |
156 | unsigned disable = 0; |
130 | 157 | ||
131 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
158 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
132 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
159 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
133 | switch (radeon_connector->hpd.hpd) { |
- | |
134 | case RADEON_HPD_1: |
160 | switch (radeon_connector->hpd.hpd) { |
135 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
161 | case RADEON_HPD_1: |
136 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
162 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
137 | rdev->irq.hpd[0] = false; |
163 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
138 | break; |
- | |
139 | case RADEON_HPD_2: |
164 | break; |
140 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
165 | case RADEON_HPD_2: |
141 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
166 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
142 | rdev->irq.hpd[1] = false; |
167 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
- | 168 | break; |
|
143 | break; |
169 | default: |
144 | default: |
- | |
145 | break; |
- | |
146 | } |
170 | break; |
147 | } |
- | |
148 | } |
- | |
149 | - | ||
150 | void rs600_bm_disable(struct radeon_device *rdev) |
- | |
151 | { |
- | |
152 | u32 tmp; |
- | |
153 | - | ||
154 | /* disable bus mastering */ |
171 | } |
Line 155... | Line 172... | ||
155 | tmp = PciRead16(rdev->pdev->bus, rdev->pdev->devfn, 0x4); |
172 | disable |= 1 << radeon_connector->hpd.hpd; |
156 | PciWrite16(rdev->pdev->bus, rdev->pdev->devfn, 0x4, tmp & 0xFFFB); |
173 | } |
157 | mdelay(1); |
174 | // radeon_irq_kms_disable_hpd(rdev, disable); |
Line 178... | Line 195... | ||
178 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
195 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
179 | WREG32(RADEON_CP_RB_WPTR, 0); |
196 | WREG32(RADEON_CP_RB_WPTR, 0); |
180 | WREG32(RADEON_CP_RB_CNTL, tmp); |
197 | WREG32(RADEON_CP_RB_CNTL, tmp); |
181 | // pci_save_state(rdev->pdev); |
198 | // pci_save_state(rdev->pdev); |
182 | /* disable bus mastering */ |
199 | /* disable bus mastering */ |
183 | rs600_bm_disable(rdev); |
200 | // pci_clear_master(rdev->pdev); |
- | 201 | mdelay(1); |
|
184 | /* reset GA+VAP */ |
202 | /* reset GA+VAP */ |
185 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
203 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
186 | S_0000F0_SOFT_RESET_GA(1)); |
204 | S_0000F0_SOFT_RESET_GA(1)); |
187 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
205 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
188 | mdelay(500); |
206 | mdelay(500); |
Line 209... | Line 227... | ||
209 | /* restore PCI & busmastering */ |
227 | /* restore PCI & busmastering */ |
210 | // pci_restore_state(rdev->pdev); |
228 | // pci_restore_state(rdev->pdev); |
211 | /* Check if GPU is idle */ |
229 | /* Check if GPU is idle */ |
212 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
230 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
213 | dev_err(rdev->dev, "failed to reset GPU\n"); |
231 | dev_err(rdev->dev, "failed to reset GPU\n"); |
214 | rdev->gpu_lockup = true; |
- | |
215 | ret = -1; |
232 | ret = -1; |
216 | } else |
233 | } else |
217 | dev_info(rdev->dev, "GPU reset succeed\n"); |
234 | dev_info(rdev->dev, "GPU reset succeed\n"); |
218 | rv515_mc_resume(rdev, &save); |
235 | rv515_mc_resume(rdev, &save); |
219 | return ret; |
236 | return ret; |
Line 238... | Line 255... | ||
238 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
255 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
239 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
256 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
240 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
257 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
241 | } |
258 | } |
Line 242... | Line 259... | ||
242 | 259 | ||
243 | int rs600_gart_init(struct radeon_device *rdev) |
260 | static int rs600_gart_init(struct radeon_device *rdev) |
244 | { |
261 | { |
Line 245... | Line 262... | ||
245 | int r; |
262 | int r; |
246 | 263 | ||
247 | if (rdev->gart.table.vram.robj) { |
264 | if (rdev->gart.robj) { |
248 | WARN(1, "RS600 GART already initialized\n"); |
265 | WARN(1, "RS600 GART already initialized\n"); |
249 | return 0; |
266 | return 0; |
250 | } |
267 | } |
Line 260... | Line 277... | ||
260 | static int rs600_gart_enable(struct radeon_device *rdev) |
277 | static int rs600_gart_enable(struct radeon_device *rdev) |
261 | { |
278 | { |
262 | u32 tmp; |
279 | u32 tmp; |
263 | int r, i; |
280 | int r, i; |
Line 264... | Line 281... | ||
264 | 281 | ||
265 | if (rdev->gart.table.vram.robj == NULL) { |
282 | if (rdev->gart.robj == NULL) { |
266 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
283 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
267 | return -EINVAL; |
284 | return -EINVAL; |
268 | } |
285 | } |
269 | r = radeon_gart_table_vram_pin(rdev); |
286 | r = radeon_gart_table_vram_pin(rdev); |
Line 313... | Line 330... | ||
313 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
330 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
314 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
331 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
315 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
332 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
316 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
333 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
317 | rs600_gart_tlb_flush(rdev); |
334 | rs600_gart_tlb_flush(rdev); |
- | 335 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
|
- | 336 | (unsigned)(rdev->mc.gtt_size >> 20), |
|
- | 337 | (unsigned long long)rdev->gart.table_addr); |
|
318 | rdev->gart.ready = true; |
338 | rdev->gart.ready = true; |
319 | return 0; |
339 | return 0; |
320 | } |
340 | } |
Line 321... | Line 341... | ||
321 | 341 | ||
322 | void rs600_gart_disable(struct radeon_device *rdev) |
342 | static void rs600_gart_disable(struct radeon_device *rdev) |
323 | { |
343 | { |
324 | u32 tmp; |
- | |
Line 325... | Line 344... | ||
325 | int r; |
344 | u32 tmp; |
326 | 345 | ||
327 | /* FIXME: disable out of gart access */ |
346 | /* FIXME: disable out of gart access */ |
328 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
347 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
329 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
348 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
330 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
- | |
331 | if (rdev->gart.table.vram.robj) { |
- | |
332 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
- | |
333 | if (r == 0) { |
- | |
334 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
- | |
335 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
- | |
336 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
- | |
337 | } |
349 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
Line 338... | Line 350... | ||
338 | } |
350 | radeon_gart_table_vram_unpin(rdev); |
339 | } |
351 | } |
340 | 352 | ||
341 | void rs600_gart_fini(struct radeon_device *rdev) |
353 | static void rs600_gart_fini(struct radeon_device *rdev) |
342 | { |
354 | { |
343 | radeon_gart_fini(rdev); |
355 | radeon_gart_fini(rdev); |
Line 351... | Line 363... | ||
351 | #define R600_PTE_READABLE (1 << 5) |
363 | #define R600_PTE_READABLE (1 << 5) |
352 | #define R600_PTE_WRITEABLE (1 << 6) |
364 | #define R600_PTE_WRITEABLE (1 << 6) |
Line 353... | Line 365... | ||
353 | 365 | ||
354 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
366 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
355 | { |
367 | { |
Line 356... | Line 368... | ||
356 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
368 | void __iomem *ptr = (void *)rdev->gart.ptr; |
357 | 369 | ||
358 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
370 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
359 | return -EINVAL; |
371 | return -EINVAL; |
Line 371... | Line 383... | ||
371 | uint32_t mode_int = 0; |
383 | uint32_t mode_int = 0; |
372 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
384 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
373 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
385 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
374 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
386 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
375 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
387 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
- | 388 | u32 hdmi0; |
|
- | 389 | if (ASIC_IS_DCE2(rdev)) |
|
- | 390 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
|
- | 391 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
|
- | 392 | else |
|
- | 393 | hdmi0 = 0; |
|
Line 376... | Line 394... | ||
376 | 394 | ||
377 | if (!rdev->irq.installed) { |
395 | if (!rdev->irq.installed) { |
378 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
396 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
379 | WREG32(R_000040_GEN_INT_CNTL, 0); |
397 | WREG32(R_000040_GEN_INT_CNTL, 0); |
380 | return -EINVAL; |
398 | return -EINVAL; |
381 | } |
399 | } |
382 | if (rdev->irq.sw_int) { |
400 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
383 | tmp |= S_000040_SW_INT_EN(1); |
401 | tmp |= S_000040_SW_INT_EN(1); |
384 | } |
- | |
385 | if (rdev->irq.gui_idle) { |
- | |
386 | tmp |= S_000040_GUI_IDLE(1); |
- | |
387 | } |
402 | } |
388 | if (rdev->irq.crtc_vblank_int[0] || |
403 | if (rdev->irq.crtc_vblank_int[0] || |
389 | rdev->irq.pflip[0]) { |
404 | atomic_read(&rdev->irq.pflip[0])) { |
390 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
405 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
391 | } |
406 | } |
392 | if (rdev->irq.crtc_vblank_int[1] || |
407 | if (rdev->irq.crtc_vblank_int[1] || |
393 | rdev->irq.pflip[1]) { |
408 | atomic_read(&rdev->irq.pflip[1])) { |
394 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
409 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
395 | } |
410 | } |
396 | if (rdev->irq.hpd[0]) { |
411 | if (rdev->irq.hpd[0]) { |
397 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
412 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
398 | } |
413 | } |
399 | if (rdev->irq.hpd[1]) { |
414 | if (rdev->irq.hpd[1]) { |
400 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
415 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
- | 416 | } |
|
- | 417 | if (rdev->irq.afmt[0]) { |
|
- | 418 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
|
401 | } |
419 | } |
402 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
420 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
403 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
421 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
404 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
422 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
- | 423 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
|
- | 424 | if (ASIC_IS_DCE2(rdev)) |
|
405 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
425 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
406 | return 0; |
426 | return 0; |
Line 407... | Line 427... | ||
407 | } |
427 | } |
408 | 428 | ||
409 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
429 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
410 | { |
430 | { |
411 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
431 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
Line 412... | Line -... | ||
412 | uint32_t irq_mask = S_000044_SW_INT(1); |
- | |
413 | u32 tmp; |
- | |
414 | - | ||
415 | /* the interrupt works, but the status bit is permanently asserted */ |
- | |
416 | if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { |
- | |
417 | if (!rdev->irq.gui_idle_acked) |
- | |
418 | irq_mask |= S_000044_GUI_IDLE_STAT(1); |
432 | uint32_t irq_mask = S_000044_SW_INT(1); |
419 | } |
433 | u32 tmp; |
420 | 434 | ||
421 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
435 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
422 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
436 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
Line 440... | Line 454... | ||
440 | } |
454 | } |
441 | } else { |
455 | } else { |
442 | rdev->irq.stat_regs.r500.disp_int = 0; |
456 | rdev->irq.stat_regs.r500.disp_int = 0; |
443 | } |
457 | } |
Line -... | Line 458... | ||
- | 458 | ||
- | 459 | if (ASIC_IS_DCE2(rdev)) { |
|
- | 460 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & |
|
- | 461 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); |
|
- | 462 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
|
- | 463 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); |
|
- | 464 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); |
|
- | 465 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); |
|
- | 466 | } |
|
- | 467 | } else |
|
- | 468 | rdev->irq.stat_regs.r500.hdmi0_status = 0; |
|
444 | 469 | ||
445 | if (irqs) { |
470 | if (irqs) { |
446 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
471 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
447 | } |
472 | } |
448 | return irqs & irq_mask; |
473 | return irqs & irq_mask; |
Line 449... | Line 474... | ||
449 | } |
474 | } |
450 | 475 | ||
- | 476 | void rs600_irq_disable(struct radeon_device *rdev) |
|
- | 477 | { |
|
- | 478 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
|
451 | void rs600_irq_disable(struct radeon_device *rdev) |
479 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
452 | { |
480 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
453 | WREG32(R_000040_GEN_INT_CNTL, 0); |
481 | WREG32(R_000040_GEN_INT_CNTL, 0); |
454 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
482 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
455 | /* Wait and acknowledge irq */ |
483 | /* Wait and acknowledge irq */ |
Line 459... | Line 487... | ||
459 | 487 | ||
460 | int rs600_irq_process(struct radeon_device *rdev) |
488 | int rs600_irq_process(struct radeon_device *rdev) |
461 | { |
489 | { |
462 | u32 status, msi_rearm; |
490 | u32 status, msi_rearm; |
463 | bool queue_hotplug = false; |
- | |
464 | - | ||
465 | /* reset gui idle ack. the status bit is broken */ |
491 | bool queue_hotplug = false; |
Line 466... | Line 492... | ||
466 | rdev->irq.gui_idle_acked = false; |
492 | bool queue_hdmi = false; |
- | 493 | ||
467 | 494 | status = rs600_irq_ack(rdev); |
|
- | 495 | if (!status && |
|
468 | status = rs600_irq_ack(rdev); |
496 | !rdev->irq.stat_regs.r500.disp_int && |
469 | if (!status && !rdev->irq.stat_regs.r500.disp_int) { |
497 | !rdev->irq.stat_regs.r500.hdmi0_status) { |
- | 498 | return IRQ_NONE; |
|
470 | return IRQ_NONE; |
499 | } |
- | 500 | while (status || |
|
471 | } |
501 | rdev->irq.stat_regs.r500.disp_int || |
472 | while (status || rdev->irq.stat_regs.r500.disp_int) { |
502 | rdev->irq.stat_regs.r500.hdmi0_status) { |
473 | /* SW interrupt */ |
503 | /* SW interrupt */ |
474 | if (G_000044_SW_INT(status)) { |
- | |
475 | radeon_fence_process(rdev); |
- | |
476 | } |
- | |
477 | /* GUI idle */ |
- | |
478 | if (G_000040_GUI_IDLE(status)) { |
- | |
479 | rdev->irq.gui_idle_acked = true; |
- | |
480 | rdev->pm.gui_idle = true; |
504 | if (G_000044_SW_INT(status)) { |
481 | // wake_up(&rdev->irq.idle_queue); |
505 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
482 | } |
506 | } |
483 | /* Vertical blank interrupts */ |
507 | /* Vertical blank interrupts */ |
484 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
508 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
Line 505... | Line 529... | ||
505 | } |
529 | } |
506 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
530 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
507 | queue_hotplug = true; |
531 | queue_hotplug = true; |
508 | DRM_DEBUG("HPD2\n"); |
532 | DRM_DEBUG("HPD2\n"); |
509 | } |
533 | } |
- | 534 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
|
- | 535 | queue_hdmi = true; |
|
- | 536 | DRM_DEBUG("HDMI0\n"); |
|
- | 537 | } |
|
510 | status = rs600_irq_ack(rdev); |
538 | status = rs600_irq_ack(rdev); |
511 | } |
539 | } |
512 | /* reset gui idle ack. the status bit is broken */ |
- | |
513 | rdev->irq.gui_idle_acked = false; |
- | |
514 | // if (queue_hotplug) |
540 | // if (queue_hotplug) |
515 | // schedule_work(&rdev->hotplug_work); |
541 | // schedule_work(&rdev->hotplug_work); |
- | 542 | // if (queue_hdmi) |
|
- | 543 | // schedule_work(&rdev->audio_work); |
|
516 | if (rdev->msi_enabled) { |
544 | if (rdev->msi_enabled) { |
517 | switch (rdev->family) { |
545 | switch (rdev->family) { |
518 | case CHIP_RS600: |
546 | case CHIP_RS600: |
519 | case CHIP_RS690: |
547 | case CHIP_RS690: |
520 | case CHIP_RS740: |
548 | case CHIP_RS740: |
521 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
549 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
522 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
550 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
523 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
551 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
524 | break; |
552 | break; |
525 | default: |
553 | default: |
526 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; |
- | |
527 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); |
- | |
528 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); |
554 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
529 | break; |
555 | break; |
530 | } |
556 | } |
531 | } |
557 | } |
532 | return IRQ_HANDLED; |
558 | return IRQ_HANDLED; |
533 | } |
559 | } |
Line 550... | Line 576... | ||
550 | udelay(1); |
576 | udelay(1); |
551 | } |
577 | } |
552 | return -1; |
578 | return -1; |
553 | } |
579 | } |
Line 554... | Line 580... | ||
554 | 580 | ||
555 | void rs600_gpu_init(struct radeon_device *rdev) |
581 | static void rs600_gpu_init(struct radeon_device *rdev) |
556 | { |
582 | { |
557 | r420_pipes_init(rdev); |
583 | r420_pipes_init(rdev); |
558 | /* Wait for mc idle */ |
584 | /* Wait for mc idle */ |
559 | if (rs600_mc_wait_for_idle(rdev)) |
585 | if (rs600_mc_wait_for_idle(rdev)) |
560 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
586 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
Line 561... | Line 587... | ||
561 | } |
587 | } |
562 | 588 | ||
563 | void rs600_mc_init(struct radeon_device *rdev) |
589 | static void rs600_mc_init(struct radeon_device *rdev) |
Line 564... | Line 590... | ||
564 | { |
590 | { |
565 | u64 base; |
591 | u64 base; |
Line 620... | Line 646... | ||
620 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
646 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
621 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
647 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
622 | WREG32(R_000074_MC_IND_DATA, v); |
648 | WREG32(R_000074_MC_IND_DATA, v); |
623 | } |
649 | } |
Line 624... | Line 650... | ||
624 | 650 | ||
625 | void rs600_debugfs(struct radeon_device *rdev) |
651 | static void rs600_debugfs(struct radeon_device *rdev) |
626 | { |
652 | { |
627 | if (r100_debugfs_rbbm_init(rdev)) |
653 | if (r100_debugfs_rbbm_init(rdev)) |
628 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
654 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
Line 686... | Line 712... | ||
686 | r = r100_cp_init(rdev, 1024 * 1024); |
712 | r = r100_cp_init(rdev, 1024 * 1024); |
687 | if (r) { |
713 | if (r) { |
688 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
714 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
689 | return r; |
715 | return r; |
690 | } |
716 | } |
- | 717 | ||
691 | r = r100_ib_init(rdev); |
718 | r = radeon_ib_pool_init(rdev); |
692 | if (r) { |
719 | if (r) { |
693 | dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
720 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
694 | return r; |
721 | return r; |
695 | } |
722 | } |
- | 723 | ||
- | 724 | ||
696 | return 0; |
725 | return 0; |
697 | } |
726 | } |
Line 752... | Line 781... | ||
752 | return r; |
781 | return r; |
753 | r = rs600_gart_init(rdev); |
782 | r = rs600_gart_init(rdev); |
754 | if (r) |
783 | if (r) |
755 | return r; |
784 | return r; |
756 | rs600_set_safe_registers(rdev); |
785 | rs600_set_safe_registers(rdev); |
- | 786 | ||
757 | rdev->accel_working = true; |
787 | rdev->accel_working = true; |
758 | r = rs600_startup(rdev); |
788 | r = rs600_startup(rdev); |
759 | if (r) { |
789 | if (r) { |
760 | /* Somethings want wront with the accel init stop accel */ |
790 | /* Somethings want wront with the accel init stop accel */ |
761 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
791 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |