WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/rs600.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
/* RS600 / Radeon X1250/X1270 integrated GPU
 *
 * This file gather function specific to RS600 which is the IGP of
 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
 * is the X1250/X1270 supporting AMD CPU). The display engine are
 * the avivo one, bios is an atombios, 3D block are the one of the
 * R4XX family. The GART is different from the RS400 one and is very
 * close to the one of the R600 family (R600 likely being an evolution
 * of the RS600 GART block).
 */
#include "drmP.h"
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
#include "rs600d.h"
 
#include "rs600_reg_safe.h"
 
void rs600_gpu_init(struct radeon_device *rdev);
int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 
/* hpd for digital panel detect/disconnect */
bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
{
	u32 tmp;
	bool connected = false;
 
	switch (hpd) {
	case RADEON_HPD_1:
		tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
		if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
			connected = true;
		break;
	case RADEON_HPD_2:
		tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
		if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
			connected = true;
		break;
	default:
		break;
	}
	return connected;
}
 
void rs600_hpd_set_polarity(struct radeon_device *rdev,
			    enum radeon_hpd_id hpd)
{
	u32 tmp;
	bool connected = rs600_hpd_sense(rdev, hpd);
 
	switch (hpd) {
	case RADEON_HPD_1:
		tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
		if (connected)
			tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
		else
			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
		WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
		break;
	case RADEON_HPD_2:
		tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
		if (connected)
			tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
		else
			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
		WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
		break;
	default:
		break;
	}
}
 
void rs600_hpd_init(struct radeon_device *rdev)
{
	struct drm_device *dev = rdev->ddev;
	struct drm_connector *connector;
 
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		switch (radeon_connector->hpd.hpd) {
		case RADEON_HPD_1:
			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
			       S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
			rdev->irq.hpd[0] = true;
			break;
		case RADEON_HPD_2:
			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
			       S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
			rdev->irq.hpd[1] = true;
			break;
		default:
			break;
		}
	}
	if (rdev->irq.installed)
		rs600_irq_set(rdev);
}
 
void rs600_hpd_fini(struct radeon_device *rdev)
{
	struct drm_device *dev = rdev->ddev;
	struct drm_connector *connector;
 
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		switch (radeon_connector->hpd.hpd) {
		case RADEON_HPD_1:
			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
			       S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
			rdev->irq.hpd[0] = false;
			break;
		case RADEON_HPD_2:
			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
			       S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
			rdev->irq.hpd[1] = false;
			break;
		default:
			break;
		}
	}
}
 
void rs600_bm_disable(struct radeon_device *rdev)
{
	u32 tmp;
 
	/* disable bus mastering */
    tmp = PciRead16(rdev->pdev->bus, rdev->pdev->devfn, 0x4);
    PciWrite16(rdev->pdev->bus, rdev->pdev->devfn, 0x4, tmp & 0xFFFB);
mdelay(1);
}
 
int rs600_asic_reset(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
	u32 status, tmp;
	int ret = 0;
 
	status = RREG32(R_000E40_RBBM_STATUS);
	if (!G_000E40_GUI_ACTIVE(status)) {
		return 0;
	}
	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* stop CP */
	WREG32(RADEON_CP_CSQ_CNTL, 0);
	tmp = RREG32(RADEON_CP_RB_CNTL);
	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
	WREG32(RADEON_CP_RB_RPTR_WR, 0);
	WREG32(RADEON_CP_RB_WPTR, 0);
	WREG32(RADEON_CP_RB_CNTL, tmp);
//   pci_save_state(rdev->pdev);
	/* disable bus mastering */
	rs600_bm_disable(rdev);
	/* reset GA+VAP */
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
					S_0000F0_SOFT_RESET_GA(1));
	RREG32(R_0000F0_RBBM_SOFT_RESET);
	mdelay(500);
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
	mdelay(1);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* reset CP */
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
	RREG32(R_0000F0_RBBM_SOFT_RESET);
	mdelay(500);
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
	mdelay(1);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* reset MC */
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
	RREG32(R_0000F0_RBBM_SOFT_RESET);
	mdelay(500);
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
	mdelay(1);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* restore PCI & busmastering */
//   pci_restore_state(rdev->pdev);
	/* Check if GPU is idle */
	if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
		dev_err(rdev->dev, "failed to reset GPU\n");
		rdev->gpu_lockup = true;
		ret = -1;
	} else
		dev_info(rdev->dev, "GPU reset succeed\n");
	rv515_mc_resume(rdev, &save);
	return ret;
}
 
/*
 * GART.
 */
void rs600_gart_tlb_flush(struct radeon_device *rdev)
{
	uint32_t tmp;
 
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
}
 
int rs600_gart_init(struct radeon_device *rdev)
{
	int r;
 
	if (rdev->gart.table.vram.robj) {
		WARN(1, "RS600 GART already initialized\n");
		return 0;
	}
	/* Initialize common gart structure */
	r = radeon_gart_init(rdev);
	if (r) {
		return r;
	}
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
	return radeon_gart_table_vram_alloc(rdev);
}
 
static int rs600_gart_enable(struct radeon_device *rdev)
{
	u32 tmp;
	int r, i;
 
	if (rdev->gart.table.vram.robj == NULL) {
		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		return -EINVAL;
	}
	r = radeon_gart_table_vram_pin(rdev);
	if (r)
		return r;
	radeon_gart_restore(rdev);
	/* Enable bus master */
	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
	WREG32(RADEON_BUS_CNTL, tmp);
	/* FIXME: setup default page */
	WREG32_MC(R_000100_MC_PT0_CNTL,
		 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
		  S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 
	for (i = 0; i < 19; i++) {
		WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
			S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
			S_00016C_SYSTEM_ACCESS_MODE_MASK(
				  V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
			S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
				  V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
			  S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
			S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
			  S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
	}
	/* enable first context */
	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
			S_000102_ENABLE_PAGE_TABLE(1) |
			S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 
	/* disable all other contexts */
	for (i = 1; i < 8; i++)
		WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 
	/* setup the page table */
	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
		 rdev->gart.table_addr);
	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 
	/* System context maps to VRAM space */
	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 
	/* enable page tables */
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
	tmp = RREG32_MC(R_000009_MC_CNTL1);
	WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
	rs600_gart_tlb_flush(rdev);
	rdev->gart.ready = true;
	return 0;
}
 
void rs600_gart_disable(struct radeon_device *rdev)
{
	u32 tmp;
	int r;
 
	/* FIXME: disable out of gart access */
	WREG32_MC(R_000100_MC_PT0_CNTL, 0);
	tmp = RREG32_MC(R_000009_MC_CNTL1);
	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
	if (rdev->gart.table.vram.robj) {
		r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
		if (r == 0) {
			radeon_bo_kunmap(rdev->gart.table.vram.robj);
			radeon_bo_unpin(rdev->gart.table.vram.robj);
			radeon_bo_unreserve(rdev->gart.table.vram.robj);
		}
	}
}
 
void rs600_gart_fini(struct radeon_device *rdev)
{
	radeon_gart_fini(rdev);
	rs600_gart_disable(rdev);
	radeon_gart_table_vram_free(rdev);
}
 
#define R600_PTE_VALID     (1 << 0)
#define R600_PTE_SYSTEM    (1 << 1)
#define R600_PTE_SNOOPED   (1 << 2)
#define R600_PTE_READABLE  (1 << 5)
#define R600_PTE_WRITEABLE (1 << 6)
 
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
{
	void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 
	if (i < 0 || i > rdev->gart.num_gpu_pages) {
		return -EINVAL;
	}
	addr = addr & 0xFFFFFFFFFFFFF000ULL;
	addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
	addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
	writeq(addr, ((void __iomem *)ptr) + (i * 8));
	return 0;
}
 
 
 
int rs600_irq_set(struct radeon_device *rdev)
{
	uint32_t tmp = 0;
	uint32_t mode_int = 0;
	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
		~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
		~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 
   if (!rdev->irq.installed) {
		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
		WREG32(R_000040_GEN_INT_CNTL, 0);
		return -EINVAL;
	}
	if (rdev->irq.sw_int) {
		tmp |= S_000040_SW_INT_EN(1);
	}
	if (rdev->irq.gui_idle) {
		tmp |= S_000040_GUI_IDLE(1);
	}
	if (rdev->irq.crtc_vblank_int[0] ||
	    rdev->irq.pflip[0]) {
		mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
	}
	if (rdev->irq.crtc_vblank_int[1] ||
	    rdev->irq.pflip[1]) {
		mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
	}
	if (rdev->irq.hpd[0]) {
		hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
	}
	if (rdev->irq.hpd[1]) {
		hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
	}
	WREG32(R_000040_GEN_INT_CNTL, tmp);
	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
	return 0;
}
 
static inline u32 rs600_irq_ack(struct radeon_device *rdev)
{
	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
	uint32_t irq_mask = S_000044_SW_INT(1);
	u32 tmp;
 
	/* the interrupt works, but the status bit is permanently asserted */
	if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
		if (!rdev->irq.gui_idle_acked)
			irq_mask |= S_000044_GUI_IDLE_STAT(1);
	}
 
	if (G_000044_DISPLAY_INT_STAT(irqs)) {
		rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			WREG32(R_006534_D1MODE_VBLANK_STATUS,
				S_006534_D1MODE_VBLANK_ACK(1));
		}
		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			WREG32(R_006D34_D2MODE_VBLANK_STATUS,
				S_006D34_D2MODE_VBLANK_ACK(1));
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
			WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
			WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
		}
	} else {
		rdev->irq.stat_regs.r500.disp_int = 0;
	}
 
	if (irqs) {
		WREG32(R_000044_GEN_INT_STATUS, irqs);
	}
	return irqs & irq_mask;
}
 
void rs600_irq_disable(struct radeon_device *rdev)
{
	WREG32(R_000040_GEN_INT_CNTL, 0);
	WREG32(R_006540_DxMODE_INT_MASK, 0);
	/* Wait and acknowledge irq */
	mdelay(1);
	rs600_irq_ack(rdev);
}
 
int rs600_irq_process(struct radeon_device *rdev)
{
	u32 status, msi_rearm;
	bool queue_hotplug = false;
 
	/* reset gui idle ack.  the status bit is broken */
	rdev->irq.gui_idle_acked = false;
 
	status = rs600_irq_ack(rdev);
	if (!status && !rdev->irq.stat_regs.r500.disp_int) {
		return IRQ_NONE;
	}
	while (status || rdev->irq.stat_regs.r500.disp_int) {
		/* SW interrupt */
		if (G_000044_SW_INT(status)) {
			radeon_fence_process(rdev);
		}
		/* GUI idle */
		if (G_000040_GUI_IDLE(status)) {
			rdev->irq.gui_idle_acked = true;
			rdev->pm.gui_idle = true;
//			wake_up(&rdev->irq.idle_queue);
		}
		/* Vertical blank interrupts */
		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			if (rdev->irq.crtc_vblank_int[0]) {
//				drm_handle_vblank(rdev->ddev, 0);
				rdev->pm.vblank_sync = true;
//				wake_up(&rdev->irq.vblank_queue);
			}
//			if (rdev->irq.pflip[0])
//				radeon_crtc_handle_flip(rdev, 0);
		}
		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			if (rdev->irq.crtc_vblank_int[1]) {
//				drm_handle_vblank(rdev->ddev, 1);
				rdev->pm.vblank_sync = true;
//				wake_up(&rdev->irq.vblank_queue);
			}
//			if (rdev->irq.pflip[1])
//				radeon_crtc_handle_flip(rdev, 1);
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			queue_hotplug = true;
			DRM_DEBUG("HPD1\n");
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			queue_hotplug = true;
			DRM_DEBUG("HPD2\n");
		}
		status = rs600_irq_ack(rdev);
	}
	/* reset gui idle ack.  the status bit is broken */
	rdev->irq.gui_idle_acked = false;
//	if (queue_hotplug)
//		schedule_work(&rdev->hotplug_work);
	if (rdev->msi_enabled) {
		switch (rdev->family) {
		case CHIP_RS600:
		case CHIP_RS690:
		case CHIP_RS740:
			msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
			WREG32(RADEON_BUS_CNTL, msi_rearm);
			WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
			break;
		default:
			msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
			WREG32(RADEON_MSI_REARM_EN, msi_rearm);
			WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
			break;
		}
	}
	return IRQ_HANDLED;
}
 
u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
{
	if (crtc == 0)
		return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
	else
		return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
}
 
int rs600_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
 
	for (i = 0; i < rdev->usec_timeout; i++) {
		if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
			return 0;
		udelay(1);
	}
	return -1;
}
 
void rs600_gpu_init(struct radeon_device *rdev)
{
	r420_pipes_init(rdev);
	/* Wait for mc idle */
	if (rs600_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
}
 
void rs600_mc_init(struct radeon_device *rdev)
{
	u64 base;
 
	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
	rdev->mc.vram_is_ddr = true;
	rdev->mc.vram_width = 128;
	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
	rdev->mc.visible_vram_size = rdev->mc.aper_size;
	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
	base = RREG32_MC(R_000004_MC_FB_LOCATION);
	base = G_000004_MC_FB_START(base) << 16;
	radeon_vram_location(rdev, &rdev->mc, base);
	rdev->mc.gtt_base_align = 0;
	radeon_gtt_location(rdev, &rdev->mc);
	radeon_update_bandwidth_info(rdev);
}
 
void rs600_bandwidth_update(struct radeon_device *rdev)
{
	struct drm_display_mode *mode0 = NULL;
	struct drm_display_mode *mode1 = NULL;
	u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
	/* FIXME: implement full support */
 
	radeon_update_display_priority(rdev);
 
	if (rdev->mode_info.crtcs[0]->base.enabled)
		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
	if (rdev->mode_info.crtcs[1]->base.enabled)
		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 
	rs690_line_buffer_adjust(rdev, mode0, mode1);
 
	if (rdev->disp_priority == 2) {
		d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
		d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
		d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
		d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
		WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
		WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
		WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
		WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
	}
}
 
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
{
	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
		S_000070_MC_IND_CITF_ARB0(1));
	return RREG32(R_000074_MC_IND_DATA);
}
 
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
		S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
	WREG32(R_000074_MC_IND_DATA, v);
}
 
void rs600_debugfs(struct radeon_device *rdev)
{
	if (r100_debugfs_rbbm_init(rdev))
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
}
 
void rs600_set_safe_registers(struct radeon_device *rdev)
{
	rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
}
 
static void rs600_mc_program(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
 
	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);
 
	/* Wait for mc idle */
	if (rs600_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 
	/* FIXME: What does AGP means for such chipset ? */
	WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
	WREG32_MC(R_000006_AGP_BASE, 0);
	WREG32_MC(R_000007_AGP_BASE_2, 0);
	/* Program MC */
	WREG32_MC(R_000004_MC_FB_LOCATION,
			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
	WREG32(R_000134_HDP_FB_LOCATION,
		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 
	rv515_mc_resume(rdev, &save);
}
 
static int rs600_startup(struct radeon_device *rdev)
{
	int r;
 
	rs600_mc_program(rdev);
	/* Resume clock */
	rv515_clock_startup(rdev);
	/* Initialize GPU configuration (# pipes, ...) */
	rs600_gpu_init(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	r = rs600_gart_enable(rdev);
	if (r)
	return r;
 
	/* allocate wb buffer */
	r = radeon_wb_init(rdev);
	if (r)
		return r;
 
	/* Enable IRQ */
	rs600_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
	r = r100_cp_init(rdev, 1024 * 1024);
	if (r) {
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
		return r;
	}
	r = r100_ib_init(rdev);
	if (r) {
		dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
		return r;
	}
	return 0;
}
 
 
 
int rs600_init(struct radeon_device *rdev)
{
	int r;
 
	/* Disable VGA */
	rv515_vga_render_disable(rdev);
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* restore some register to sane defaults */
	r100_restore_sanity(rdev);
	/* BIOS */
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r)
			return r;
	} else {
		dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
		return -EINVAL;
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_asic_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (radeon_boot_test_post_card(rdev) == false)
		return -EINVAL;
 
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* initialize memory controller */
	rs600_mc_init(rdev);
	rs600_debugfs(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r)
		return r;
	r = radeon_irq_kms_init(rdev);
	if (r)
		return r;
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
	r = rs600_gart_init(rdev);
	if (r)
		return r;
	rs600_set_safe_registers(rdev);
	rdev->accel_working = true;
	r = rs600_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
//		r100_cp_fini(rdev);
//		r100_wb_fini(rdev);
//		r100_ib_fini(rdev);
		rs600_gart_fini(rdev);
//		radeon_irq_kms_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}

Rev 1963	Rev 2005
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	/* RS600 / Radeon X1250/X1270 integrated GPU	28	/* RS600 / Radeon X1250/X1270 integrated GPU
29	*	29	*
30	* This file gather function specific to RS600 which is the IGP of	30	* This file gather function specific to RS600 which is the IGP of
31	* the X1250/X1270 family supporting intel CPU (while RS690/RS740	31	* the X1250/X1270 family supporting intel CPU (while RS690/RS740
32	* is the X1250/X1270 supporting AMD CPU). The display engine are	32	* is the X1250/X1270 supporting AMD CPU). The display engine are
33	* the avivo one, bios is an atombios, 3D block are the one of the	33	* the avivo one, bios is an atombios, 3D block are the one of the
34	* R4XX family. The GART is different from the RS400 one and is very	34	* R4XX family. The GART is different from the RS400 one and is very
35	* close to the one of the R600 family (R600 likely being an evolution	35	* close to the one of the R600 family (R600 likely being an evolution
36	* of the RS600 GART block).	36	* of the RS600 GART block).
37	*/	37	*/
38	#include "drmP.h"	38	#include "drmP.h"
39	#include "radeon.h"	39	#include "radeon.h"
40	#include "radeon_asic.h"	40	#include "radeon_asic.h"
41	#include "atom.h"	41	#include "atom.h"
42	#include "rs600d.h"	42	#include "rs600d.h"
43		43
44	#include "rs600_reg_safe.h"	44	#include "rs600_reg_safe.h"
45		45
46	void rs600_gpu_init(struct radeon_device *rdev);	46	void rs600_gpu_init(struct radeon_device *rdev);
47	int rs600_mc_wait_for_idle(struct radeon_device *rdev);	47	int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48		48
49	/* hpd for digital panel detect/disconnect */	49	/* hpd for digital panel detect/disconnect */
50	bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)	50	bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
51	{	51	{
52	u32 tmp;	52	u32 tmp;
53	bool connected = false;	53	bool connected = false;
54		54
55	switch (hpd) {	55	switch (hpd) {
56	case RADEON_HPD_1:	56	case RADEON_HPD_1:
57	tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);	57	tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
58	if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))	58	if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
59	connected = true;	59	connected = true;
60	break;	60	break;
61	case RADEON_HPD_2:	61	case RADEON_HPD_2:
62	tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);	62	tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
63	if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))	63	if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
64	connected = true;	64	connected = true;
65	break;	65	break;
66	default:	66	default:
67	break;	67	break;
68	}	68	}
69	return connected;	69	return connected;
70	}	70	}
71		71
72	void rs600_hpd_set_polarity(struct radeon_device *rdev,	72	void rs600_hpd_set_polarity(struct radeon_device *rdev,
73	enum radeon_hpd_id hpd)	73	enum radeon_hpd_id hpd)
74	{	74	{
75	u32 tmp;	75	u32 tmp;
76	bool connected = rs600_hpd_sense(rdev, hpd);	76	bool connected = rs600_hpd_sense(rdev, hpd);
77		77
78	switch (hpd) {	78	switch (hpd) {
79	case RADEON_HPD_1:	79	case RADEON_HPD_1:
80	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);	80	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
81	if (connected)	81	if (connected)
82	tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);	82	tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
83	else	83	else
84	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);	84	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
85	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);	85	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
86	break;	86	break;
87	case RADEON_HPD_2:	87	case RADEON_HPD_2:
88	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);	88	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
89	if (connected)	89	if (connected)
90	tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);	90	tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
91	else	91	else
92	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);	92	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
93	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);	93	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
94	break;	94	break;
95	default:	95	default:
96	break;	96	break;
97	}	97	}
98	}	98	}
99		99
100	void rs600_hpd_init(struct radeon_device *rdev)	100	void rs600_hpd_init(struct radeon_device *rdev)
101	{	101	{
102	struct drm_device *dev = rdev->ddev;	102	struct drm_device *dev = rdev->ddev;
103	struct drm_connector *connector;	103	struct drm_connector *connector;
104		104
105	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {	105	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
106	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	106	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
107	switch (radeon_connector->hpd.hpd) {	107	switch (radeon_connector->hpd.hpd) {
108	case RADEON_HPD_1:	108	case RADEON_HPD_1:
109	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,	109	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
110	S_007D00_DC_HOT_PLUG_DETECT1_EN(1));	110	S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
111	// rdev->irq.hpd[0] = true;	111	rdev->irq.hpd[0] = true;
112	break;	112	break;
113	case RADEON_HPD_2:	113	case RADEON_HPD_2:
114	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,	114	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
115	S_007D10_DC_HOT_PLUG_DETECT2_EN(1));	115	S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
116	// rdev->irq.hpd[1] = true;	116	rdev->irq.hpd[1] = true;
117	break;	117	break;
118	default:	118	default:
119	break;	119	break;
120	}	120	}
121	}	121	}
122	// if (rdev->irq.installed)	122	if (rdev->irq.installed)
123	// rs600_irq_set(rdev);	123	rs600_irq_set(rdev);
124	}	124	}
125		125
126	void rs600_hpd_fini(struct radeon_device *rdev)	126	void rs600_hpd_fini(struct radeon_device *rdev)
127	{	127	{
128	struct drm_device *dev = rdev->ddev;	128	struct drm_device *dev = rdev->ddev;
129	struct drm_connector *connector;	129	struct drm_connector *connector;
130		130
131	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {	131	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
132	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	132	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
133	switch (radeon_connector->hpd.hpd) {	133	switch (radeon_connector->hpd.hpd) {
134	case RADEON_HPD_1:	134	case RADEON_HPD_1:
135	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,	135	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
136	S_007D00_DC_HOT_PLUG_DETECT1_EN(0));	136	S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
137	// rdev->irq.hpd[0] = false;	137	rdev->irq.hpd[0] = false;
138	break;	138	break;
139	case RADEON_HPD_2:	139	case RADEON_HPD_2:
140	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,	140	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
141	S_007D10_DC_HOT_PLUG_DETECT2_EN(0));	141	S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
142	// rdev->irq.hpd[1] = false;	142	rdev->irq.hpd[1] = false;
143	break;	143	break;
144	default:	144	default:
145	break;	145	break;
146	}	146	}
147	}	147	}
148	}	148	}
149		149
150	void rs600_bm_disable(struct radeon_device *rdev)	150	void rs600_bm_disable(struct radeon_device *rdev)
151	{	151	{
152	u32 tmp;	152	u32 tmp;
153		153
154	/* disable bus mastering */	154	/* disable bus mastering */
155	tmp = PciRead16(rdev->pdev->bus, rdev->pdev->devfn, 0x4);	155	tmp = PciRead16(rdev->pdev->bus, rdev->pdev->devfn, 0x4);
156	PciWrite16(rdev->pdev->bus, rdev->pdev->devfn, 0x4, tmp & 0xFFFB);	156	PciWrite16(rdev->pdev->bus, rdev->pdev->devfn, 0x4, tmp & 0xFFFB);
157	mdelay(1);	157	mdelay(1);
158	}	158	}
159		159
160	int rs600_asic_reset(struct radeon_device *rdev)	160	int rs600_asic_reset(struct radeon_device *rdev)
161	{	161	{
162	struct rv515_mc_save save;	162	struct rv515_mc_save save;
163	u32 status, tmp;	163	u32 status, tmp;
164	int ret = 0;	164	int ret = 0;
165		165
166	status = RREG32(R_000E40_RBBM_STATUS);	166	status = RREG32(R_000E40_RBBM_STATUS);
167	if (!G_000E40_GUI_ACTIVE(status)) {	167	if (!G_000E40_GUI_ACTIVE(status)) {
168	return 0;	168	return 0;
169	}	169	}
170	/* Stops all mc clients */	170	/* Stops all mc clients */
171	rv515_mc_stop(rdev, &save);	171	rv515_mc_stop(rdev, &save);
172	status = RREG32(R_000E40_RBBM_STATUS);	172	status = RREG32(R_000E40_RBBM_STATUS);
173	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	173	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
174	/* stop CP */	174	/* stop CP */
175	WREG32(RADEON_CP_CSQ_CNTL, 0);	175	WREG32(RADEON_CP_CSQ_CNTL, 0);
176	tmp = RREG32(RADEON_CP_RB_CNTL);	176	tmp = RREG32(RADEON_CP_RB_CNTL);
177	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);	177	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
178	WREG32(RADEON_CP_RB_RPTR_WR, 0);	178	WREG32(RADEON_CP_RB_RPTR_WR, 0);
179	WREG32(RADEON_CP_RB_WPTR, 0);	179	WREG32(RADEON_CP_RB_WPTR, 0);
180	WREG32(RADEON_CP_RB_CNTL, tmp);	180	WREG32(RADEON_CP_RB_CNTL, tmp);
181	// pci_save_state(rdev->pdev);	181	// pci_save_state(rdev->pdev);
182	/* disable bus mastering */	182	/* disable bus mastering */
183	rs600_bm_disable(rdev);	183	rs600_bm_disable(rdev);
184	/* reset GA+VAP */	184	/* reset GA+VAP */
185	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) \|	185	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) \|
186	S_0000F0_SOFT_RESET_GA(1));	186	S_0000F0_SOFT_RESET_GA(1));
187	RREG32(R_0000F0_RBBM_SOFT_RESET);	187	RREG32(R_0000F0_RBBM_SOFT_RESET);
188	mdelay(500);	188	mdelay(500);
189	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);	189	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
190	mdelay(1);	190	mdelay(1);
191	status = RREG32(R_000E40_RBBM_STATUS);	191	status = RREG32(R_000E40_RBBM_STATUS);
192	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	192	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
193	/* reset CP */	193	/* reset CP */
194	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));	194	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
195	RREG32(R_0000F0_RBBM_SOFT_RESET);	195	RREG32(R_0000F0_RBBM_SOFT_RESET);
196	mdelay(500);	196	mdelay(500);
197	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);	197	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
198	mdelay(1);	198	mdelay(1);
199	status = RREG32(R_000E40_RBBM_STATUS);	199	status = RREG32(R_000E40_RBBM_STATUS);
200	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	200	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
201	/* reset MC */	201	/* reset MC */
202	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));	202	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
203	RREG32(R_0000F0_RBBM_SOFT_RESET);	203	RREG32(R_0000F0_RBBM_SOFT_RESET);
204	mdelay(500);	204	mdelay(500);
205	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);	205	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
206	mdelay(1);	206	mdelay(1);
207	status = RREG32(R_000E40_RBBM_STATUS);	207	status = RREG32(R_000E40_RBBM_STATUS);
208	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	208	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
209	/* restore PCI & busmastering */	209	/* restore PCI & busmastering */
210	// pci_restore_state(rdev->pdev);	210	// pci_restore_state(rdev->pdev);
211	/* Check if GPU is idle */	211	/* Check if GPU is idle */
212	if (G_000E40_GA_BUSY(status) \|\| G_000E40_VAP_BUSY(status)) {	212	if (G_000E40_GA_BUSY(status) \|\| G_000E40_VAP_BUSY(status)) {
213	dev_err(rdev->dev, "failed to reset GPU\n");	213	dev_err(rdev->dev, "failed to reset GPU\n");
214	rdev->gpu_lockup = true;	214	rdev->gpu_lockup = true;
215	ret = -1;	215	ret = -1;
216	} else	216	} else
217	dev_info(rdev->dev, "GPU reset succeed\n");	217	dev_info(rdev->dev, "GPU reset succeed\n");
218	rv515_mc_resume(rdev, &save);	218	rv515_mc_resume(rdev, &save);
219	return ret;	219	return ret;
220	}	220	}
221		221
222	/*	222	/*
223	* GART.	223	* GART.
224	*/	224	*/
225	void rs600_gart_tlb_flush(struct radeon_device *rdev)	225	void rs600_gart_tlb_flush(struct radeon_device *rdev)
226	{	226	{
227	uint32_t tmp;	227	uint32_t tmp;
228		228
229	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	229	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
230	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;	230	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
231	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);	231	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
232		232
233	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	233	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
234	tmp \|= S_000100_INVALIDATE_ALL_L1_TLBS(1) \| S_000100_INVALIDATE_L2_CACHE(1);	234	tmp \|= S_000100_INVALIDATE_ALL_L1_TLBS(1) \| S_000100_INVALIDATE_L2_CACHE(1);
235	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);	235	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
236		236
237	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	237	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
238	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;	238	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
239	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);	239	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
240	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	240	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
241	}	241	}
242		242
243	int rs600_gart_init(struct radeon_device *rdev)	243	int rs600_gart_init(struct radeon_device *rdev)
244	{	244	{
245	int r;	245	int r;
246		246
247	if (rdev->gart.table.vram.robj) {	247	if (rdev->gart.table.vram.robj) {
248	WARN(1, "RS600 GART already initialized\n");	248	WARN(1, "RS600 GART already initialized\n");
249	return 0;	249	return 0;
250	}	250	}
251	/* Initialize common gart structure */	251	/* Initialize common gart structure */
252	r = radeon_gart_init(rdev);	252	r = radeon_gart_init(rdev);
253	if (r) {	253	if (r) {
254	return r;	254	return r;
255	}	255	}
256	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;	256	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
257	return radeon_gart_table_vram_alloc(rdev);	257	return radeon_gart_table_vram_alloc(rdev);
258	}	258	}
259		259
260	int rs600_gart_enable(struct radeon_device *rdev)	260	static int rs600_gart_enable(struct radeon_device *rdev)
261	{	261	{
262	u32 tmp;	262	u32 tmp;
263	int r, i;	263	int r, i;
264		264
265	if (rdev->gart.table.vram.robj == NULL) {	265	if (rdev->gart.table.vram.robj == NULL) {
266	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");	266	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
267	return -EINVAL;	267	return -EINVAL;
268	}	268	}
269	r = radeon_gart_table_vram_pin(rdev);	269	r = radeon_gart_table_vram_pin(rdev);
270	if (r)	270	if (r)
271	return r;	271	return r;
272	radeon_gart_restore(rdev);	272	radeon_gart_restore(rdev);
273	/* Enable bus master */	273	/* Enable bus master */
274	tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;	274	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
275	WREG32(R_00004C_BUS_CNTL, tmp);	275	WREG32(RADEON_BUS_CNTL, tmp);
276	/* FIXME: setup default page */	276	/* FIXME: setup default page */
277	WREG32_MC(R_000100_MC_PT0_CNTL,	277	WREG32_MC(R_000100_MC_PT0_CNTL,
278	(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) \|	278	(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) \|
279	S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));	279	S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
280		280
281	for (i = 0; i < 19; i++) {	281	for (i = 0; i < 19; i++) {
282	WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,	282	WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
283	S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) \|	283	S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) \|
284	S_00016C_SYSTEM_ACCESS_MODE_MASK(	284	S_00016C_SYSTEM_ACCESS_MODE_MASK(
285	V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) \|	285	V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) \|
286	S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(	286	S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
287	V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) \|	287	V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) \|
288	S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) \|	288	S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) \|
289	S_00016C_ENABLE_FRAGMENT_PROCESSING(1) \|	289	S_00016C_ENABLE_FRAGMENT_PROCESSING(1) \|
290	S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));	290	S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
291	}	291	}
292	/* enable first context */	292	/* enable first context */
293	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,	293	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
294	S_000102_ENABLE_PAGE_TABLE(1) \|	294	S_000102_ENABLE_PAGE_TABLE(1) \|
295	S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));	295	S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
296		296
297	/* disable all other contexts */	297	/* disable all other contexts */
298	for (i = 1; i < 8; i++)	298	for (i = 1; i < 8; i++)
299	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);	299	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
300		300
301	/* setup the page table */	301	/* setup the page table */
302	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,	302	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
303	rdev->gart.table_addr);	303	rdev->gart.table_addr);
304	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);	304	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
305	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);	305	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
306	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);	306	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
307		307
308	/* System context maps to VRAM space */	308	/* System context maps to VRAM space */
309	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);	309	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
310	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);	310	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
311		311
312	/* enable page tables */	312	/* enable page tables */
313	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	313	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
314	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp \| S_000100_ENABLE_PT(1)));	314	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp \| S_000100_ENABLE_PT(1)));
315	tmp = RREG32_MC(R_000009_MC_CNTL1);	315	tmp = RREG32_MC(R_000009_MC_CNTL1);
316	WREG32_MC(R_000009_MC_CNTL1, (tmp \| S_000009_ENABLE_PAGE_TABLES(1)));	316	WREG32_MC(R_000009_MC_CNTL1, (tmp \| S_000009_ENABLE_PAGE_TABLES(1)));
317	rs600_gart_tlb_flush(rdev);	317	rs600_gart_tlb_flush(rdev);
318	rdev->gart.ready = true;	318	rdev->gart.ready = true;
319	return 0;	319	return 0;
320	}	320	}
321		321
322	void rs600_gart_disable(struct radeon_device *rdev)	322	void rs600_gart_disable(struct radeon_device *rdev)
323	{	323	{
324	u32 tmp;	324	u32 tmp;
325	int r;	325	int r;
326		326
327	/* FIXME: disable out of gart access */	327	/* FIXME: disable out of gart access */
328	WREG32_MC(R_000100_MC_PT0_CNTL, 0);	328	WREG32_MC(R_000100_MC_PT0_CNTL, 0);
329	tmp = RREG32_MC(R_000009_MC_CNTL1);	329	tmp = RREG32_MC(R_000009_MC_CNTL1);
330	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);	330	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
331	if (rdev->gart.table.vram.robj) {	331	if (rdev->gart.table.vram.robj) {
332	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);	332	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
333	if (r == 0) {	333	if (r == 0) {
334	radeon_bo_kunmap(rdev->gart.table.vram.robj);	334	radeon_bo_kunmap(rdev->gart.table.vram.robj);
335	radeon_bo_unpin(rdev->gart.table.vram.robj);	335	radeon_bo_unpin(rdev->gart.table.vram.robj);
336	radeon_bo_unreserve(rdev->gart.table.vram.robj);	336	radeon_bo_unreserve(rdev->gart.table.vram.robj);
337	}	337	}
338	}	338	}
339	}	339	}
340		340
341	void rs600_gart_fini(struct radeon_device *rdev)	341	void rs600_gart_fini(struct radeon_device *rdev)
342	{	342	{
343	radeon_gart_fini(rdev);	343	radeon_gart_fini(rdev);
344	rs600_gart_disable(rdev);	344	rs600_gart_disable(rdev);
345	radeon_gart_table_vram_free(rdev);	345	radeon_gart_table_vram_free(rdev);
346	}	346	}
347		347
348	#define R600_PTE_VALID (1 << 0)	348	#define R600_PTE_VALID (1 << 0)
349	#define R600_PTE_SYSTEM (1 << 1)	349	#define R600_PTE_SYSTEM (1 << 1)
350	#define R600_PTE_SNOOPED (1 << 2)	350	#define R600_PTE_SNOOPED (1 << 2)
351	#define R600_PTE_READABLE (1 << 5)	351	#define R600_PTE_READABLE (1 << 5)
352	#define R600_PTE_WRITEABLE (1 << 6)	352	#define R600_PTE_WRITEABLE (1 << 6)
353		353
354	int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)	354	int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
355	{	355	{
356	void __iomem ptr = (void )rdev->gart.table.vram.ptr;	356	void __iomem ptr = (void )rdev->gart.table.vram.ptr;
357		357
358	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {	358	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
359	return -EINVAL;	359	return -EINVAL;
360	}	360	}
361	addr = addr & 0xFFFFFFFFFFFFF000ULL;	361	addr = addr & 0xFFFFFFFFFFFFF000ULL;
362	addr \|= R600_PTE_VALID \| R600_PTE_SYSTEM \| R600_PTE_SNOOPED;	362	addr \|= R600_PTE_VALID \| R600_PTE_SYSTEM \| R600_PTE_SNOOPED;
363	addr \|= R600_PTE_READABLE \| R600_PTE_WRITEABLE;	363	addr \|= R600_PTE_READABLE \| R600_PTE_WRITEABLE;
364	writeq(addr, ((void __iomem )ptr) + (i 8));	364	writeq(addr, ((void __iomem )ptr) + (i 8));
365	return 0;	365	return 0;
366	}	366	}
367		-
368	#if 0	-
369		367
370	int rs600_irq_set(struct radeon_device *rdev)	368	int rs600_irq_set(struct radeon_device *rdev)
371	{	369	{
372	uint32_t tmp = 0;	370	uint32_t tmp = 0;
373	uint32_t mode_int = 0;	371	uint32_t mode_int = 0;
374	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &	372	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
375	~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);	373	~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
376	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &	374	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
377	~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);	375	~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
378		376
379	if (!rdev->irq.installed) {	377	if (!rdev->irq.installed) {
380	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");	378	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
381	WREG32(R_000040_GEN_INT_CNTL, 0);	379	WREG32(R_000040_GEN_INT_CNTL, 0);
382	return -EINVAL;	380	return -EINVAL;
383	}	381	}
384	if (rdev->irq.sw_int) {	382	if (rdev->irq.sw_int) {
385	tmp \|= S_000040_SW_INT_EN(1);	383	tmp \|= S_000040_SW_INT_EN(1);
386	}	384	}
387	if (rdev->irq.gui_idle) {	385	if (rdev->irq.gui_idle) {
388	tmp \|= S_000040_GUI_IDLE(1);	386	tmp \|= S_000040_GUI_IDLE(1);
389	}	387	}
390	if (rdev->irq.crtc_vblank_int[0] \|\|	388	if (rdev->irq.crtc_vblank_int[0] \|\|
391	rdev->irq.pflip[0]) {	389	rdev->irq.pflip[0]) {
392	mode_int \|= S_006540_D1MODE_VBLANK_INT_MASK(1);	390	mode_int \|= S_006540_D1MODE_VBLANK_INT_MASK(1);
393	}	391	}
394	if (rdev->irq.crtc_vblank_int[1] \|\|	392	if (rdev->irq.crtc_vblank_int[1] \|\|
395	rdev->irq.pflip[1]) {	393	rdev->irq.pflip[1]) {
396	mode_int \|= S_006540_D2MODE_VBLANK_INT_MASK(1);	394	mode_int \|= S_006540_D2MODE_VBLANK_INT_MASK(1);
397	}	395	}
398	if (rdev->irq.hpd[0]) {	396	if (rdev->irq.hpd[0]) {
399	hpd1 \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);	397	hpd1 \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
400	}	398	}
401	if (rdev->irq.hpd[1]) {	399	if (rdev->irq.hpd[1]) {
402	hpd2 \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);	400	hpd2 \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
403	}	401	}
404	WREG32(R_000040_GEN_INT_CNTL, tmp);	402	WREG32(R_000040_GEN_INT_CNTL, tmp);
405	WREG32(R_006540_DxMODE_INT_MASK, mode_int);	403	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
406	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);	404	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
407	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);	405	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
408	return 0;	406	return 0;
409	}	407	}
410		408
411	static inline u32 rs600_irq_ack(struct radeon_device *rdev)	409	static inline u32 rs600_irq_ack(struct radeon_device *rdev)
412	{	410	{
413	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);	411	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
414	uint32_t irq_mask = S_000044_SW_INT(1);	412	uint32_t irq_mask = S_000044_SW_INT(1);
415	u32 tmp;	413	u32 tmp;
416		414
417	/* the interrupt works, but the status bit is permanently asserted */	415	/* the interrupt works, but the status bit is permanently asserted */
418	if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {	416	if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
419	if (!rdev->irq.gui_idle_acked)	417	if (!rdev->irq.gui_idle_acked)
420	irq_mask \|= S_000044_GUI_IDLE_STAT(1);	418	irq_mask \|= S_000044_GUI_IDLE_STAT(1);
421	}	419	}
422		420
423	if (G_000044_DISPLAY_INT_STAT(irqs)) {	421	if (G_000044_DISPLAY_INT_STAT(irqs)) {
424	rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);	422	rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
425	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	423	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
426	WREG32(R_006534_D1MODE_VBLANK_STATUS,	424	WREG32(R_006534_D1MODE_VBLANK_STATUS,
427	S_006534_D1MODE_VBLANK_ACK(1));	425	S_006534_D1MODE_VBLANK_ACK(1));
428	}	426	}
429	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	427	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
430	WREG32(R_006D34_D2MODE_VBLANK_STATUS,	428	WREG32(R_006D34_D2MODE_VBLANK_STATUS,
431	S_006D34_D2MODE_VBLANK_ACK(1));	429	S_006D34_D2MODE_VBLANK_ACK(1));
432	}	430	}
433	if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	431	if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
434	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);	432	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
435	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);	433	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
436	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);	434	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
437	}	435	}
438	if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	436	if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
439	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);	437	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
440	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);	438	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
441	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);	439	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
442	}	440	}
443	} else {	441	} else {
444	rdev->irq.stat_regs.r500.disp_int = 0;	442	rdev->irq.stat_regs.r500.disp_int = 0;
445	}	443	}
446		444
447	if (irqs) {	445	if (irqs) {
448	WREG32(R_000044_GEN_INT_STATUS, irqs);	446	WREG32(R_000044_GEN_INT_STATUS, irqs);
449	}	447	}
450	return irqs & irq_mask;	448	return irqs & irq_mask;
451	}	449	}
452		450
453	void rs600_irq_disable(struct radeon_device *rdev)	451	void rs600_irq_disable(struct radeon_device *rdev)
454	{	452	{
455	WREG32(R_000040_GEN_INT_CNTL, 0);	453	WREG32(R_000040_GEN_INT_CNTL, 0);
456	WREG32(R_006540_DxMODE_INT_MASK, 0);	454	WREG32(R_006540_DxMODE_INT_MASK, 0);
457	/* Wait and acknowledge irq */	455	/* Wait and acknowledge irq */
458	mdelay(1);	456	mdelay(1);
459	rs600_irq_ack(rdev);	457	rs600_irq_ack(rdev);
460	}	458	}
-		459
-		460	int rs600_irq_process(struct radeon_device *rdev)
-		461	{
-		462	u32 status, msi_rearm;
-		463	bool queue_hotplug = false;
-		464
-		465	/* reset gui idle ack. the status bit is broken */
-		466	rdev->irq.gui_idle_acked = false;
-		467
-		468	status = rs600_irq_ack(rdev);
-		469	if (!status && !rdev->irq.stat_regs.r500.disp_int) {
-		470	return IRQ_NONE;
-		471	}
-		472	while (status \|\| rdev->irq.stat_regs.r500.disp_int) {
-		473	/* SW interrupt */
-		474	if (G_000044_SW_INT(status)) {
-		475	radeon_fence_process(rdev);
-		476	}
-		477	/* GUI idle */
-		478	if (G_000040_GUI_IDLE(status)) {
-		479	rdev->irq.gui_idle_acked = true;
-		480	rdev->pm.gui_idle = true;
-		481	// wake_up(&rdev->irq.idle_queue);
-		482	}
-		483	/* Vertical blank interrupts */
-		484	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
-		485	if (rdev->irq.crtc_vblank_int[0]) {
-		486	// drm_handle_vblank(rdev->ddev, 0);
-		487	rdev->pm.vblank_sync = true;
-		488	// wake_up(&rdev->irq.vblank_queue);
-		489	}
-		490	// if (rdev->irq.pflip[0])
-		491	// radeon_crtc_handle_flip(rdev, 0);
-		492	}
-		493	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
-		494	if (rdev->irq.crtc_vblank_int[1]) {
-		495	// drm_handle_vblank(rdev->ddev, 1);
-		496	rdev->pm.vblank_sync = true;
461		497	// wake_up(&rdev->irq.vblank_queue);
-		498	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/rs600.c – Rev 1963 → 2005