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Rev 1963 | Rev 2005 | ||
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Line 106... | Line 106... | ||
106 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
106 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
107 | switch (radeon_connector->hpd.hpd) { |
107 | switch (radeon_connector->hpd.hpd) { |
108 | case RADEON_HPD_1: |
108 | case RADEON_HPD_1: |
109 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
109 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
110 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
110 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
111 | // rdev->irq.hpd[0] = true; |
111 | rdev->irq.hpd[0] = true; |
112 | break; |
112 | break; |
113 | case RADEON_HPD_2: |
113 | case RADEON_HPD_2: |
114 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
114 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
115 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
115 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
116 | // rdev->irq.hpd[1] = true; |
116 | rdev->irq.hpd[1] = true; |
117 | break; |
117 | break; |
118 | default: |
118 | default: |
119 | break; |
119 | break; |
120 | } |
120 | } |
121 | } |
121 | } |
122 | // if (rdev->irq.installed) |
122 | if (rdev->irq.installed) |
123 | // rs600_irq_set(rdev); |
123 | rs600_irq_set(rdev); |
124 | } |
124 | } |
Line 125... | Line 125... | ||
125 | 125 | ||
126 | void rs600_hpd_fini(struct radeon_device *rdev) |
126 | void rs600_hpd_fini(struct radeon_device *rdev) |
127 | { |
127 | { |
Line 132... | Line 132... | ||
132 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
132 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
133 | switch (radeon_connector->hpd.hpd) { |
133 | switch (radeon_connector->hpd.hpd) { |
134 | case RADEON_HPD_1: |
134 | case RADEON_HPD_1: |
135 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
135 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
136 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
136 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
137 | // rdev->irq.hpd[0] = false; |
137 | rdev->irq.hpd[0] = false; |
138 | break; |
138 | break; |
139 | case RADEON_HPD_2: |
139 | case RADEON_HPD_2: |
140 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
140 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
141 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
141 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
142 | // rdev->irq.hpd[1] = false; |
142 | rdev->irq.hpd[1] = false; |
143 | break; |
143 | break; |
144 | default: |
144 | default: |
145 | break; |
145 | break; |
146 | } |
146 | } |
147 | } |
147 | } |
Line 255... | Line 255... | ||
255 | } |
255 | } |
256 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
256 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
257 | return radeon_gart_table_vram_alloc(rdev); |
257 | return radeon_gart_table_vram_alloc(rdev); |
258 | } |
258 | } |
Line 259... | Line 259... | ||
259 | 259 | ||
260 | int rs600_gart_enable(struct radeon_device *rdev) |
260 | static int rs600_gart_enable(struct radeon_device *rdev) |
261 | { |
261 | { |
262 | u32 tmp; |
262 | u32 tmp; |
Line 263... | Line 263... | ||
263 | int r, i; |
263 | int r, i; |
Line 269... | Line 269... | ||
269 | r = radeon_gart_table_vram_pin(rdev); |
269 | r = radeon_gart_table_vram_pin(rdev); |
270 | if (r) |
270 | if (r) |
271 | return r; |
271 | return r; |
272 | radeon_gart_restore(rdev); |
272 | radeon_gart_restore(rdev); |
273 | /* Enable bus master */ |
273 | /* Enable bus master */ |
274 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; |
274 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
275 | WREG32(R_00004C_BUS_CNTL, tmp); |
275 | WREG32(RADEON_BUS_CNTL, tmp); |
276 | /* FIXME: setup default page */ |
276 | /* FIXME: setup default page */ |
277 | WREG32_MC(R_000100_MC_PT0_CNTL, |
277 | WREG32_MC(R_000100_MC_PT0_CNTL, |
278 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
278 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
279 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
279 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
Line 363... | Line 363... | ||
363 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
363 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
364 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
364 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
365 | return 0; |
365 | return 0; |
366 | } |
366 | } |
Line 367... | Line -... | ||
367 | - | ||
368 | #if 0 |
- | |
369 | 367 | ||
370 | int rs600_irq_set(struct radeon_device *rdev) |
368 | int rs600_irq_set(struct radeon_device *rdev) |
371 | { |
369 | { |
372 | uint32_t tmp = 0; |
370 | uint32_t tmp = 0; |
373 | uint32_t mode_int = 0; |
371 | uint32_t mode_int = 0; |
Line 457... | Line 455... | ||
457 | /* Wait and acknowledge irq */ |
455 | /* Wait and acknowledge irq */ |
458 | mdelay(1); |
456 | mdelay(1); |
459 | rs600_irq_ack(rdev); |
457 | rs600_irq_ack(rdev); |
460 | } |
458 | } |
Line -... | Line 459... | ||
- | 459 | ||
- | 460 | int rs600_irq_process(struct radeon_device *rdev) |
|
- | 461 | { |
|
- | 462 | u32 status, msi_rearm; |
|
- | 463 | bool queue_hotplug = false; |
|
- | 464 | ||
- | 465 | /* reset gui idle ack. the status bit is broken */ |
|
- | 466 | rdev->irq.gui_idle_acked = false; |
|
- | 467 | ||
- | 468 | status = rs600_irq_ack(rdev); |
|
- | 469 | if (!status && !rdev->irq.stat_regs.r500.disp_int) { |
|
- | 470 | return IRQ_NONE; |
|
- | 471 | } |
|
- | 472 | while (status || rdev->irq.stat_regs.r500.disp_int) { |
|
- | 473 | /* SW interrupt */ |
|
- | 474 | if (G_000044_SW_INT(status)) { |
|
- | 475 | radeon_fence_process(rdev); |
|
- | 476 | } |
|
- | 477 | /* GUI idle */ |
|
- | 478 | if (G_000040_GUI_IDLE(status)) { |
|
- | 479 | rdev->irq.gui_idle_acked = true; |
|
- | 480 | rdev->pm.gui_idle = true; |
|
- | 481 | // wake_up(&rdev->irq.idle_queue); |
|
- | 482 | } |
|
- | 483 | /* Vertical blank interrupts */ |
|
- | 484 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
|
- | 485 | if (rdev->irq.crtc_vblank_int[0]) { |
|
- | 486 | // drm_handle_vblank(rdev->ddev, 0); |
|
- | 487 | rdev->pm.vblank_sync = true; |
|
- | 488 | // wake_up(&rdev->irq.vblank_queue); |
|
- | 489 | } |
|
- | 490 | // if (rdev->irq.pflip[0]) |
|
- | 491 | // radeon_crtc_handle_flip(rdev, 0); |
|
- | 492 | } |
|
- | 493 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
|
- | 494 | if (rdev->irq.crtc_vblank_int[1]) { |
|
- | 495 | // drm_handle_vblank(rdev->ddev, 1); |
|
- | 496 | rdev->pm.vblank_sync = true; |
|
461 | 497 | // wake_up(&rdev->irq.vblank_queue); |
|
- | 498 | } |
|
- | 499 | // if (rdev->irq.pflip[1]) |
|
- | 500 | // radeon_crtc_handle_flip(rdev, 1); |
|
- | 501 | } |
|
- | 502 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
|
- | 503 | queue_hotplug = true; |
|
- | 504 | DRM_DEBUG("HPD1\n"); |
|
- | 505 | } |
|
- | 506 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
|
- | 507 | queue_hotplug = true; |
|
- | 508 | DRM_DEBUG("HPD2\n"); |
|
- | 509 | } |
|
- | 510 | status = rs600_irq_ack(rdev); |
|
- | 511 | } |
|
- | 512 | /* reset gui idle ack. the status bit is broken */ |
|
- | 513 | rdev->irq.gui_idle_acked = false; |
|
- | 514 | // if (queue_hotplug) |
|
- | 515 | // schedule_work(&rdev->hotplug_work); |
|
- | 516 | if (rdev->msi_enabled) { |
|
- | 517 | switch (rdev->family) { |
|
- | 518 | case CHIP_RS600: |
|
- | 519 | case CHIP_RS690: |
|
- | 520 | case CHIP_RS740: |
|
- | 521 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
|
- | 522 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
|
- | 523 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
|
- | 524 | break; |
|
- | 525 | default: |
|
- | 526 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; |
|
- | 527 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); |
|
- | 528 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); |
|
- | 529 | break; |
|
- | 530 | } |
|
- | 531 | } |
|
- | 532 | return IRQ_HANDLED; |
|
Line 462... | Line 533... | ||
462 | #endif |
533 | } |
463 | 534 | ||
464 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
535 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
465 | { |
536 | { |
Line 600... | Line 671... | ||
600 | /* Initialize GART (initialize after TTM so we can allocate |
671 | /* Initialize GART (initialize after TTM so we can allocate |
601 | * memory through TTM but finalize after TTM) */ |
672 | * memory through TTM but finalize after TTM) */ |
602 | r = rs600_gart_enable(rdev); |
673 | r = rs600_gart_enable(rdev); |
603 | if (r) |
674 | if (r) |
604 | return r; |
675 | return r; |
- | 676 | ||
- | 677 | /* allocate wb buffer */ |
|
- | 678 | r = radeon_wb_init(rdev); |
|
- | 679 | if (r) |
|
- | 680 | return r; |
|
- | 681 | ||
605 | /* Enable IRQ */ |
682 | /* Enable IRQ */ |
606 | // rs600_irq_set(rdev); |
683 | rs600_irq_set(rdev); |
607 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
684 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
608 | /* 1M ring buffer */ |
685 | /* 1M ring buffer */ |
609 | r = r100_cp_init(rdev, 1024 * 1024); |
686 | r = r100_cp_init(rdev, 1024 * 1024); |
610 | if (r) { |
687 | if (r) { |
611 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
688 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
612 | return r; |
689 | return r; |
613 | } |
690 | } |
614 | // r = r100_ib_init(rdev); |
691 | r = r100_ib_init(rdev); |
615 | // if (r) { |
692 | if (r) { |
616 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
693 | dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
617 | // return r; |
694 | return r; |
618 | // } |
695 | } |
619 | return 0; |
696 | return 0; |
620 | } |
697 | } |
Line 661... | Line 738... | ||
661 | radeon_get_clock_info(rdev->ddev); |
738 | radeon_get_clock_info(rdev->ddev); |
662 | /* initialize memory controller */ |
739 | /* initialize memory controller */ |
663 | rs600_mc_init(rdev); |
740 | rs600_mc_init(rdev); |
664 | rs600_debugfs(rdev); |
741 | rs600_debugfs(rdev); |
665 | /* Fence driver */ |
742 | /* Fence driver */ |
666 | // r = radeon_fence_driver_init(rdev); |
743 | r = radeon_fence_driver_init(rdev); |
667 | // if (r) |
744 | if (r) |
668 | // return r; |
745 | return r; |
669 | // r = radeon_irq_kms_init(rdev); |
746 | r = radeon_irq_kms_init(rdev); |
670 | // if (r) |
747 | if (r) |
671 | // return r; |
748 | return r; |
672 | /* Memory manager */ |
749 | /* Memory manager */ |
673 | r = radeon_bo_init(rdev); |
750 | r = radeon_bo_init(rdev); |
674 | if (r) |
751 | if (r) |
675 | return r; |
752 | return r; |
676 | r = rs600_gart_init(rdev); |
753 | r = rs600_gart_init(rdev); |