Rev 1430 | Rev 2005 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1430 | Rev 1963 | ||
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Line 35... | Line 35... | ||
35 | * close to the one of the R600 family (R600 likely being an evolution |
35 | * close to the one of the R600 family (R600 likely being an evolution |
36 | * of the RS600 GART block). |
36 | * of the RS600 GART block). |
37 | */ |
37 | */ |
38 | #include "drmP.h" |
38 | #include "drmP.h" |
39 | #include "radeon.h" |
39 | #include "radeon.h" |
- | 40 | #include "radeon_asic.h" |
|
40 | #include "atom.h" |
41 | #include "atom.h" |
41 | #include "rs600d.h" |
42 | #include "rs600d.h" |
Line 42... | Line 43... | ||
42 | 43 | ||
Line 144... | Line 145... | ||
144 | break; |
145 | break; |
145 | } |
146 | } |
146 | } |
147 | } |
147 | } |
148 | } |
Line -... | Line 149... | ||
- | 149 | ||
- | 150 | void rs600_bm_disable(struct radeon_device *rdev) |
|
- | 151 | { |
|
- | 152 | u32 tmp; |
|
- | 153 | ||
- | 154 | /* disable bus mastering */ |
|
- | 155 | tmp = PciRead16(rdev->pdev->bus, rdev->pdev->devfn, 0x4); |
|
- | 156 | PciWrite16(rdev->pdev->bus, rdev->pdev->devfn, 0x4, tmp & 0xFFFB); |
|
- | 157 | mdelay(1); |
|
- | 158 | } |
|
- | 159 | ||
- | 160 | int rs600_asic_reset(struct radeon_device *rdev) |
|
- | 161 | { |
|
- | 162 | struct rv515_mc_save save; |
|
- | 163 | u32 status, tmp; |
|
- | 164 | int ret = 0; |
|
- | 165 | ||
- | 166 | status = RREG32(R_000E40_RBBM_STATUS); |
|
- | 167 | if (!G_000E40_GUI_ACTIVE(status)) { |
|
- | 168 | return 0; |
|
- | 169 | } |
|
- | 170 | /* Stops all mc clients */ |
|
- | 171 | rv515_mc_stop(rdev, &save); |
|
- | 172 | status = RREG32(R_000E40_RBBM_STATUS); |
|
- | 173 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
|
- | 174 | /* stop CP */ |
|
- | 175 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
|
- | 176 | tmp = RREG32(RADEON_CP_RB_CNTL); |
|
- | 177 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
|
- | 178 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
|
- | 179 | WREG32(RADEON_CP_RB_WPTR, 0); |
|
- | 180 | WREG32(RADEON_CP_RB_CNTL, tmp); |
|
- | 181 | // pci_save_state(rdev->pdev); |
|
- | 182 | /* disable bus mastering */ |
|
- | 183 | rs600_bm_disable(rdev); |
|
- | 184 | /* reset GA+VAP */ |
|
- | 185 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
|
- | 186 | S_0000F0_SOFT_RESET_GA(1)); |
|
- | 187 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
|
- | 188 | mdelay(500); |
|
- | 189 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
|
- | 190 | mdelay(1); |
|
- | 191 | status = RREG32(R_000E40_RBBM_STATUS); |
|
- | 192 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
|
- | 193 | /* reset CP */ |
|
- | 194 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
|
- | 195 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
|
- | 196 | mdelay(500); |
|
- | 197 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
|
- | 198 | mdelay(1); |
|
- | 199 | status = RREG32(R_000E40_RBBM_STATUS); |
|
- | 200 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
|
- | 201 | /* reset MC */ |
|
- | 202 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); |
|
- | 203 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
|
- | 204 | mdelay(500); |
|
- | 205 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
|
- | 206 | mdelay(1); |
|
- | 207 | status = RREG32(R_000E40_RBBM_STATUS); |
|
- | 208 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
|
- | 209 | /* restore PCI & busmastering */ |
|
- | 210 | // pci_restore_state(rdev->pdev); |
|
- | 211 | /* Check if GPU is idle */ |
|
- | 212 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
|
- | 213 | dev_err(rdev->dev, "failed to reset GPU\n"); |
|
- | 214 | rdev->gpu_lockup = true; |
|
- | 215 | ret = -1; |
|
- | 216 | } else |
|
- | 217 | dev_info(rdev->dev, "GPU reset succeed\n"); |
|
- | 218 | rv515_mc_resume(rdev, &save); |
|
- | 219 | return ret; |
|
- | 220 | } |
|
148 | 221 | ||
149 | /* |
222 | /* |
150 | * GART. |
223 | * GART. |
151 | */ |
224 | */ |
152 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
225 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
Line 156... | Line 229... | ||
156 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
229 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
157 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
230 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
158 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
231 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
Line 159... | Line 232... | ||
159 | 232 | ||
160 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
233 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
161 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); |
234 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
Line 162... | Line 235... | ||
162 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
235 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
163 | 236 | ||
164 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
237 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
Line 170... | Line 243... | ||
170 | int rs600_gart_init(struct radeon_device *rdev) |
243 | int rs600_gart_init(struct radeon_device *rdev) |
171 | { |
244 | { |
172 | int r; |
245 | int r; |
Line 173... | Line 246... | ||
173 | 246 | ||
174 | if (rdev->gart.table.vram.robj) { |
247 | if (rdev->gart.table.vram.robj) { |
175 | WARN(1, "RS600 GART already initialized.\n"); |
248 | WARN(1, "RS600 GART already initialized\n"); |
176 | return 0; |
249 | return 0; |
177 | } |
250 | } |
178 | /* Initialize common gart structure */ |
251 | /* Initialize common gart structure */ |
179 | r = radeon_gart_init(rdev); |
252 | r = radeon_gart_init(rdev); |
Line 265... | Line 338... | ||
265 | } |
338 | } |
266 | } |
339 | } |
Line 267... | Line 340... | ||
267 | 340 | ||
268 | void rs600_gart_fini(struct radeon_device *rdev) |
341 | void rs600_gart_fini(struct radeon_device *rdev) |
- | 342 | { |
|
269 | { |
343 | radeon_gart_fini(rdev); |
270 | rs600_gart_disable(rdev); |
344 | rs600_gart_disable(rdev); |
271 | radeon_gart_table_vram_free(rdev); |
- | |
272 | radeon_gart_fini(rdev); |
345 | radeon_gart_table_vram_free(rdev); |
Line 273... | Line 346... | ||
273 | } |
346 | } |
274 | 347 | ||
275 | #define R600_PTE_VALID (1 << 0) |
348 | #define R600_PTE_VALID (1 << 0) |
Line 290... | Line 363... | ||
290 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
363 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
291 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
364 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
292 | return 0; |
365 | return 0; |
293 | } |
366 | } |
Line -... | Line 367... | ||
- | 367 | ||
294 | 368 | #if 0 |
|
295 | /* |
369 | |
296 | int rs600_irq_set(struct radeon_device *rdev) |
370 | int rs600_irq_set(struct radeon_device *rdev) |
297 | { |
371 | { |
298 | uint32_t tmp = 0; |
372 | uint32_t tmp = 0; |
299 | uint32_t mode_int = 0; |
373 | uint32_t mode_int = 0; |
300 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
374 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
301 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
375 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
302 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
376 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
Line 303... | Line 377... | ||
303 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
377 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
304 | 378 | ||
305 | if (!rdev->irq.installed) { |
379 | if (!rdev->irq.installed) { |
306 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); |
380 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
307 | WREG32(R_000040_GEN_INT_CNTL, 0); |
381 | WREG32(R_000040_GEN_INT_CNTL, 0); |
308 | return -EINVAL; |
382 | return -EINVAL; |
309 | } |
383 | } |
310 | if (rdev->irq.sw_int) { |
384 | if (rdev->irq.sw_int) { |
- | 385 | tmp |= S_000040_SW_INT_EN(1); |
|
- | 386 | } |
|
- | 387 | if (rdev->irq.gui_idle) { |
|
311 | tmp |= S_000040_SW_INT_EN(1); |
388 | tmp |= S_000040_GUI_IDLE(1); |
- | 389 | } |
|
312 | } |
390 | if (rdev->irq.crtc_vblank_int[0] || |
313 | if (rdev->irq.crtc_vblank_int[0]) { |
391 | rdev->irq.pflip[0]) { |
314 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
392 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
- | 393 | } |
|
315 | } |
394 | if (rdev->irq.crtc_vblank_int[1] || |
316 | if (rdev->irq.crtc_vblank_int[1]) { |
395 | rdev->irq.pflip[1]) { |
317 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
396 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
318 | } |
397 | } |
319 | if (rdev->irq.hpd[0]) { |
398 | if (rdev->irq.hpd[0]) { |
Line 326... | Line 405... | ||
326 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
405 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
327 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
406 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
328 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
407 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
329 | return 0; |
408 | return 0; |
330 | } |
409 | } |
331 | */ |
- | |
Line 332... | Line 410... | ||
332 | 410 | ||
333 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) |
411 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
334 | { |
412 | { |
335 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
413 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
336 | uint32_t irq_mask = ~C_000044_SW_INT; |
414 | uint32_t irq_mask = S_000044_SW_INT(1); |
Line -... | Line 415... | ||
- | 415 | u32 tmp; |
|
- | 416 | ||
- | 417 | /* the interrupt works, but the status bit is permanently asserted */ |
|
- | 418 | if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { |
|
- | 419 | if (!rdev->irq.gui_idle_acked) |
|
- | 420 | irq_mask |= S_000044_GUI_IDLE_STAT(1); |
|
337 | u32 tmp; |
421 | } |
338 | 422 | ||
339 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
423 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
340 | *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
424 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
341 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { |
425 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
342 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
426 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
343 | S_006534_D1MODE_VBLANK_ACK(1)); |
427 | S_006534_D1MODE_VBLANK_ACK(1)); |
344 | } |
428 | } |
345 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
429 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
346 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
430 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
347 | S_006D34_D2MODE_VBLANK_ACK(1)); |
431 | S_006D34_D2MODE_VBLANK_ACK(1)); |
348 | } |
432 | } |
349 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) { |
433 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
350 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
434 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
351 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
435 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
352 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
436 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
353 | } |
437 | } |
354 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) { |
438 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
355 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
439 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
356 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
440 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
357 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
441 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
358 | } |
442 | } |
359 | } else { |
443 | } else { |
Line 360... | Line 444... | ||
360 | *r500_disp_int = 0; |
444 | rdev->irq.stat_regs.r500.disp_int = 0; |
361 | } |
445 | } |
362 | 446 | ||
363 | if (irqs) { |
447 | if (irqs) { |
364 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
448 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
Line 365... | Line 449... | ||
365 | } |
449 | } |
366 | return irqs & irq_mask; |
450 | return irqs & irq_mask; |
367 | } |
- | |
368 | - | ||
369 | void rs600_irq_disable(struct radeon_device *rdev) |
451 | } |
370 | { |
452 | |
371 | u32 tmp; |
453 | void rs600_irq_disable(struct radeon_device *rdev) |
372 | 454 | { |
|
373 | WREG32(R_000040_GEN_INT_CNTL, 0); |
455 | WREG32(R_000040_GEN_INT_CNTL, 0); |
374 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
456 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
Line -... | Line 457... | ||
- | 457 | /* Wait and acknowledge irq */ |
|
Line 375... | Line 458... | ||
375 | /* Wait and acknowledge irq */ |
458 | mdelay(1); |
376 | mdelay(1); |
459 | rs600_irq_ack(rdev); |
377 | rs600_irq_ack(rdev, &tmp); |
460 | } |
378 | } |
461 | |
Line 398... | Line 481... | ||
398 | return -1; |
481 | return -1; |
399 | } |
482 | } |
Line 400... | Line 483... | ||
400 | 483 | ||
401 | void rs600_gpu_init(struct radeon_device *rdev) |
484 | void rs600_gpu_init(struct radeon_device *rdev) |
402 | { |
- | |
403 | r100_hdp_reset(rdev); |
485 | { |
404 | r420_pipes_init(rdev); |
486 | r420_pipes_init(rdev); |
405 | /* Wait for mc idle */ |
487 | /* Wait for mc idle */ |
406 | if (rs600_mc_wait_for_idle(rdev)) |
488 | if (rs600_mc_wait_for_idle(rdev)) |
407 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
489 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
Line 408... | Line 490... | ||
408 | } |
490 | } |
409 | 491 | ||
410 | void rs600_mc_init(struct radeon_device *rdev) |
492 | void rs600_mc_init(struct radeon_device *rdev) |
Line 411... | Line 493... | ||
411 | { |
493 | { |
412 | u64 base; |
494 | u64 base; |
413 | 495 | ||
414 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
496 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
415 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
497 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
416 | rdev->mc.vram_is_ddr = true; |
498 | rdev->mc.vram_is_ddr = true; |
417 | rdev->mc.vram_width = 128; |
499 | rdev->mc.vram_width = 128; |
418 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
500 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
419 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
501 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
420 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
502 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
421 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
503 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
- | 504 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
|
422 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
505 | base = G_000004_MC_FB_START(base) << 16; |
- | 506 | radeon_vram_location(rdev, &rdev->mc, base); |
|
423 | base = G_000004_MC_FB_START(base) << 16; |
507 | rdev->mc.gtt_base_align = 0; |
Line 424... | Line 508... | ||
424 | radeon_vram_location(rdev, &rdev->mc, base); |
508 | radeon_gtt_location(rdev, &rdev->mc); |
425 | radeon_gtt_location(rdev, &rdev->mc); |
509 | radeon_update_bandwidth_info(rdev); |
- | 510 | } |
|
- | 511 | ||
- | 512 | void rs600_bandwidth_update(struct radeon_device *rdev) |
|
426 | } |
513 | { |
- | 514 | struct drm_display_mode *mode0 = NULL; |
|
- | 515 | struct drm_display_mode *mode1 = NULL; |
|
- | 516 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
|
- | 517 | /* FIXME: implement full support */ |
|
- | 518 | ||
- | 519 | radeon_update_display_priority(rdev); |
|
- | 520 | ||
- | 521 | if (rdev->mode_info.crtcs[0]->base.enabled) |
|
- | 522 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
|
- | 523 | if (rdev->mode_info.crtcs[1]->base.enabled) |
|
- | 524 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
|
- | 525 | ||
- | 526 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
|
- | 527 | ||
- | 528 | if (rdev->disp_priority == 2) { |
|
- | 529 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
|
- | 530 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
|
- | 531 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
|
- | 532 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
|
- | 533 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
|
427 | 534 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
|
Line 428... | Line 535... | ||
428 | void rs600_bandwidth_update(struct radeon_device *rdev) |
535 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
429 | { |
536 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
430 | /* FIXME: implement, should this be like rs690 ? */ |
537 | } |
Line 499... | Line 606... | ||
499 | // rs600_irq_set(rdev); |
606 | // rs600_irq_set(rdev); |
500 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
607 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
501 | /* 1M ring buffer */ |
608 | /* 1M ring buffer */ |
502 | r = r100_cp_init(rdev, 1024 * 1024); |
609 | r = r100_cp_init(rdev, 1024 * 1024); |
503 | if (r) { |
610 | if (r) { |
504 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
611 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
505 | return r; |
612 | return r; |
506 | } |
613 | } |
507 | // r = r100_wb_init(rdev); |
- | |
508 | // if (r) |
- | |
509 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
- | |
510 | // r = r100_ib_init(rdev); |
614 | // r = r100_ib_init(rdev); |
511 | // if (r) { |
615 | // if (r) { |
512 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
616 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
513 | // return r; |
617 | // return r; |
514 | // } |
618 | // } |
Line 525... | Line 629... | ||
525 | rv515_vga_render_disable(rdev); |
629 | rv515_vga_render_disable(rdev); |
526 | /* Initialize scratch registers */ |
630 | /* Initialize scratch registers */ |
527 | radeon_scratch_init(rdev); |
631 | radeon_scratch_init(rdev); |
528 | /* Initialize surface registers */ |
632 | /* Initialize surface registers */ |
529 | radeon_surface_init(rdev); |
633 | radeon_surface_init(rdev); |
- | 634 | /* restore some register to sane defaults */ |
|
- | 635 | r100_restore_sanity(rdev); |
|
530 | /* BIOS */ |
636 | /* BIOS */ |
531 | if (!radeon_get_bios(rdev)) { |
637 | if (!radeon_get_bios(rdev)) { |
532 | if (ASIC_IS_AVIVO(rdev)) |
638 | if (ASIC_IS_AVIVO(rdev)) |
533 | return -EINVAL; |
639 | return -EINVAL; |
534 | } |
640 | } |
Line 539... | Line 645... | ||
539 | } else { |
645 | } else { |
540 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
646 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
541 | return -EINVAL; |
647 | return -EINVAL; |
542 | } |
648 | } |
543 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
649 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
544 | if (radeon_gpu_reset(rdev)) { |
650 | if (radeon_asic_reset(rdev)) { |
545 | dev_warn(rdev->dev, |
651 | dev_warn(rdev->dev, |
546 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
652 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
547 | RREG32(R_000E40_RBBM_STATUS), |
653 | RREG32(R_000E40_RBBM_STATUS), |
548 | RREG32(R_0007C0_CP_STAT)); |
654 | RREG32(R_0007C0_CP_STAT)); |
549 | } |
655 | } |
Line 551... | Line 657... | ||
551 | if (radeon_boot_test_post_card(rdev) == false) |
657 | if (radeon_boot_test_post_card(rdev) == false) |
552 | return -EINVAL; |
658 | return -EINVAL; |
Line 553... | Line 659... | ||
553 | 659 | ||
554 | /* Initialize clocks */ |
660 | /* Initialize clocks */ |
555 | radeon_get_clock_info(rdev->ddev); |
- | |
556 | /* Initialize power management */ |
- | |
557 | radeon_pm_init(rdev); |
661 | radeon_get_clock_info(rdev->ddev); |
558 | /* initialize memory controller */ |
662 | /* initialize memory controller */ |
559 | rs600_mc_init(rdev); |
663 | rs600_mc_init(rdev); |
560 | rs600_debugfs(rdev); |
664 | rs600_debugfs(rdev); |
561 | /* Fence driver */ |
665 | /* Fence driver */ |