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Rev 1413 Rev 1430
Line 43... Line 43...
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#include "rs600_reg_safe.h"
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#include "rs600_reg_safe.h"
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void rs600_gpu_init(struct radeon_device *rdev);
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void rs600_gpu_init(struct radeon_device *rdev);
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int rs600_mc_wait_for_idle(struct radeon_device *rdev);
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int rs600_mc_init(struct radeon_device *rdev)
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{
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	/* read back the MC value from the hw */
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	int r;
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	u32 tmp;
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	/* Setup GPU memory space */
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	tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
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	rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
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	rdev->mc.gtt_location = 0xffffffffUL;
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	r = radeon_mc_setup(rdev);
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	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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	if (r)
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		return r;
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	return 0;
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}
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int rs600_mc_wait_for_idle(struct radeon_device *rdev);
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/* hpd for digital panel detect/disconnect */
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/* hpd for digital panel detect/disconnect */
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bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
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bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
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{
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{
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		return -EINVAL;
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		return -EINVAL;
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	}
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	}
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	r = radeon_gart_table_vram_pin(rdev);
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	r = radeon_gart_table_vram_pin(rdev);
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	if (r)
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	if (r)
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		return r;
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		return r;
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	radeon_gart_restore(rdev);
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	/* Enable bus master */
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	/* Enable bus master */
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	tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
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	tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
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	WREG32(R_00004C_BUS_CNTL, tmp);
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	WREG32(R_00004C_BUS_CNTL, tmp);
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	/* FIXME: setup default page */
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	/* FIXME: setup default page */
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	WREG32_MC(R_000100_MC_PT0_CNTL,
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	WREG32_MC(R_000100_MC_PT0_CNTL,
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	/* Wait for mc idle */
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	/* Wait for mc idle */
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	if (rs600_mc_wait_for_idle(rdev))
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	if (rs600_mc_wait_for_idle(rdev))
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		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
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		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
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}
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}
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void rs600_vram_info(struct radeon_device *rdev)
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void rs600_mc_init(struct radeon_device *rdev)
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{
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	u64 base;
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	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
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{
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	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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	rdev->mc.vram_is_ddr = true;
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	rdev->mc.vram_is_ddr = true;
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	rdev->mc.vram_width = 128;
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	rdev->mc.vram_width = 128;
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	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
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	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
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	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
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	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
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	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
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	rdev->mc.visible_vram_size = rdev->mc.aper_size;
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	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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	if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
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	base = RREG32_MC(R_000004_MC_FB_LOCATION);
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		rdev->mc.mc_vram_size = rdev->mc.aper_size;
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	base = G_000004_MC_FB_START(base) << 16;
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	if (rdev->mc.real_vram_size > rdev->mc.aper_size)
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	radeon_vram_location(rdev, &rdev->mc, base);
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		rdev->mc.real_vram_size = rdev->mc.aper_size;
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	radeon_gtt_location(rdev, &rdev->mc);
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}
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}
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void rs600_bandwidth_update(struct radeon_device *rdev)
 428 
void rs600_bandwidth_update(struct radeon_device *rdev)
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	/* Initialize clocks */
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	/* Initialize clocks */
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	radeon_get_clock_info(rdev->ddev);
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	radeon_get_clock_info(rdev->ddev);
572 
	/* Initialize power management */
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	/* Initialize power management */
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	radeon_pm_init(rdev);
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574 
	/* Get vram informations */
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575 
	rs600_vram_info(rdev);
 557 
	radeon_pm_init(rdev);
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	/* Initialize memory controller (also test AGP) */
 558 
	/* initialize memory controller */
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	r = rs600_mc_init(rdev);
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578 
	if (r)
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579 
		return r;
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	rs600_mc_init(rdev);
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	rs600_debugfs(rdev);
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	rs600_debugfs(rdev);
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	/* Fence driver */
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	/* Fence driver */
582 
//	r = radeon_fence_driver_init(rdev);
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//	r = radeon_fence_driver_init(rdev);
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//	if (r)
 563 
//	if (r)