WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/rs600.c



	/* Setup GPU memory space */
	tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
	rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
	rdev->mc.gtt_location = 0xffffffffUL;
	r = radeon_mc_setup(rdev);
	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
	if (r)
		return r;
	return 0;
}

		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		switch (radeon_connector->hpd.hpd) {
		case RADEON_HPD_1:
			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
			       S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
//           rdev->irq.hpd[0] = true;
			break;
		case RADEON_HPD_2:
			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
			       S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
//           rdev->irq.hpd[1] = true;
			break;
		default:
			break;
		}
	}
//   if (rdev->irq.installed)
//   rs600_irq_set(rdev);
}

 
void rs600_hpd_fini(struct radeon_device *rdev)
{

		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		switch (radeon_connector->hpd.hpd) {
		case RADEON_HPD_1:
			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
			       S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
//           rdev->irq.hpd[0] = false;
			break;
		case RADEON_HPD_2:
			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
			       S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
//           rdev->irq.hpd[1] = false;
			break;
		default:
			break;
		}
	}

	addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
	writeq(addr, ((void __iomem *)ptr) + (i * 8));
	return 0;
}

 
/*
int rs600_irq_set(struct radeon_device *rdev)
{
	uint32_t tmp = 0;
	uint32_t mode_int = 0;
	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
		~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &

		~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 
   if (!rdev->irq.installed) {
		WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
		WREG32(R_000040_GEN_INT_CNTL, 0);
		return -EINVAL;
	}
	if (rdev->irq.sw_int) {
		tmp |= S_000040_SW_INT_EN(1);
	}

	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
	return 0;
}
*/

 
static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
{
	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);

	r = rs600_gart_enable(rdev);
	if (r)
	return r;
	/* Enable IRQ */
//	rs600_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
//	r = r100_cp_init(rdev, 1024 * 1024);
//	if (r) {
//		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
//		return r;

Rev 1321	Rev 1403
Line 54...	Line 54...
54	/* Setup GPU memory space */	54	/* Setup GPU memory space */
55	tmp = RREG32_MC(R_000004_MC_FB_LOCATION);	55	tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
56	rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;	56	rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
57	rdev->mc.gtt_location = 0xffffffffUL;	57	rdev->mc.gtt_location = 0xffffffffUL;
58	r = radeon_mc_setup(rdev);	58	r = radeon_mc_setup(rdev);
-		59	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
59	if (r)	60	if (r)
60	return r;	61	return r;
61	return 0;	62	return 0;
62	}	63	}
Line 121...	Line 122...
121	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	122	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
122	switch (radeon_connector->hpd.hpd) {	123	switch (radeon_connector->hpd.hpd) {
123	case RADEON_HPD_1:	124	case RADEON_HPD_1:
124	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,	125	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
125	S_007D00_DC_HOT_PLUG_DETECT1_EN(1));	126	S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
126	rdev->irq.hpd[0] = true;	127	// rdev->irq.hpd[0] = true;
127	break;	128	break;
128	case RADEON_HPD_2:	129	case RADEON_HPD_2:
129	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,	130	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
130	S_007D10_DC_HOT_PLUG_DETECT2_EN(1));	131	S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
131	rdev->irq.hpd[1] = true;	132	// rdev->irq.hpd[1] = true;
132	break;	133	break;
133	default:	134	default:
134	break;	135	break;
135	}	136	}
136	}	137	}
-		138	// if (rdev->irq.installed)
137	rs600_irq_set(rdev);	139	// rs600_irq_set(rdev);
138	}	140	}
Line 139...	Line 141...
139		141
140	void rs600_hpd_fini(struct radeon_device *rdev)	142	void rs600_hpd_fini(struct radeon_device *rdev)
141	{	143	{
Line 146...	Line 148...
146	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	148	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
147	switch (radeon_connector->hpd.hpd) {	149	switch (radeon_connector->hpd.hpd) {
148	case RADEON_HPD_1:	150	case RADEON_HPD_1:
149	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,	151	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
150	S_007D00_DC_HOT_PLUG_DETECT1_EN(0));	152	S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
151	rdev->irq.hpd[0] = false;	153	// rdev->irq.hpd[0] = false;
152	break;	154	break;
153	case RADEON_HPD_2:	155	case RADEON_HPD_2:
154	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,	156	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
155	S_007D10_DC_HOT_PLUG_DETECT2_EN(0));	157	S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
156	rdev->irq.hpd[1] = false;	158	// rdev->irq.hpd[1] = false;
157	break;	159	break;
158	default:	160	default:
159	break;	161	break;
160	}	162	}
161	}	163	}
Line 300...	Line 302...
300	addr \|= R600_PTE_READABLE \| R600_PTE_WRITEABLE;	302	addr \|= R600_PTE_READABLE \| R600_PTE_WRITEABLE;
301	writeq(addr, ((void __iomem )ptr) + (i 8));	303	writeq(addr, ((void __iomem )ptr) + (i 8));
302	return 0;	304	return 0;
303	}	305	}
Line -...	Line 306...
-		306
304		307	/*
305	int rs600_irq_set(struct radeon_device *rdev)	308	int rs600_irq_set(struct radeon_device *rdev)
306	{	309	{
307	uint32_t tmp = 0;	310	uint32_t tmp = 0;
308	uint32_t mode_int = 0;	311	uint32_t mode_int = 0;
309	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &	312	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
310	~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);	313	~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
311	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &	314	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
Line -...	Line 315...
-		315	~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
-		316
-		317	if (!rdev->irq.installed) {
-		318	WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
-		319	WREG32(R_000040_GEN_INT_CNTL, 0);
312	~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);	320	return -EINVAL;
313		321	}
314	if (rdev->irq.sw_int) {	322	if (rdev->irq.sw_int) {
315	tmp \|= S_000040_SW_INT_EN(1);	323	tmp \|= S_000040_SW_INT_EN(1);
316	}	324	}
Line 330...	Line 338...
330	WREG32(R_006540_DxMODE_INT_MASK, mode_int);	338	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
331	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);	339	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
332	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);	340	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
333	return 0;	341	return 0;
334	}	342	}
-		343	*/
Line 335...	Line 344...
335		344
336	static inline uint32_t rs600_irq_ack(struct radeon_device rdev, u32 r500_disp_int)	345	static inline uint32_t rs600_irq_ack(struct radeon_device rdev, u32 r500_disp_int)
337	{	346	{
338	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);	347	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
Line 498...	Line 507...
498	r = rs600_gart_enable(rdev);	507	r = rs600_gart_enable(rdev);
499	if (r)	508	if (r)
500	return r;	509	return r;
501	/* Enable IRQ */	510	/* Enable IRQ */
502	// rs600_irq_set(rdev);	511	// rs600_irq_set(rdev);
-		512	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
503	/* 1M ring buffer */	513	/* 1M ring buffer */
504	// r = r100_cp_init(rdev, 1024 * 1024);	514	// r = r100_cp_init(rdev, 1024 * 1024);
505	// if (r) {	515	// if (r) {
506	// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);	516	// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
507	// return r;	517	// return r;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/rs600.c – Rev 1321 → 1403