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Rev 3764 Rev 5078
Line 107... Line 107...
107 
int rs400_gart_enable(struct radeon_device *rdev)
 107 
int rs400_gart_enable(struct radeon_device *rdev)
108 
{
 108 
{
109 
	uint32_t size_reg;
 109 
	uint32_t size_reg;
110 
	uint32_t tmp;
 110 
	uint32_t tmp;
Line 111... Line -...
111 
 
 - 
 
112 
	radeon_gart_restore(rdev);
 111 
 
113 
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 112 
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
114 
	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
 113 
	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
115 
	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
 114 
	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
116 
	/* Check gart size */
 115 
	/* Check gart size */
Line 172... Line 171...
172 
		  (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
 171 
		  (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
173 
	/* Disable AGP mode */
 172 
	/* Disable AGP mode */
174 
	/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
 173 
	/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
175 
	 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
 174 
	 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
176 
	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
 175 
	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
177 
		WREG32_MC(RS480_MC_MISC_CNTL,
 176 
		tmp = RREG32_MC(RS480_MC_MISC_CNTL);
178 
			  (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
 177 
		tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
- 
 
 178 
		WREG32_MC(RS480_MC_MISC_CNTL, tmp);
179 
	} else {
 179 
	} else {
- 
 
 180 
		tmp = RREG32_MC(RS480_MC_MISC_CNTL);
- 
 
 181 
		tmp |= RS480_GART_INDEX_REG_EN;
180 
		WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 182 
		WREG32_MC(RS480_MC_MISC_CNTL, tmp);
181 
	}
 183 
	}
182 
	/* Enable gart */
 184 
	/* Enable gart */
183 
	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
 185 
	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
184 
	rs400_gart_tlb_flush(rdev);
 186 
	rs400_gart_tlb_flush(rdev);
185 
	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 187 
	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
Line 204... Line 206...
204 
	radeon_gart_fini(rdev);
 206 
	radeon_gart_fini(rdev);
205 
	rs400_gart_disable(rdev);
 207 
	rs400_gart_disable(rdev);
206 
	radeon_gart_table_ram_free(rdev);
 208 
	radeon_gart_table_ram_free(rdev);
207 
}
 209 
}
Line -... Line 210...
- 
 
 210 
 
208 
 
 211 
#define RS400_PTE_UNSNOOPED (1 << 0)
209 
#define RS400_PTE_WRITEABLE (1 << 2)
 212 
#define RS400_PTE_WRITEABLE (1 << 2)
Line 210... Line 213...
210 
#define RS400_PTE_READABLE  (1 << 3)
 213 
#define RS400_PTE_READABLE  (1 << 3)
- 
 
 214 
 
211 
 
 215 
void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
212 
int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 216 
			 uint64_t addr, uint32_t flags)
213 
{
 217 
{
Line 214... Line -...
214 
	uint32_t entry;
 - 
 
215 
	u32 *gtt = rdev->gart.ptr;
 - 
 
216 
 
 - 
 
217 
	if (i < 0 || i > rdev->gart.num_gpu_pages) {
 - 
 
218 
		return -EINVAL;
 218 
	uint32_t entry;
219 
	}
 219 
	u32 *gtt = rdev->gart.ptr;
- 
 
 220 
 
220 
 
 221 
	entry = (lower_32_bits(addr) & PAGE_MASK) |
- 
 
 222 
		((upper_32_bits(addr) & 0xff) << 4);
- 
 
 223 
	if (flags & RADEON_GART_PAGE_READ)
- 
 
 224 
		addr |= RS400_PTE_READABLE;
- 
 
 225 
	if (flags & RADEON_GART_PAGE_WRITE)
221 
	entry = (lower_32_bits(addr) & PAGE_MASK) |
 226 
		addr |= RS400_PTE_WRITEABLE;
222 
		((upper_32_bits(addr) & 0xff) << 4) |
 227 
	if (!(flags & RADEON_GART_PAGE_SNOOP))
223 
		RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
 - 
 
224 
	entry = cpu_to_le32(entry);
 228 
		entry |= RS400_PTE_UNSNOOPED;
Line 225... Line 229...
225 
	gtt[i] = entry;
 229 
	entry = cpu_to_le32(entry);
226 
	return 0;
 230 
	gtt[i] = entry;
227 
}
 231 
}
Line 269... Line 273...
269 
	radeon_update_bandwidth_info(rdev);
 273 
	radeon_update_bandwidth_info(rdev);
270 
}
 274 
}
Line 271... Line 275...
271 
 
 275 
 
272 
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 276 
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
- 
 
 277 
{
273 
{
 278 
	unsigned long flags;
Line -... Line 279...
- 
 
 279 
	uint32_t r;
274 
	uint32_t r;
 280 
 
275 
 
 281 
	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
276 
	WREG32(RS480_NB_MC_INDEX, reg & 0xff);
 282 
	WREG32(RS480_NB_MC_INDEX, reg & 0xff);
- 
 
 283 
	r = RREG32(RS480_NB_MC_DATA);
277 
	r = RREG32(RS480_NB_MC_DATA);
 284 
	WREG32(RS480_NB_MC_INDEX, 0xff);
278 
	WREG32(RS480_NB_MC_INDEX, 0xff);
 285 
	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
Line 279... Line 286...
279 
	return r;
 286 
	return r;
280 
}
 287 
}
- 
 
 288 
 
- 
 
 289 
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
- 
 
 290 
{
281 
 
 291 
	unsigned long flags;
282 
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 292 
 
283 
{
 293 
	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
- 
 
 294 
	WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
284 
	WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
 295 
	WREG32(RS480_NB_MC_DATA, (v));
Line 285... Line 296...
285 
	WREG32(RS480_NB_MC_DATA, (v));
 296 
	WREG32(RS480_NB_MC_INDEX, 0xff);
286 
	WREG32(RS480_NB_MC_INDEX, 0xff);
 297 
	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
287 
}
 298 
}
Line 496... Line 507...
496 
	r = rs400_gart_init(rdev);
 507 
	r = rs400_gart_init(rdev);
497 
	if (r)
 508 
	if (r)
498 
		return r;
 509 
		return r;
499 
	r300_set_reg_safe(rdev);
 510 
	r300_set_reg_safe(rdev);
Line -... Line 511...
- 
 
 511 
 
- 
 
 512 
	/* Initialize power management */
- 
 
 513 
	radeon_pm_init(rdev);
500 
 
 514 
 
501 
	rdev->accel_working = true;
 515 
	rdev->accel_working = true;
502 
	r = rs400_startup(rdev);
 516 
	r = rs400_startup(rdev);
503 
	if (r) {
 517 
	if (r) {
504 
		/* Somethings want wront with the accel init stop accel */
 518 
		/* Somethings want wront with the accel init stop accel */