Rev 2005 | Rev 3764 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 2005 | Rev 2997 | ||
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Line 75... | Line 75... | ||
75 | 75 | ||
76 | int rs400_gart_init(struct radeon_device *rdev) |
76 | int rs400_gart_init(struct radeon_device *rdev) |
77 | { |
77 | { |
Line 78... | Line 78... | ||
78 | int r; |
78 | int r; |
79 | 79 | ||
80 | if (rdev->gart.table.ram.ptr) { |
80 | if (rdev->gart.ptr) { |
81 | WARN(1, "RS400 GART already initialized\n"); |
81 | WARN(1, "RS400 GART already initialized\n"); |
82 | return 0; |
82 | return 0; |
83 | } |
83 | } |
Line 180... | Line 180... | ||
180 | WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); |
180 | WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); |
181 | } |
181 | } |
182 | /* Enable gart */ |
182 | /* Enable gart */ |
183 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); |
183 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); |
184 | rs400_gart_tlb_flush(rdev); |
184 | rs400_gart_tlb_flush(rdev); |
- | 185 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
|
- | 186 | (unsigned)(rdev->mc.gtt_size >> 20), |
|
- | 187 | (unsigned long long)rdev->gart.table_addr); |
|
185 | rdev->gart.ready = true; |
188 | rdev->gart.ready = true; |
186 | return 0; |
189 | return 0; |
187 | } |
190 | } |
Line 188... | Line 191... | ||
188 | 191 | ||
Line 207... | Line 210... | ||
207 | #define RS400_PTE_READABLE (1 << 3) |
210 | #define RS400_PTE_READABLE (1 << 3) |
Line 208... | Line 211... | ||
208 | 211 | ||
209 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
212 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
210 | { |
213 | { |
- | 214 | uint32_t entry; |
|
Line 211... | Line 215... | ||
211 | uint32_t entry; |
215 | u32 *gtt = rdev->gart.ptr; |
212 | 216 | ||
213 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
217 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
Line 214... | Line 218... | ||
214 | return -EINVAL; |
218 | return -EINVAL; |
215 | } |
219 | } |
216 | 220 | ||
217 | entry = (lower_32_bits(addr) & PAGE_MASK) | |
221 | entry = (lower_32_bits(addr) & PAGE_MASK) | |
218 | ((upper_32_bits(addr) & 0xff) << 4) | |
222 | ((upper_32_bits(addr) & 0xff) << 4) | |
219 | RS400_PTE_WRITEABLE | RS400_PTE_READABLE; |
223 | RS400_PTE_WRITEABLE | RS400_PTE_READABLE; |
220 | entry = cpu_to_le32(entry); |
224 | entry = cpu_to_le32(entry); |
Line 221... | Line 225... | ||
221 | rdev->gart.table.ram.ptr[i] = entry; |
225 | gtt[i] = entry; |
222 | return 0; |
226 | return 0; |
Line 236... | Line 240... | ||
236 | DRM_UDELAY(1); |
240 | DRM_UDELAY(1); |
237 | } |
241 | } |
238 | return -1; |
242 | return -1; |
239 | } |
243 | } |
Line 240... | Line 244... | ||
240 | 244 | ||
241 | void rs400_gpu_init(struct radeon_device *rdev) |
245 | static void rs400_gpu_init(struct radeon_device *rdev) |
242 | { |
246 | { |
243 | /* FIXME: is this correct ? */ |
247 | /* FIXME: is this correct ? */ |
244 | r420_pipes_init(rdev); |
248 | r420_pipes_init(rdev); |
245 | if (rs400_mc_wait_for_idle(rdev)) { |
249 | if (rs400_mc_wait_for_idle(rdev)) { |
246 | printk(KERN_WARNING "rs400: Failed to wait MC idle while " |
250 | printk(KERN_WARNING "rs400: Failed to wait MC idle while " |
247 | "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); |
251 | "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); |
248 | } |
252 | } |
Line 249... | Line 253... | ||
249 | } |
253 | } |
250 | 254 | ||
251 | void rs400_mc_init(struct radeon_device *rdev) |
255 | static void rs400_mc_init(struct radeon_device *rdev) |
Line 252... | Line 256... | ||
252 | { |
256 | { |
253 | u64 base; |
257 | u64 base; |
Line 364... | Line 368... | ||
364 | #else |
368 | #else |
365 | return 0; |
369 | return 0; |
366 | #endif |
370 | #endif |
367 | } |
371 | } |
Line 368... | Line 372... | ||
368 | 372 | ||
369 | void rs400_mc_program(struct radeon_device *rdev) |
373 | static void rs400_mc_program(struct radeon_device *rdev) |
370 | { |
374 | { |
Line 371... | Line 375... | ||
371 | struct r100_mc_save save; |
375 | struct r100_mc_save save; |
372 | 376 | ||
Line 413... | Line 417... | ||
413 | r = r100_cp_init(rdev, 1024 * 1024); |
417 | r = r100_cp_init(rdev, 1024 * 1024); |
414 | if (r) { |
418 | if (r) { |
415 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
419 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
416 | return r; |
420 | return r; |
417 | } |
421 | } |
- | 422 | ||
418 | r = r100_ib_init(rdev); |
423 | r = radeon_ib_pool_init(rdev); |
419 | if (r) { |
424 | if (r) { |
420 | dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
425 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
421 | return r; |
426 | return r; |
422 | } |
427 | } |
- | 428 | ||
423 | return 0; |
429 | return 0; |
424 | } |
430 | } |
Line 480... | Line 486... | ||
480 | return r; |
486 | return r; |
481 | r = rs400_gart_init(rdev); |
487 | r = rs400_gart_init(rdev); |
482 | if (r) |
488 | if (r) |
483 | return r; |
489 | return r; |
484 | r300_set_reg_safe(rdev); |
490 | r300_set_reg_safe(rdev); |
- | 491 | ||
485 | rdev->accel_working = true; |
492 | rdev->accel_working = true; |
486 | r = rs400_startup(rdev); |
493 | r = rs400_startup(rdev); |
487 | if (r) { |
494 | if (r) { |
488 | /* Somethings want wront with the accel init stop accel */ |
495 | /* Somethings want wront with the accel init stop accel */ |
489 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
496 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |