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Rev 1986 Rev 2004
Line 28... Line 28...
28 
{
 28 
{
29 
    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 29 
    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
30 
    struct radeon_device *rdev = crtc->dev->dev_private;
 30 
    struct radeon_device *rdev = crtc->dev->dev_private;
31 
 
 31 
 
Line 32... Line 32...
32 
    if (ASIC_IS_AVIVO(rdev)) {
 32 
    if (ASIC_IS_DCE4(rdev)) {
- 
 
 33 
        WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
- 
 
 34 
        WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
- 
 
 35 
               EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
- 
 
 36 
    } else if (ASIC_IS_AVIVO(rdev)) {
33 
        WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
 37 
        WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
34 
        WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
 38 
        WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
35 
                 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
 39 
                 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
36 
    } else {
 40 
    } else {
37 
        switch (radeon_crtc->crtc_id) {
 41 
        switch (radeon_crtc->crtc_id) {
Line 56... Line 60...
56 
    struct radeon_device *rdev = crtc->dev->dev_private;
 60 
    struct radeon_device *rdev = crtc->dev->dev_private;
57 
    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 61 
    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
58 
    uint32_t cur_lock;
 62 
    uint32_t cur_lock;
59 
 
 63 
 
Line 60... Line 64...
60 
    if (ASIC_IS_AVIVO(rdev)) {
 64 
    if (ASIC_IS_DCE4(rdev)) {
- 
 
 65 
        cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
- 
 
 66 
        if (lock)
- 
 
 67 
            cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
- 
 
 68 
        else
- 
 
 69 
            cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
- 
 
 70 
        WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
- 
 
 71 
    } else if (ASIC_IS_AVIVO(rdev)) {
61 
        cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
 72 
        cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
62 
        if (lock)
 73 
        if (lock)
63 
            cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
 74 
            cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
64 
        else
 75 
        else
65 
            cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
 76 
            cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
Line 88... Line 99...
88 
 
 99 
 
Line 89... Line 100...
89 
    rdisplay->cursor = cursor;
 100 
    rdisplay->cursor = cursor;
90 
    gpu_addr = radeon_bo_gpu_offset(cursor->robj);
 101 
    gpu_addr = radeon_bo_gpu_offset(cursor->robj);
Line 91... Line 102...
91 
 
 102 
 
- 
 
 103 
    if (ASIC_IS_DCE4(rdev)) {
- 
 
 104 
        WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
- 
 
 105 
               0);
- 
 
 106 
        WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
- 
 
 107 
               gpu_addr);
- 
 
 108 
    } else if (ASIC_IS_AVIVO(rdev)) {
- 
 
 109 
        if (rdev->family >= CHIP_RV770)
92 
    if (ASIC_IS_AVIVO(rdev))
 110 
            WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0);
- 
 
 111 
        WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
93 
        WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
 112 
    }
94 
    else {
 113 
    else {
95 
        radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_start;
 114 
        radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_start;
96 
        /* offset is from DISP(2)_BASE_ADDRESS */
 115 
        /* offset is from DISP(2)_BASE_ADDRESS */
97 
        WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
 116 
        WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
Line 108... Line 127...
108 
    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 127 
    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
109 
 
 128 
 
Line 110... Line 129...
110 
    int hot_x = cursor->hot_x;
 129 
    int hot_x = cursor->hot_x;
111 
    int hot_y = cursor->hot_y;
 130 
    int hot_y = cursor->hot_y;
- 
 
 131 
    int w = 32;
Line 112... Line 132...
112 
 
 132 
 
113 
    radeon_lock_cursor_kms(crtc, true);
 - 
 
114 
    if (ASIC_IS_AVIVO(rdev))
 - 
 
115 
    {
 - 
 
116 
        int w = 32;
 - 
 
117 
        int i = 0;
 - 
 
Line 118... Line -...
118 
        struct drm_crtc *crtc_p;
 - 
 
119 
 
 - 
 
120 
        /* avivo cursor are offset into the total surface */
 133 
    radeon_lock_cursor_kms(crtc, true);
121 
//        x += crtc->x;
 - 
 
122 
//        y += crtc->y;
 - 
 
123 
 
 - 
 
124 
//        DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
 - 
 
125 
#if 0
 134 
 
126 
        /* avivo cursor image can't end on 128 pixel boundry or
 - 
 
127 
         * go past the end of the frame if both crtcs are enabled
 - 
 
128 
         */
 - 
 
129 
        list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
 135 
    if (ASIC_IS_DCE4(rdev)) {
130 
            if (crtc_p->enabled)
 - 
 
131 
                i++;
 - 
 
132 
        }
 - 
 
133 
        if (i > 1) {
 - 
 
134 
            int cursor_end, frame_end;
 - 
 
135 
 
 136 
        WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
136 
            cursor_end = x + w;
 137 
               (x << 16) | y);
137 
            frame_end = crtc->x + crtc->mode.crtc_hdisplay;
 138 
        WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset,
138 
            if (cursor_end >= frame_end) {
 - 
 
139 
                w = w - (cursor_end - frame_end);
 139 
               (hot_x << 16) | hot_y);
140 
                if (!(frame_end & 0x7f))
 - 
 
141 
                    w--;
 140 
        WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
142 
            } else {
 - 
 
143 
                if (!(cursor_end & 0x7f))
 - 
 
144 
                    w--;
 - 
 
145 
            }
 - 
 
146 
            if (w <= 0)
 - 
 
147 
                w = 1;
 - 
 
148 
        }
 141 
               ((w - 1) << 16) | 31);
149 
#endif
 142 
    } else if (ASIC_IS_AVIVO(rdev)) {
150 
        WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
 143 
        WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
151 
               (x << 16) | y);
 144 
               (x << 16) | y);
152 
        WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset,
 145 
        WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset,