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| Rev 1430 | Rev 1877 | ||
|---|---|---|---|
| 1 | #include |
1 | #include |
| 2 | #include |
2 | #include |
| 3 | #include |
3 | #include |
| 4 | #include "radeon_drm.h" |
4 | #include "radeon_drm.h" |
| 5 | #include "radeon.h" |
5 | #include "radeon.h" |
| 6 | #include "radeon_object.h" |
6 | #include "radeon_object.h" |
| 7 | #include "display.h" |
7 | #include "display.h" |
| 8 | 8 | ||
| 9 | #include "r100d.h" |
9 | #include "r100d.h" |
| 10 | 10 | ||
| 11 | 11 | ||
| 12 | display_t *rdisplay; |
12 | display_t *rdisplay; |
| 13 | 13 | ||
| 14 | static cursor_t* __stdcall select_cursor(cursor_t *cursor); |
14 | static cursor_t* __stdcall select_cursor(cursor_t *cursor); |
| 15 | static void __stdcall move_cursor(cursor_t *cursor, int x, int y); |
15 | static void __stdcall move_cursor(cursor_t *cursor, int x, int y); |
| 16 | 16 | ||
| - | 17 | extern void __attribute__((regparm(1))) destroy_cursor(cursor_t *cursor); |
|
| 17 | extern void destroy_cursor(void); |
18 | //extern void destroy_cursor(void); |
| 18 | 19 | ||
| 19 | void disable_mouse(void) |
20 | void disable_mouse(void) |
| 20 | {}; |
21 | {}; |
| 21 | 22 | ||
| 22 | int init_cursor(cursor_t *cursor) |
23 | int init_cursor(cursor_t *cursor) |
| 23 | { |
24 | { |
| 24 | struct radeon_device *rdev; |
25 | struct radeon_device *rdev; |
| 25 | 26 | ||
| 26 | uint32_t *bits; |
27 | uint32_t *bits; |
| 27 | uint32_t *src; |
28 | uint32_t *src; |
| 28 | 29 | ||
| 29 | int i,j; |
30 | int i,j; |
| 30 | int r; |
31 | int r; |
| 31 | 32 | ||
| 32 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
33 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
| 33 | 34 | ||
| 34 | r = radeon_bo_create(rdev, NULL, CURSOR_WIDTH*CURSOR_HEIGHT*4, |
35 | r = radeon_bo_create(rdev, NULL, CURSOR_WIDTH*CURSOR_HEIGHT*4, |
| 35 | false, RADEON_GEM_DOMAIN_VRAM, &cursor->robj); |
36 | false, RADEON_GEM_DOMAIN_VRAM, &cursor->robj); |
| 36 | 37 | ||
| 37 | if (unlikely(r != 0)) |
38 | if (unlikely(r != 0)) |
| 38 | return r; |
39 | return r; |
| 39 | 40 | ||
| 40 | r = radeon_bo_reserve(cursor->robj, false); |
41 | r = radeon_bo_reserve(cursor->robj, false); |
| 41 | if (unlikely(r != 0)) |
42 | if (unlikely(r != 0)) |
| 42 | return r; |
43 | return r; |
| 43 | 44 | ||
| 44 | r = radeon_bo_pin(cursor->robj, RADEON_GEM_DOMAIN_VRAM, NULL); |
45 | r = radeon_bo_pin(cursor->robj, RADEON_GEM_DOMAIN_VRAM, NULL); |
| 45 | if (unlikely(r != 0)) |
46 | if (unlikely(r != 0)) |
| 46 | return r; |
47 | return r; |
| 47 | 48 | ||
| 48 | r = radeon_bo_kmap(cursor->robj, (void**)&bits); |
49 | r = radeon_bo_kmap(cursor->robj, (void**)&bits); |
| 49 | if (r) { |
50 | if (r) { |
| 50 | DRM_ERROR("radeon: failed to map cursor (%d).\n", r); |
51 | DRM_ERROR("radeon: failed to map cursor (%d).\n", r); |
| 51 | return r; |
52 | return r; |
| 52 | }; |
53 | }; |
| 53 | 54 | ||
| 54 | src = cursor->data; |
55 | src = cursor->data; |
| 55 | 56 | ||
| 56 | for(i = 0; i < 32; i++) |
57 | for(i = 0; i < 32; i++) |
| 57 | { |
58 | { |
| 58 | for(j = 0; j < 32; j++) |
59 | for(j = 0; j < 32; j++) |
| 59 | *bits++ = *src++; |
60 | *bits++ = *src++; |
| 60 | for(j = 32; j < CURSOR_WIDTH; j++) |
61 | for(j = 32; j < CURSOR_WIDTH; j++) |
| 61 | *bits++ = 0; |
62 | *bits++ = 0; |
| 62 | } |
63 | } |
| 63 | for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++) |
64 | for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++) |
| 64 | *bits++ = 0; |
65 | *bits++ = 0; |
| 65 | 66 | ||
| 66 | radeon_bo_kunmap(cursor->robj); |
67 | radeon_bo_kunmap(cursor->robj); |
| 67 | 68 | ||
| 68 | // cursor->header.destroy = destroy_cursor; |
69 | cursor->header.destroy = destroy_cursor; |
| 69 | 70 | ||
| 70 | return 0; |
71 | return 0; |
| 71 | }; |
72 | }; |
| 72 | 73 | ||
| - | 74 | //void __attribute__((externally_visible)) fini_cursor(cursor_t *cursor) |
|
| 73 | void fini_cursor(cursor_t *cursor) |
75 | void __attribute__((regparm(1))) destroy_cursor(cursor_t *cursor) |
| 74 | { |
76 | { |
| 75 | list_del(&cursor->list); |
77 | list_del(&cursor->list); |
| 76 | radeon_bo_unpin(cursor->robj); |
78 | radeon_bo_unpin(cursor->robj); |
| 77 | KernelFree(cursor->data); |
79 | KernelFree(cursor->data); |
| 78 | __DestroyObject(cursor); |
80 | __DestroyObject(cursor); |
| 79 | }; |
81 | }; |
| 80 | 82 | ||
| 81 | 83 | ||
| 82 | static void radeon_show_cursor() |
84 | static void radeon_show_cursor() |
| 83 | { |
85 | { |
| 84 | struct radeon_device *rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
86 | struct radeon_device *rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
| 85 | 87 | ||
| 86 | if (ASIC_IS_AVIVO(rdev)) { |
88 | if (ASIC_IS_AVIVO(rdev)) { |
| 87 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL); |
89 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL); |
| 88 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
90 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
| 89 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
91 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
| 90 | } else { |
92 | } else { |
| 91 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
93 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
| 92 | WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | |
94 | WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | |
| 93 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
95 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
| 94 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
96 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
| 95 | } |
97 | } |
| 96 | } |
98 | } |
| 97 | 99 | ||
| 98 | cursor_t* __stdcall select_cursor(cursor_t *cursor) |
100 | cursor_t* __stdcall select_cursor(cursor_t *cursor) |
| 99 | { |
101 | { |
| 100 | struct radeon_device *rdev; |
102 | struct radeon_device *rdev; |
| 101 | cursor_t *old; |
103 | cursor_t *old; |
| 102 | uint32_t gpu_addr; |
104 | uint32_t gpu_addr; |
| 103 | 105 | ||
| 104 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
106 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
| 105 | 107 | ||
| 106 | old = rdisplay->cursor; |
108 | old = rdisplay->cursor; |
| 107 | 109 | ||
| 108 | rdisplay->cursor = cursor; |
110 | rdisplay->cursor = cursor; |
| 109 | gpu_addr = radeon_bo_gpu_offset(cursor->robj); |
111 | gpu_addr = radeon_bo_gpu_offset(cursor->robj); |
| 110 | 112 | ||
| 111 | if (ASIC_IS_AVIVO(rdev)) |
113 | if (ASIC_IS_AVIVO(rdev)) |
| 112 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS, gpu_addr); |
114 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS, gpu_addr); |
| 113 | else { |
115 | else { |
| 114 | WREG32(RADEON_CUR_OFFSET, gpu_addr - rdev->mc.vram_start); |
116 | WREG32(RADEON_CUR_OFFSET, gpu_addr - rdev->mc.vram_start); |
| 115 | } |
117 | } |
| 116 | 118 | ||
| 117 | return old; |
119 | return old; |
| 118 | }; |
120 | }; |
| 119 | 121 | ||
| 120 | static void radeon_lock_cursor(bool lock) |
122 | static void radeon_lock_cursor(bool lock) |
| 121 | { |
123 | { |
| 122 | struct radeon_device *rdev; |
124 | struct radeon_device *rdev; |
| 123 | 125 | ||
| 124 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
126 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
| 125 | 127 | ||
| 126 | uint32_t cur_lock; |
128 | uint32_t cur_lock; |
| 127 | 129 | ||
| 128 | if (ASIC_IS_AVIVO(rdev)) { |
130 | if (ASIC_IS_AVIVO(rdev)) { |
| 129 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE); |
131 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE); |
| 130 | if (lock) |
132 | if (lock) |
| 131 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
133 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
| 132 | else |
134 | else |
| 133 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
135 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
| 134 | WREG32(AVIVO_D1CUR_UPDATE, cur_lock); |
136 | WREG32(AVIVO_D1CUR_UPDATE, cur_lock); |
| 135 | } else { |
137 | } else { |
| 136 | cur_lock = RREG32(RADEON_CUR_OFFSET); |
138 | cur_lock = RREG32(RADEON_CUR_OFFSET); |
| 137 | if (lock) |
139 | if (lock) |
| 138 | cur_lock |= RADEON_CUR_LOCK; |
140 | cur_lock |= RADEON_CUR_LOCK; |
| 139 | else |
141 | else |
| 140 | cur_lock &= ~RADEON_CUR_LOCK; |
142 | cur_lock &= ~RADEON_CUR_LOCK; |
| 141 | WREG32(RADEON_CUR_OFFSET, cur_lock); |
143 | WREG32(RADEON_CUR_OFFSET, cur_lock); |
| 142 | } |
144 | } |
| 143 | } |
145 | } |
| 144 | 146 | ||
| 145 | 147 | ||
| 146 | void __stdcall move_cursor(cursor_t *cursor, int x, int y) |
148 | void __stdcall move_cursor(cursor_t *cursor, int x, int y) |
| 147 | { |
149 | { |
| 148 | struct radeon_device *rdev; |
150 | struct radeon_device *rdev; |
| 149 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
151 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
| 150 | 152 | ||
| 151 | int hot_x = cursor->hot_x; |
153 | int hot_x = cursor->hot_x; |
| 152 | int hot_y = cursor->hot_y; |
154 | int hot_y = cursor->hot_y; |
| 153 | 155 | ||
| 154 | radeon_lock_cursor(true); |
156 | radeon_lock_cursor(true); |
| 155 | if (ASIC_IS_AVIVO(rdev)) |
157 | if (ASIC_IS_AVIVO(rdev)) |
| 156 | { |
158 | { |
| 157 | int w = 32; |
159 | int w = 32; |
| 158 | 160 | ||
| 159 | WREG32(AVIVO_D1CUR_POSITION, (x << 16) | y); |
161 | WREG32(AVIVO_D1CUR_POSITION, (x << 16) | y); |
| 160 | WREG32(AVIVO_D1CUR_HOT_SPOT, (hot_x << 16) | hot_y); |
162 | WREG32(AVIVO_D1CUR_HOT_SPOT, (hot_x << 16) | hot_y); |
| 161 | WREG32(AVIVO_D1CUR_SIZE, ((w - 1) << 16) | 31); |
163 | WREG32(AVIVO_D1CUR_SIZE, ((w - 1) << 16) | 31); |
| 162 | } else { |
164 | } else { |
| 163 | 165 | ||
| 164 | uint32_t gpu_addr; |
166 | uint32_t gpu_addr; |
| 165 | int xorg =0, yorg=0; |
167 | int xorg =0, yorg=0; |
| 166 | 168 | ||
| 167 | x = x - hot_x; |
169 | x = x - hot_x; |
| 168 | y = y - hot_y; |
170 | y = y - hot_y; |
| 169 | 171 | ||
| 170 | if( x < 0 ) |
172 | if( x < 0 ) |
| 171 | { |
173 | { |
| 172 | xorg = -x + 1; |
174 | xorg = -x + 1; |
| 173 | x = 0; |
175 | x = 0; |
| 174 | } |
176 | } |
| 175 | 177 | ||
| 176 | if( y < 0 ) |
178 | if( y < 0 ) |
| 177 | { |
179 | { |
| 178 | yorg = -hot_y + 1; |
180 | yorg = -hot_y + 1; |
| 179 | y = 0; |
181 | y = 0; |
| 180 | }; |
182 | }; |
| 181 | 183 | ||
| 182 | WREG32(RADEON_CUR_HORZ_VERT_OFF, |
184 | WREG32(RADEON_CUR_HORZ_VERT_OFF, |
| 183 | (RADEON_CUR_LOCK | (xorg << 16) | yorg )); |
185 | (RADEON_CUR_LOCK | (xorg << 16) | yorg )); |
| 184 | WREG32(RADEON_CUR_HORZ_VERT_POSN, |
186 | WREG32(RADEON_CUR_HORZ_VERT_POSN, |
| 185 | (RADEON_CUR_LOCK | (x << 16) | y)); |
187 | (RADEON_CUR_LOCK | (x << 16) | y)); |
| 186 | 188 | ||
| 187 | gpu_addr = radeon_bo_gpu_offset(cursor->robj); |
189 | gpu_addr = radeon_bo_gpu_offset(cursor->robj); |
| 188 | 190 | ||
| 189 | /* offset is from DISP(2)_BASE_ADDRESS */ |
191 | /* offset is from DISP(2)_BASE_ADDRESS */ |
| 190 | WREG32(RADEON_CUR_OFFSET, |
192 | WREG32(RADEON_CUR_OFFSET, |
| 191 | (gpu_addr - rdev->mc.vram_start + (yorg * 256))); |
193 | (gpu_addr - rdev->mc.vram_start + (yorg * 256))); |
| 192 | } |
194 | } |
| 193 | radeon_lock_cursor(false); |
195 | radeon_lock_cursor(false); |
| 194 | } |
196 | } |
| 195 | 197 | ||
| 196 | void __stdcall restore_cursor(int x, int y) |
198 | void __stdcall restore_cursor(int x, int y) |
| 197 | { |
199 | { |
| 198 | }; |
200 | }; |
| 199 | 201 | ||
| 200 | 202 | ||
| 201 | bool init_display(struct radeon_device *rdev, videomode_t *usermode) |
203 | bool init_display(struct radeon_device *rdev, videomode_t *usermode) |
| 202 | { |
204 | { |
| 203 | struct drm_device *dev; |
205 | struct drm_device *dev; |
| 204 | 206 | ||
| 205 | cursor_t *cursor; |
207 | cursor_t *cursor; |
| 206 | bool retval = true; |
208 | bool retval = true; |
| 207 | u32_t ifl; |
209 | u32_t ifl; |
| 208 | 210 | ||
| 209 | ENTER(); |
211 | ENTER(); |
| 210 | 212 | ||
| 211 | rdisplay = GetDisplay(); |
213 | rdisplay = GetDisplay(); |
| 212 | 214 | ||
| 213 | dev = rdisplay->ddev = rdev->ddev; |
215 | dev = rdisplay->ddev = rdev->ddev; |
| 214 | 216 | ||
| 215 | ifl = safe_cli(); |
217 | ifl = safe_cli(); |
| 216 | { |
218 | { |
| 217 | list_for_each_entry(cursor, &rdisplay->cursors, list) |
219 | list_for_each_entry(cursor, &rdisplay->cursors, list) |
| 218 | { |
220 | { |
| 219 | init_cursor(cursor); |
221 | init_cursor(cursor); |
| 220 | }; |
222 | }; |
| 221 | 223 | ||
| 222 | rdisplay->restore_cursor(0,0); |
224 | rdisplay->restore_cursor(0,0); |
| 223 | rdisplay->init_cursor = init_cursor; |
225 | rdisplay->init_cursor = init_cursor; |
| 224 | rdisplay->select_cursor = select_cursor; |
226 | rdisplay->select_cursor = select_cursor; |
| 225 | rdisplay->show_cursor = NULL; |
227 | rdisplay->show_cursor = NULL; |
| 226 | rdisplay->move_cursor = move_cursor; |
228 | rdisplay->move_cursor = move_cursor; |
| 227 | rdisplay->restore_cursor = restore_cursor; |
229 | rdisplay->restore_cursor = restore_cursor; |
| 228 | rdisplay->disable_mouse = disable_mouse; |
230 | rdisplay->disable_mouse = disable_mouse; |
| 229 | 231 | ||
| 230 | select_cursor(rdisplay->cursor); |
232 | select_cursor(rdisplay->cursor); |
| 231 | radeon_show_cursor(); |
233 | radeon_show_cursor(); |
| 232 | }; |
234 | }; |
| 233 | safe_sti(ifl); |
235 | safe_sti(ifl); |
| 234 | 236 | ||
| 235 | LEAVE(); |
237 | LEAVE(); |
| 236 | 238 | ||
| 237 | return retval; |
239 | return retval; |
| 238 | }; |
240 | }; |
| 239 | 241 | ||
| 240 | 242 | ||
| 241 | struct fb_info *framebuffer_alloc(size_t size, struct device *dev) |
243 | struct fb_info *framebuffer_alloc(size_t size, struct device *dev) |
| 242 | { |
244 | { |
| 243 | #define BYTES_PER_LONG (BITS_PER_LONG/8) |
245 | #define BYTES_PER_LONG (BITS_PER_LONG/8) |
| 244 | #define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG)) |
246 | #define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG)) |
| 245 | int fb_info_size = sizeof(struct fb_info); |
247 | int fb_info_size = sizeof(struct fb_info); |
| 246 | struct fb_info *info; |
248 | struct fb_info *info; |
| 247 | char *p; |
249 | char *p; |
| 248 | 250 | ||
| 249 | if (size) |
251 | if (size) |
| 250 | fb_info_size += PADDING; |
252 | fb_info_size += PADDING; |
| 251 | 253 | ||
| 252 | p = kzalloc(fb_info_size + size, GFP_KERNEL); |
254 | p = kzalloc(fb_info_size + size, GFP_KERNEL); |
| 253 | 255 | ||
| 254 | if (!p) |
256 | if (!p) |
| 255 | return NULL; |
257 | return NULL; |
| 256 | 258 | ||
| 257 | info = (struct fb_info *) p; |
259 | info = (struct fb_info *) p; |
| 258 | 260 | ||
| 259 | if (size) |
261 | if (size) |
| 260 | info->par = p + fb_info_size; |
262 | info->par = p + fb_info_size; |
| 261 | 263 | ||
| 262 | return info; |
264 | return info; |
| 263 | #undef PADDING |
265 | #undef PADDING |
| 264 | #undef BYTES_PER_LONG |
266 | #undef BYTES_PER_LONG |
| 265 | } |
267 | } |
| 266 | 268 | ||
| 267 | void framebuffer_release(struct fb_info *info) |
269 | void framebuffer_release(struct fb_info *info) |
| 268 | { |
270 | { |
| 269 | kfree(info); |
271 | kfree(info); |
| 270 | } |
272 | } |
| 271 | 273 | ||
| 272 | #define PACKET3_PAINT_MULTI 0x9A |
274 | #define PACKET3_PAINT_MULTI 0x9A |
| 273 | # define R5XX_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
275 | # define R5XX_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
| 274 | # define R5XX_GMC_WR_MSK_DIS (1 << 30) |
276 | # define R5XX_GMC_WR_MSK_DIS (1 << 30) |
| 275 | # define R5XX_ROP3_P 0x00f00000 |
277 | # define R5XX_ROP3_P 0x00f00000 |
| 276 | 278 | ||
| 277 | #define R5XX_SC_TOP_LEFT 0x16ec |
279 | #define R5XX_SC_TOP_LEFT 0x16ec |
| 278 | #define R5XX_SC_BOTTOM_RIGHT 0x16f0 |
280 | #define R5XX_SC_BOTTOM_RIGHT 0x16f0 |
| 279 | # define R5XX_SC_SIGN_MASK_LO 0x8000 |
281 | # define R5XX_SC_SIGN_MASK_LO 0x8000 |
| 280 | # define R5XX_SC_SIGN_MASK_HI 0x80000000 |
282 | # define R5XX_SC_SIGN_MASK_HI 0x80000000 |
| 281 | 283 | ||
| 282 | #define R5XX_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 |
284 | #define R5XX_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 |
| 283 | # define R5XX_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) |
285 | # define R5XX_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) |
| 284 | # define R5XX_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) |
286 | # define R5XX_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) |
| 285 | 287 | ||
| 286 | 288 | ||
| 287 | int r100_2D_test(struct radeon_device *rdev) |
289 | int r100_2D_test(struct radeon_device *rdev) |
| 288 | { |
290 | { |
| 289 | 291 | ||
| 290 | uint32_t pitch; |
292 | uint32_t pitch; |
| 291 | uint32_t offset; |
293 | uint32_t offset; |
| 292 | 294 | ||
| 293 | int r; |
295 | int r; |
| 294 | 296 | ||
| 295 | ENTER(); |
297 | ENTER(); |
| 296 | 298 | ||
| 297 | pitch = (1024*4)/64; |
299 | pitch = (1024*4)/64; |
| 298 | offset = rdev->mc.vram_start; |
300 | offset = rdev->mc.vram_start; |
| 299 | 301 | ||
| 300 | r = radeon_ring_lock(rdev, 16); |
302 | r = radeon_ring_lock(rdev, 16); |
| 301 | if (r) { |
303 | if (r) { |
| 302 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
304 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
| 303 | return r; |
305 | return r; |
| 304 | } |
306 | } |
| 305 | radeon_ring_write(rdev, PACKET0(R5XX_SC_TOP_LEFT, 0)); |
307 | radeon_ring_write(rdev, PACKET0(R5XX_SC_TOP_LEFT, 0)); |
| 306 | radeon_ring_write(rdev, 0); |
308 | radeon_ring_write(rdev, 0); |
| 307 | 309 | ||
| 308 | radeon_ring_write(rdev, PACKET0(R5XX_SC_BOTTOM_RIGHT, 0)); |
310 | radeon_ring_write(rdev, PACKET0(R5XX_SC_BOTTOM_RIGHT, 0)); |
| 309 | radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX | |
311 | radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX | |
| 310 | RADEON_DEFAULT_SC_BOTTOM_MAX); |
312 | RADEON_DEFAULT_SC_BOTTOM_MAX); |
| 311 | 313 | ||
| 312 | radeon_ring_write(rdev, PACKET0(R5XX_DEFAULT_SC_BOTTOM_RIGHT, 0)); |
314 | radeon_ring_write(rdev, PACKET0(R5XX_DEFAULT_SC_BOTTOM_RIGHT, 0)); |
| 313 | radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX | |
315 | radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX | |
| 314 | RADEON_DEFAULT_SC_BOTTOM_MAX); |
316 | RADEON_DEFAULT_SC_BOTTOM_MAX); |
| 315 | 317 | ||
| 316 | radeon_ring_write(rdev, PACKET3(PACKET3_PAINT_MULTI, 4)); |
318 | radeon_ring_write(rdev, PACKET3(PACKET3_PAINT_MULTI, 4)); |
| 317 | radeon_ring_write(rdev, RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
319 | radeon_ring_write(rdev, RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 318 | RADEON_GMC_BRUSH_SOLID_COLOR | |
320 | RADEON_GMC_BRUSH_SOLID_COLOR | |
| 319 | RADEON_GMC_DST_32BPP | |
321 | RADEON_GMC_DST_32BPP | |
| 320 | RADEON_GMC_SRC_DATATYPE_COLOR | |
322 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 321 | R5XX_GMC_CLR_CMP_CNTL_DIS | |
323 | R5XX_GMC_CLR_CMP_CNTL_DIS | |
| 322 | R5XX_GMC_WR_MSK_DIS | |
324 | R5XX_GMC_WR_MSK_DIS | |
| 323 | R5XX_ROP3_P); |
325 | R5XX_ROP3_P); |
| 324 | 326 | ||
| 325 | radeon_ring_write(rdev, (pitch<<22)|(offset>>10)); |
327 | radeon_ring_write(rdev, (pitch<<22)|(offset>>10)); |
| 326 | radeon_ring_write(rdev, 0x0000FF00); |
328 | radeon_ring_write(rdev, 0x0000FF00); |
| 327 | radeon_ring_write(rdev, (64<<16)|64); |
329 | radeon_ring_write(rdev, (64<<16)|64); |
| 328 | radeon_ring_write(rdev, (128<<16)|128); |
330 | radeon_ring_write(rdev, (128<<16)|128); |
| 329 | 331 | ||
| 330 | radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); |
332 | radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); |
| 331 | radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); |
333 | radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); |
| 332 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
334 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| 333 | radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | |
335 | radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | |
| 334 | RADEON_WAIT_HOST_IDLECLEAN | |
336 | RADEON_WAIT_HOST_IDLECLEAN | |
| 335 | RADEON_WAIT_DMA_GUI_IDLE); |
337 | RADEON_WAIT_DMA_GUI_IDLE); |
| 336 | 338 | ||
| 337 | radeon_ring_unlock_commit(rdev); |
339 | radeon_ring_unlock_commit(rdev); |
| 338 | 340 | ||
| 339 | LEAVE(); |
341 | LEAVE(); |
| 340 | return r; |
342 | return r; |
| 341 | } |
343 | } |
| 342 | 344 | ||
| 343 | 345 | ||
| 344 | #include "r600_reg_auto_r6xx.h" |
346 | #include "r600_reg_auto_r6xx.h" |
| 345 | #include "r600_reg_r6xx.h" |
347 | #include "r600_reg_r6xx.h" |
| 346 | #include "r600d.h" |
348 | #include "r600d.h" |
| 347 | 349 | ||
| 348 | const u32 r6xx_default_state[] = |
350 | const u32 r6xx_default_state[] = |
| 349 | { |
351 | { |
| 350 | 0xc0002400, |
352 | 0xc0002400, |
| 351 | 0x00000000, |
353 | 0x00000000, |
| 352 | 0xc0012800, |
354 | 0xc0012800, |
| 353 | 0x80000000, |
355 | 0x80000000, |
| 354 | 0x80000000, |
356 | 0x80000000, |
| 355 | 0xc0004600, |
357 | 0xc0004600, |
| 356 | 0x00000016, |
358 | 0x00000016, |
| 357 | 0xc0016800, |
359 | 0xc0016800, |
| 358 | 0x00000010, |
360 | 0x00000010, |
| 359 | 0x00028000, |
361 | 0x00028000, |
| 360 | 0xc0016800, |
362 | 0xc0016800, |
| 361 | 0x00000010, |
363 | 0x00000010, |
| 362 | 0x00008000, |
364 | 0x00008000, |
| 363 | 0xc0016800, |
365 | 0xc0016800, |
| 364 | 0x00000542, |
366 | 0x00000542, |
| 365 | 0x07000003, |
367 | 0x07000003, |
| 366 | 0xc0016800, |
368 | 0xc0016800, |
| 367 | 0x000005c5, |
369 | 0x000005c5, |
| 368 | 0x00000000, |
370 | 0x00000000, |
| 369 | 0xc0016800, |
371 | 0xc0016800, |
| 370 | 0x00000363, |
372 | 0x00000363, |
| 371 | 0x00000000, |
373 | 0x00000000, |
| 372 | 0xc0016800, |
374 | 0xc0016800, |
| 373 | 0x0000060c, |
375 | 0x0000060c, |
| 374 | 0x82000000, |
376 | 0x82000000, |
| 375 | 0xc0016800, |
377 | 0xc0016800, |
| 376 | 0x0000060e, |
378 | 0x0000060e, |
| 377 | 0x01020204, |
379 | 0x01020204, |
| 378 | 0xc0016f00, |
380 | 0xc0016f00, |
| 379 | 0x00000000, |
381 | 0x00000000, |
| 380 | 0x00000000, |
382 | 0x00000000, |
| 381 | 0xc0016f00, |
383 | 0xc0016f00, |
| 382 | 0x00000001, |
384 | 0x00000001, |
| 383 | 0x00000000, |
385 | 0x00000000, |
| 384 | 0xc0096900, |
386 | 0xc0096900, |
| 385 | 0x0000022a, |
387 | 0x0000022a, |
| 386 | 0x00000000, |
388 | 0x00000000, |
| 387 | 0x00000000, |
389 | 0x00000000, |
| 388 | 0x00000000, |
390 | 0x00000000, |
| 389 | 0x00000000, |
391 | 0x00000000, |
| 390 | 0x00000000, |
392 | 0x00000000, |
| 391 | 0x00000000, |
393 | 0x00000000, |
| 392 | 0x00000000, |
394 | 0x00000000, |
| 393 | 0x00000000, |
395 | 0x00000000, |
| 394 | 0x00000000, |
396 | 0x00000000, |
| 395 | 0xc0016900, |
397 | 0xc0016900, |
| 396 | 0x00000004, |
398 | 0x00000004, |
| 397 | 0x00000000, |
399 | 0x00000000, |
| 398 | 0xc0016900, |
400 | 0xc0016900, |
| 399 | 0x0000000a, |
401 | 0x0000000a, |
| 400 | 0x00000000, |
402 | 0x00000000, |
| 401 | 0xc0016900, |
403 | 0xc0016900, |
| 402 | 0x0000000b, |
404 | 0x0000000b, |
| 403 | 0x00000000, |
405 | 0x00000000, |
| 404 | 0xc0016900, |
406 | 0xc0016900, |
| 405 | 0x0000010c, |
407 | 0x0000010c, |
| 406 | 0x00000000, |
408 | 0x00000000, |
| 407 | 0xc0016900, |
409 | 0xc0016900, |
| 408 | 0x0000010d, |
410 | 0x0000010d, |
| 409 | 0x00000000, |
411 | 0x00000000, |
| 410 | 0xc0016900, |
412 | 0xc0016900, |
| 411 | 0x00000200, |
413 | 0x00000200, |
| 412 | 0x00000000, |
414 | 0x00000000, |
| 413 | 0xc0016900, |
415 | 0xc0016900, |
| 414 | 0x00000343, |
416 | 0x00000343, |
| 415 | 0x00000060, |
417 | 0x00000060, |
| 416 | 0xc0016900, |
418 | 0xc0016900, |
| 417 | 0x00000344, |
419 | 0x00000344, |
| 418 | 0x00000040, |
420 | 0x00000040, |
| 419 | 0xc0016900, |
421 | 0xc0016900, |
| 420 | 0x00000351, |
422 | 0x00000351, |
| 421 | 0x0000aa00, |
423 | 0x0000aa00, |
| 422 | 0xc0016900, |
424 | 0xc0016900, |
| 423 | 0x00000104, |
425 | 0x00000104, |
| 424 | 0x00000000, |
426 | 0x00000000, |
| 425 | 0xc0016900, |
427 | 0xc0016900, |
| 426 | 0x0000010e, |
428 | 0x0000010e, |
| 427 | 0x00000000, |
429 | 0x00000000, |
| 428 | 0xc0046900, |
430 | 0xc0046900, |
| 429 | 0x00000105, |
431 | 0x00000105, |
| 430 | 0x00000000, |
432 | 0x00000000, |
| 431 | 0x00000000, |
433 | 0x00000000, |
| 432 | 0x00000000, |
434 | 0x00000000, |
| 433 | 0x00000000, |
435 | 0x00000000, |
| 434 | 0xc0036900, |
436 | 0xc0036900, |
| 435 | 0x00000109, |
437 | 0x00000109, |
| 436 | 0x00000000, |
438 | 0x00000000, |
| 437 | 0x00000000, |
439 | 0x00000000, |
| 438 | 0x00000000, |
440 | 0x00000000, |
| 439 | 0xc0046900, |
441 | 0xc0046900, |
| 440 | 0x0000030c, |
442 | 0x0000030c, |
| 441 | 0x01000000, |
443 | 0x01000000, |
| 442 | 0x00000000, |
444 | 0x00000000, |
| 443 | 0x00000000, |
445 | 0x00000000, |
| 444 | 0x00000000, |
446 | 0x00000000, |
| 445 | 0xc0046900, |
447 | 0xc0046900, |
| 446 | 0x00000048, |
448 | 0x00000048, |
| 447 | 0x3f800000, |
449 | 0x3f800000, |
| 448 | 0x00000000, |
450 | 0x00000000, |
| 449 | 0x3f800000, |
451 | 0x3f800000, |
| 450 | 0x3f800000, |
452 | 0x3f800000, |
| 451 | 0xc0016900, |
453 | 0xc0016900, |
| 452 | 0x0000008e, |
454 | 0x0000008e, |
| 453 | 0x0000000f, |
455 | 0x0000000f, |
| 454 | 0xc0016900, |
456 | 0xc0016900, |
| 455 | 0x00000080, |
457 | 0x00000080, |
| 456 | 0x00000000, |
458 | 0x00000000, |
| 457 | 0xc0016900, |
459 | 0xc0016900, |
| 458 | 0x00000083, |
460 | 0x00000083, |
| 459 | 0x0000ffff, |
461 | 0x0000ffff, |
| 460 | 0xc0016900, |
462 | 0xc0016900, |
| 461 | 0x00000084, |
463 | 0x00000084, |
| 462 | 0x00000000, |
464 | 0x00000000, |
| 463 | 0xc0016900, |
465 | 0xc0016900, |
| 464 | 0x00000085, |
466 | 0x00000085, |
| 465 | 0x20002000, |
467 | 0x20002000, |
| 466 | 0xc0016900, |
468 | 0xc0016900, |
| 467 | 0x00000086, |
469 | 0x00000086, |
| 468 | 0x00000000, |
470 | 0x00000000, |
| 469 | 0xc0016900, |
471 | 0xc0016900, |
| 470 | 0x00000087, |
472 | 0x00000087, |
| 471 | 0x20002000, |
473 | 0x20002000, |
| 472 | 0xc0016900, |
474 | 0xc0016900, |
| 473 | 0x00000088, |
475 | 0x00000088, |
| 474 | 0x00000000, |
476 | 0x00000000, |
| 475 | 0xc0016900, |
477 | 0xc0016900, |
| 476 | 0x00000089, |
478 | 0x00000089, |
| 477 | 0x20002000, |
479 | 0x20002000, |
| 478 | 0xc0016900, |
480 | 0xc0016900, |
| 479 | 0x0000008a, |
481 | 0x0000008a, |
| 480 | 0x00000000, |
482 | 0x00000000, |
| 481 | 0xc0016900, |
483 | 0xc0016900, |
| 482 | 0x0000008b, |
484 | 0x0000008b, |
| 483 | 0x20002000, |
485 | 0x20002000, |
| 484 | 0xc0016900, |
486 | 0xc0016900, |
| 485 | 0x0000008c, |
487 | 0x0000008c, |
| 486 | 0x00000000, |
488 | 0x00000000, |
| 487 | 0xc0016900, |
489 | 0xc0016900, |
| 488 | 0x00000094, |
490 | 0x00000094, |
| 489 | 0x80000000, |
491 | 0x80000000, |
| 490 | 0xc0016900, |
492 | 0xc0016900, |
| 491 | 0x00000095, |
493 | 0x00000095, |
| 492 | 0x20002000, |
494 | 0x20002000, |
| 493 | 0xc0026900, |
495 | 0xc0026900, |
| 494 | 0x000000b4, |
496 | 0x000000b4, |
| 495 | 0x00000000, |
497 | 0x00000000, |
| 496 | 0x3f800000, |
498 | 0x3f800000, |
| 497 | 0xc0016900, |
499 | 0xc0016900, |
| 498 | 0x00000096, |
500 | 0x00000096, |
| 499 | 0x80000000, |
501 | 0x80000000, |
| 500 | 0xc0016900, |
502 | 0xc0016900, |
| 501 | 0x00000097, |
503 | 0x00000097, |
| 502 | 0x20002000, |
504 | 0x20002000, |
| 503 | 0xc0026900, |
505 | 0xc0026900, |
| 504 | 0x000000b6, |
506 | 0x000000b6, |
| 505 | 0x00000000, |
507 | 0x00000000, |
| 506 | 0x3f800000, |
508 | 0x3f800000, |
| 507 | 0xc0016900, |
509 | 0xc0016900, |
| 508 | 0x00000098, |
510 | 0x00000098, |
| 509 | 0x80000000, |
511 | 0x80000000, |
| 510 | 0xc0016900, |
512 | 0xc0016900, |
| 511 | 0x00000099, |
513 | 0x00000099, |
| 512 | 0x20002000, |
514 | 0x20002000, |
| 513 | 0xc0026900, |
515 | 0xc0026900, |
| 514 | 0x000000b8, |
516 | 0x000000b8, |
| 515 | 0x00000000, |
517 | 0x00000000, |
| 516 | 0x3f800000, |
518 | 0x3f800000, |
| 517 | 0xc0016900, |
519 | 0xc0016900, |
| 518 | 0x0000009a, |
520 | 0x0000009a, |
| 519 | 0x80000000, |
521 | 0x80000000, |
| 520 | 0xc0016900, |
522 | 0xc0016900, |
| 521 | 0x0000009b, |
523 | 0x0000009b, |
| 522 | 0x20002000, |
524 | 0x20002000, |
| 523 | 0xc0026900, |
525 | 0xc0026900, |
| 524 | 0x000000ba, |
526 | 0x000000ba, |
| 525 | 0x00000000, |
527 | 0x00000000, |
| 526 | 0x3f800000, |
528 | 0x3f800000, |
| 527 | 0xc0016900, |
529 | 0xc0016900, |
| 528 | 0x0000009c, |
530 | 0x0000009c, |
| 529 | 0x80000000, |
531 | 0x80000000, |
| 530 | 0xc0016900, |
532 | 0xc0016900, |
| 531 | 0x0000009d, |
533 | 0x0000009d, |
| 532 | 0x20002000, |
534 | 0x20002000, |
| 533 | 0xc0026900, |
535 | 0xc0026900, |
| 534 | 0x000000bc, |
536 | 0x000000bc, |
| 535 | 0x00000000, |
537 | 0x00000000, |
| 536 | 0x3f800000, |
538 | 0x3f800000, |
| 537 | 0xc0016900, |
539 | 0xc0016900, |
| 538 | 0x0000009e, |
540 | 0x0000009e, |
| 539 | 0x80000000, |
541 | 0x80000000, |
| 540 | 0xc0016900, |
542 | 0xc0016900, |
| 541 | 0x0000009f, |
543 | 0x0000009f, |
| 542 | 0x20002000, |
544 | 0x20002000, |
| 543 | 0xc0026900, |
545 | 0xc0026900, |
| 544 | 0x000000be, |
546 | 0x000000be, |
| 545 | 0x00000000, |
547 | 0x00000000, |
| 546 | 0x3f800000, |
548 | 0x3f800000, |
| 547 | 0xc0016900, |
549 | 0xc0016900, |
| 548 | 0x000000a0, |
550 | 0x000000a0, |
| 549 | 0x80000000, |
551 | 0x80000000, |
| 550 | 0xc0016900, |
552 | 0xc0016900, |
| 551 | 0x000000a1, |
553 | 0x000000a1, |
| 552 | 0x20002000, |
554 | 0x20002000, |
| 553 | 0xc0026900, |
555 | 0xc0026900, |
| 554 | 0x000000c0, |
556 | 0x000000c0, |
| 555 | 0x00000000, |
557 | 0x00000000, |
| 556 | 0x3f800000, |
558 | 0x3f800000, |
| 557 | 0xc0016900, |
559 | 0xc0016900, |
| 558 | 0x000000a2, |
560 | 0x000000a2, |
| 559 | 0x80000000, |
561 | 0x80000000, |
| 560 | 0xc0016900, |
562 | 0xc0016900, |
| 561 | 0x000000a3, |
563 | 0x000000a3, |
| 562 | 0x20002000, |
564 | 0x20002000, |
| 563 | 0xc0026900, |
565 | 0xc0026900, |
| 564 | 0x000000c2, |
566 | 0x000000c2, |
| 565 | 0x00000000, |
567 | 0x00000000, |
| 566 | 0x3f800000, |
568 | 0x3f800000, |
| 567 | 0xc0016900, |
569 | 0xc0016900, |
| 568 | 0x000000a4, |
570 | 0x000000a4, |
| 569 | 0x80000000, |
571 | 0x80000000, |
| 570 | 0xc0016900, |
572 | 0xc0016900, |
| 571 | 0x000000a5, |
573 | 0x000000a5, |
| 572 | 0x20002000, |
574 | 0x20002000, |
| 573 | 0xc0026900, |
575 | 0xc0026900, |
| 574 | 0x000000c4, |
576 | 0x000000c4, |
| 575 | 0x00000000, |
577 | 0x00000000, |
| 576 | 0x3f800000, |
578 | 0x3f800000, |
| 577 | 0xc0016900, |
579 | 0xc0016900, |
| 578 | 0x000000a6, |
580 | 0x000000a6, |
| 579 | 0x80000000, |
581 | 0x80000000, |
| 580 | 0xc0016900, |
582 | 0xc0016900, |
| 581 | 0x000000a7, |
583 | 0x000000a7, |
| 582 | 0x20002000, |
584 | 0x20002000, |
| 583 | 0xc0026900, |
585 | 0xc0026900, |
| 584 | 0x000000c6, |
586 | 0x000000c6, |
| 585 | 0x00000000, |
587 | 0x00000000, |
| 586 | 0x3f800000, |
588 | 0x3f800000, |
| 587 | 0xc0016900, |
589 | 0xc0016900, |
| 588 | 0x000000a8, |
590 | 0x000000a8, |
| 589 | 0x80000000, |
591 | 0x80000000, |
| 590 | 0xc0016900, |
592 | 0xc0016900, |
| 591 | 0x000000a9, |
593 | 0x000000a9, |
| 592 | 0x20002000, |
594 | 0x20002000, |
| 593 | 0xc0026900, |
595 | 0xc0026900, |
| 594 | 0x000000c8, |
596 | 0x000000c8, |
| 595 | 0x00000000, |
597 | 0x00000000, |
| 596 | 0x3f800000, |
598 | 0x3f800000, |
| 597 | 0xc0016900, |
599 | 0xc0016900, |
| 598 | 0x000000aa, |
600 | 0x000000aa, |
| 599 | 0x80000000, |
601 | 0x80000000, |
| 600 | 0xc0016900, |
602 | 0xc0016900, |
| 601 | 0x000000ab, |
603 | 0x000000ab, |
| 602 | 0x20002000, |
604 | 0x20002000, |
| 603 | 0xc0026900, |
605 | 0xc0026900, |
| 604 | 0x000000ca, |
606 | 0x000000ca, |
| 605 | 0x00000000, |
607 | 0x00000000, |
| 606 | 0x3f800000, |
608 | 0x3f800000, |
| 607 | 0xc0016900, |
609 | 0xc0016900, |
| 608 | 0x000000ac, |
610 | 0x000000ac, |
| 609 | 0x80000000, |
611 | 0x80000000, |
| 610 | 0xc0016900, |
612 | 0xc0016900, |
| 611 | 0x000000ad, |
613 | 0x000000ad, |
| 612 | 0x20002000, |
614 | 0x20002000, |
| 613 | 0xc0026900, |
615 | 0xc0026900, |
| 614 | 0x000000cc, |
616 | 0x000000cc, |
| 615 | 0x00000000, |
617 | 0x00000000, |
| 616 | 0x3f800000, |
618 | 0x3f800000, |
| 617 | 0xc0016900, |
619 | 0xc0016900, |
| 618 | 0x000000ae, |
620 | 0x000000ae, |
| 619 | 0x80000000, |
621 | 0x80000000, |
| 620 | 0xc0016900, |
622 | 0xc0016900, |
| 621 | 0x000000af, |
623 | 0x000000af, |
| 622 | 0x20002000, |
624 | 0x20002000, |
| 623 | 0xc0026900, |
625 | 0xc0026900, |
| 624 | 0x000000ce, |
626 | 0x000000ce, |
| 625 | 0x00000000, |
627 | 0x00000000, |
| 626 | 0x3f800000, |
628 | 0x3f800000, |
| 627 | 0xc0016900, |
629 | 0xc0016900, |
| 628 | 0x000000b0, |
630 | 0x000000b0, |
| 629 | 0x80000000, |
631 | 0x80000000, |
| 630 | 0xc0016900, |
632 | 0xc0016900, |
| 631 | 0x000000b1, |
633 | 0x000000b1, |
| 632 | 0x20002000, |
634 | 0x20002000, |
| 633 | 0xc0026900, |
635 | 0xc0026900, |
| 634 | 0x000000d0, |
636 | 0x000000d0, |
| 635 | 0x00000000, |
637 | 0x00000000, |
| 636 | 0x3f800000, |
638 | 0x3f800000, |
| 637 | 0xc0016900, |
639 | 0xc0016900, |
| 638 | 0x000000b2, |
640 | 0x000000b2, |
| 639 | 0x80000000, |
641 | 0x80000000, |
| 640 | 0xc0016900, |
642 | 0xc0016900, |
| 641 | 0x000000b3, |
643 | 0x000000b3, |
| 642 | 0x20002000, |
644 | 0x20002000, |
| 643 | 0xc0026900, |
645 | 0xc0026900, |
| 644 | 0x000000d2, |
646 | 0x000000d2, |
| 645 | 0x00000000, |
647 | 0x00000000, |
| 646 | 0x3f800000, |
648 | 0x3f800000, |
| 647 | 0xc0016900, |
649 | 0xc0016900, |
| 648 | 0x00000293, |
650 | 0x00000293, |
| 649 | 0x00004010, |
651 | 0x00004010, |
| 650 | 0xc0016900, |
652 | 0xc0016900, |
| 651 | 0x00000300, |
653 | 0x00000300, |
| 652 | 0x00000000, |
654 | 0x00000000, |
| 653 | 0xc0016900, |
655 | 0xc0016900, |
| 654 | 0x00000301, |
656 | 0x00000301, |
| 655 | 0x00000000, |
657 | 0x00000000, |
| 656 | 0xc0016900, |
658 | 0xc0016900, |
| 657 | 0x00000312, |
659 | 0x00000312, |
| 658 | 0xffffffff, |
660 | 0xffffffff, |
| 659 | 0xc0016900, |
661 | 0xc0016900, |
| 660 | 0x00000307, |
662 | 0x00000307, |
| 661 | 0x00000000, |
663 | 0x00000000, |
| 662 | 0xc0016900, |
664 | 0xc0016900, |
| 663 | 0x00000308, |
665 | 0x00000308, |
| 664 | 0x00000000, |
666 | 0x00000000, |
| 665 | 0xc0016900, |
667 | 0xc0016900, |
| 666 | 0x00000283, |
668 | 0x00000283, |
| 667 | 0x00000000, |
669 | 0x00000000, |
| 668 | 0xc0016900, |
670 | 0xc0016900, |
| 669 | 0x00000292, |
671 | 0x00000292, |
| 670 | 0x00000000, |
672 | 0x00000000, |
| 671 | 0xc0066900, |
673 | 0xc0066900, |
| 672 | 0x0000010f, |
674 | 0x0000010f, |
| 673 | 0x00000000, |
675 | 0x00000000, |
| 674 | 0x00000000, |
676 | 0x00000000, |
| 675 | 0x00000000, |
677 | 0x00000000, |
| 676 | 0x00000000, |
678 | 0x00000000, |
| 677 | 0x00000000, |
679 | 0x00000000, |
| 678 | 0x00000000, |
680 | 0x00000000, |
| 679 | 0xc0016900, |
681 | 0xc0016900, |
| 680 | 0x00000206, |
682 | 0x00000206, |
| 681 | 0x00000000, |
683 | 0x00000000, |
| 682 | 0xc0016900, |
684 | 0xc0016900, |
| 683 | 0x00000207, |
685 | 0x00000207, |
| 684 | 0x00000000, |
686 | 0x00000000, |
| 685 | 0xc0016900, |
687 | 0xc0016900, |
| 686 | 0x00000208, |
688 | 0x00000208, |
| 687 | 0x00000000, |
689 | 0x00000000, |
| 688 | 0xc0046900, |
690 | 0xc0046900, |
| 689 | 0x00000303, |
691 | 0x00000303, |
| 690 | 0x3f800000, |
692 | 0x3f800000, |
| 691 | 0x3f800000, |
693 | 0x3f800000, |
| 692 | 0x3f800000, |
694 | 0x3f800000, |
| 693 | 0x3f800000, |
695 | 0x3f800000, |
| 694 | 0xc0016900, |
696 | 0xc0016900, |
| 695 | 0x00000205, |
697 | 0x00000205, |
| 696 | 0x00000004, |
698 | 0x00000004, |
| 697 | 0xc0016900, |
699 | 0xc0016900, |
| 698 | 0x00000280, |
700 | 0x00000280, |
| 699 | 0x00000000, |
701 | 0x00000000, |
| 700 | 0xc0016900, |
702 | 0xc0016900, |
| 701 | 0x00000281, |
703 | 0x00000281, |
| 702 | 0x00000000, |
704 | 0x00000000, |
| 703 | 0xc0016900, |
705 | 0xc0016900, |
| 704 | 0x0000037e, |
706 | 0x0000037e, |
| 705 | 0x00000000, |
707 | 0x00000000, |
| 706 | 0xc0016900, |
708 | 0xc0016900, |
| 707 | 0x00000382, |
709 | 0x00000382, |
| 708 | 0x00000000, |
710 | 0x00000000, |
| 709 | 0xc0016900, |
711 | 0xc0016900, |
| 710 | 0x00000380, |
712 | 0x00000380, |
| 711 | 0x00000000, |
713 | 0x00000000, |
| 712 | 0xc0016900, |
714 | 0xc0016900, |
| 713 | 0x00000383, |
715 | 0x00000383, |
| 714 | 0x00000000, |
716 | 0x00000000, |
| 715 | 0xc0016900, |
717 | 0xc0016900, |
| 716 | 0x00000381, |
718 | 0x00000381, |
| 717 | 0x00000000, |
719 | 0x00000000, |
| 718 | 0xc0016900, |
720 | 0xc0016900, |
| 719 | 0x00000282, |
721 | 0x00000282, |
| 720 | 0x00000008, |
722 | 0x00000008, |
| 721 | 0xc0016900, |
723 | 0xc0016900, |
| 722 | 0x00000302, |
724 | 0x00000302, |
| 723 | 0x0000002d, |
725 | 0x0000002d, |
| 724 | 0xc0016900, |
726 | 0xc0016900, |
| 725 | 0x0000037f, |
727 | 0x0000037f, |
| 726 | 0x00000000, |
728 | 0x00000000, |
| 727 | 0xc0016900, |
729 | 0xc0016900, |
| 728 | 0x000001b2, |
730 | 0x000001b2, |
| 729 | 0x00000000, |
731 | 0x00000000, |
| 730 | 0xc0016900, |
732 | 0xc0016900, |
| 731 | 0x000001b6, |
733 | 0x000001b6, |
| 732 | 0x00000000, |
734 | 0x00000000, |
| 733 | 0xc0016900, |
735 | 0xc0016900, |
| 734 | 0x000001b7, |
736 | 0x000001b7, |
| 735 | 0x00000000, |
737 | 0x00000000, |
| 736 | 0xc0016900, |
738 | 0xc0016900, |
| 737 | 0x000001b8, |
739 | 0x000001b8, |
| 738 | 0x00000000, |
740 | 0x00000000, |
| 739 | 0xc0016900, |
741 | 0xc0016900, |
| 740 | 0x000001b9, |
742 | 0x000001b9, |
| 741 | 0x00000000, |
743 | 0x00000000, |
| 742 | 0xc0016900, |
744 | 0xc0016900, |
| 743 | 0x00000225, |
745 | 0x00000225, |
| 744 | 0x00000000, |
746 | 0x00000000, |
| 745 | 0xc0016900, |
747 | 0xc0016900, |
| 746 | 0x00000229, |
748 | 0x00000229, |
| 747 | 0x00000000, |
749 | 0x00000000, |
| 748 | 0xc0016900, |
750 | 0xc0016900, |
| 749 | 0x00000237, |
751 | 0x00000237, |
| 750 | 0x00000000, |
752 | 0x00000000, |
| 751 | 0xc0016900, |
753 | 0xc0016900, |
| 752 | 0x00000100, |
754 | 0x00000100, |
| 753 | 0x00000800, |
755 | 0x00000800, |
| 754 | 0xc0016900, |
756 | 0xc0016900, |
| 755 | 0x00000101, |
757 | 0x00000101, |
| 756 | 0x00000000, |
758 | 0x00000000, |
| 757 | 0xc0016900, |
759 | 0xc0016900, |
| 758 | 0x00000102, |
760 | 0x00000102, |
| 759 | 0x00000000, |
761 | 0x00000000, |
| 760 | 0xc0016900, |
762 | 0xc0016900, |
| 761 | 0x000002a8, |
763 | 0x000002a8, |
| 762 | 0x00000000, |
764 | 0x00000000, |
| 763 | 0xc0016900, |
765 | 0xc0016900, |
| 764 | 0x000002a9, |
766 | 0x000002a9, |
| 765 | 0x00000000, |
767 | 0x00000000, |
| 766 | 0xc0016900, |
768 | 0xc0016900, |
| 767 | 0x00000103, |
769 | 0x00000103, |
| 768 | 0x00000000, |
770 | 0x00000000, |
| 769 | 0xc0016900, |
771 | 0xc0016900, |
| 770 | 0x00000284, |
772 | 0x00000284, |
| 771 | 0x00000000, |
773 | 0x00000000, |
| 772 | 0xc0016900, |
774 | 0xc0016900, |
| 773 | 0x00000290, |
775 | 0x00000290, |
| 774 | 0x00000000, |
776 | 0x00000000, |
| 775 | 0xc0016900, |
777 | 0xc0016900, |
| 776 | 0x00000285, |
778 | 0x00000285, |
| 777 | 0x00000000, |
779 | 0x00000000, |
| 778 | 0xc0016900, |
780 | 0xc0016900, |
| 779 | 0x00000286, |
781 | 0x00000286, |
| 780 | 0x00000000, |
782 | 0x00000000, |
| 781 | 0xc0016900, |
783 | 0xc0016900, |
| 782 | 0x00000287, |
784 | 0x00000287, |
| 783 | 0x00000000, |
785 | 0x00000000, |
| 784 | 0xc0016900, |
786 | 0xc0016900, |
| 785 | 0x00000288, |
787 | 0x00000288, |
| 786 | 0x00000000, |
788 | 0x00000000, |
| 787 | 0xc0016900, |
789 | 0xc0016900, |
| 788 | 0x00000289, |
790 | 0x00000289, |
| 789 | 0x00000000, |
791 | 0x00000000, |
| 790 | 0xc0016900, |
792 | 0xc0016900, |
| 791 | 0x0000028a, |
793 | 0x0000028a, |
| 792 | 0x00000000, |
794 | 0x00000000, |
| 793 | 0xc0016900, |
795 | 0xc0016900, |
| 794 | 0x0000028b, |
796 | 0x0000028b, |
| 795 | 0x00000000, |
797 | 0x00000000, |
| 796 | 0xc0016900, |
798 | 0xc0016900, |
| 797 | 0x0000028c, |
799 | 0x0000028c, |
| 798 | 0x00000000, |
800 | 0x00000000, |
| 799 | 0xc0016900, |
801 | 0xc0016900, |
| 800 | 0x0000028d, |
802 | 0x0000028d, |
| 801 | 0x00000000, |
803 | 0x00000000, |
| 802 | 0xc0016900, |
804 | 0xc0016900, |
| 803 | 0x0000028e, |
805 | 0x0000028e, |
| 804 | 0x00000000, |
806 | 0x00000000, |
| 805 | 0xc0016900, |
807 | 0xc0016900, |
| 806 | 0x0000028f, |
808 | 0x0000028f, |
| 807 | 0x00000000, |
809 | 0x00000000, |
| 808 | 0xc0016900, |
810 | 0xc0016900, |
| 809 | 0x000002a1, |
811 | 0x000002a1, |
| 810 | 0x00000000, |
812 | 0x00000000, |
| 811 | 0xc0016900, |
813 | 0xc0016900, |
| 812 | 0x000002a5, |
814 | 0x000002a5, |
| 813 | 0x00000000, |
815 | 0x00000000, |
| 814 | 0xc0016900, |
816 | 0xc0016900, |
| 815 | 0x000002ac, |
817 | 0x000002ac, |
| 816 | 0x00000000, |
818 | 0x00000000, |
| 817 | 0xc0016900, |
819 | 0xc0016900, |
| 818 | 0x000002ad, |
820 | 0x000002ad, |
| 819 | 0x00000000, |
821 | 0x00000000, |
| 820 | 0xc0016900, |
822 | 0xc0016900, |
| 821 | 0x000002ae, |
823 | 0x000002ae, |
| 822 | 0x00000000, |
824 | 0x00000000, |
| 823 | 0xc0016900, |
825 | 0xc0016900, |
| 824 | 0x000002c8, |
826 | 0x000002c8, |
| 825 | 0x00000000, |
827 | 0x00000000, |
| 826 | 0xc0016900, |
828 | 0xc0016900, |
| 827 | 0x00000206, |
829 | 0x00000206, |
| 828 | 0x00000100, |
830 | 0x00000100, |
| 829 | 0xc0016900, |
831 | 0xc0016900, |
| 830 | 0x00000204, |
832 | 0x00000204, |
| 831 | 0x00010000, |
833 | 0x00010000, |
| 832 | 0xc0036e00, |
834 | 0xc0036e00, |
| 833 | 0x00000000, |
835 | 0x00000000, |
| 834 | 0x00000012, |
836 | 0x00000012, |
| 835 | 0x00000000, |
837 | 0x00000000, |
| 836 | 0x00000000, |
838 | 0x00000000, |
| 837 | 0xc0016900, |
839 | 0xc0016900, |
| 838 | 0x0000008f, |
840 | 0x0000008f, |
| 839 | 0x0000000f, |
841 | 0x0000000f, |
| 840 | 0xc0016900, |
842 | 0xc0016900, |
| 841 | 0x000001e8, |
843 | 0x000001e8, |
| 842 | 0x00000001, |
844 | 0x00000001, |
| 843 | 0xc0016900, |
845 | 0xc0016900, |
| 844 | 0x00000202, |
846 | 0x00000202, |
| 845 | 0x00cc0000, |
847 | 0x00cc0000, |
| 846 | 0xc0016900, |
848 | 0xc0016900, |
| 847 | 0x00000205, |
849 | 0x00000205, |
| 848 | 0x00000244, |
850 | 0x00000244, |
| 849 | 0xc0016900, |
851 | 0xc0016900, |
| 850 | 0x00000203, |
852 | 0x00000203, |
| 851 | 0x00000210, |
853 | 0x00000210, |
| 852 | 0xc0016900, |
854 | 0xc0016900, |
| 853 | 0x000001b1, |
855 | 0x000001b1, |
| 854 | 0x00000000, |
856 | 0x00000000, |
| 855 | 0xc0016900, |
857 | 0xc0016900, |
| 856 | 0x00000185, |
858 | 0x00000185, |
| 857 | 0x00000000, |
859 | 0x00000000, |
| 858 | 0xc0016900, |
860 | 0xc0016900, |
| 859 | 0x000001b3, |
861 | 0x000001b3, |
| 860 | 0x00000001, |
862 | 0x00000001, |
| 861 | 0xc0016900, |
863 | 0xc0016900, |
| 862 | 0x000001b4, |
864 | 0x000001b4, |
| 863 | 0x00000000, |
865 | 0x00000000, |
| 864 | 0xc0016900, |
866 | 0xc0016900, |
| 865 | 0x00000191, |
867 | 0x00000191, |
| 866 | 0x00000b00, |
868 | 0x00000b00, |
| 867 | 0xc0016900, |
869 | 0xc0016900, |
| 868 | 0x000001b5, |
870 | 0x000001b5, |
| 869 | 0x00000000, |
871 | 0x00000000, |
| 870 | }; |
872 | }; |
| 871 | 873 | ||
| 872 | 874 | ||
| 873 | 875 | ||
| 874 | const u32 r7xx_default_state[] = |
876 | const u32 r7xx_default_state[] = |
| 875 | { |
877 | { |
| 876 | 0xc0012800, |
878 | 0xc0012800, |
| 877 | 0x80000000, |
879 | 0x80000000, |
| 878 | 0x80000000, |
880 | 0x80000000, |
| 879 | 0xc0004600, |
881 | 0xc0004600, |
| 880 | 0x00000016, |
882 | 0x00000016, |
| 881 | 0xc0016800, |
883 | 0xc0016800, |
| 882 | 0x00000010, |
884 | 0x00000010, |
| 883 | 0x00028000, |
885 | 0x00028000, |
| 884 | 0xc0016800, |
886 | 0xc0016800, |
| 885 | 0x00000010, |
887 | 0x00000010, |
| 886 | 0x00008000, |
888 | 0x00008000, |
| 887 | 0xc0016800, |
889 | 0xc0016800, |
| 888 | 0x00000542, |
890 | 0x00000542, |
| 889 | 0x07000002, |
891 | 0x07000002, |
| 890 | 0xc0016800, |
892 | 0xc0016800, |
| 891 | 0x000005c5, |
893 | 0x000005c5, |
| 892 | 0x00000000, |
894 | 0x00000000, |
| 893 | 0xc0016800, |
895 | 0xc0016800, |
| 894 | 0x00000363, |
896 | 0x00000363, |
| 895 | 0x00004000, |
897 | 0x00004000, |
| 896 | 0xc0016800, |
898 | 0xc0016800, |
| 897 | 0x0000060c, |
899 | 0x0000060c, |
| 898 | 0x00000000, |
900 | 0x00000000, |
| 899 | 0xc0016800, |
901 | 0xc0016800, |
| 900 | 0x0000060e, |
902 | 0x0000060e, |
| 901 | 0x00420204, |
903 | 0x00420204, |
| 902 | 0xc0016f00, |
904 | 0xc0016f00, |
| 903 | 0x00000000, |
905 | 0x00000000, |
| 904 | 0x00000000, |
906 | 0x00000000, |
| 905 | 0xc0016f00, |
907 | 0xc0016f00, |
| 906 | 0x00000001, |
908 | 0x00000001, |
| 907 | 0x00000000, |
909 | 0x00000000, |
| 908 | 0xc0096900, |
910 | 0xc0096900, |
| 909 | 0x0000022a, |
911 | 0x0000022a, |
| 910 | 0x00000000, |
912 | 0x00000000, |
| 911 | 0x00000000, |
913 | 0x00000000, |
| 912 | 0x00000000, |
914 | 0x00000000, |
| 913 | 0x00000000, |
915 | 0x00000000, |
| 914 | 0x00000000, |
916 | 0x00000000, |
| 915 | 0x00000000, |
917 | 0x00000000, |
| 916 | 0x00000000, |
918 | 0x00000000, |
| 917 | 0x00000000, |
919 | 0x00000000, |
| 918 | 0x00000000, |
920 | 0x00000000, |
| 919 | 0xc0016900, |
921 | 0xc0016900, |
| 920 | 0x00000004, |
922 | 0x00000004, |
| 921 | 0x00000000, |
923 | 0x00000000, |
| 922 | 0xc0016900, |
924 | 0xc0016900, |
| 923 | 0x0000000a, |
925 | 0x0000000a, |
| 924 | 0x00000000, |
926 | 0x00000000, |
| 925 | 0xc0016900, |
927 | 0xc0016900, |
| 926 | 0x0000000b, |
928 | 0x0000000b, |
| 927 | 0x00000000, |
929 | 0x00000000, |
| 928 | 0xc0016900, |
930 | 0xc0016900, |
| 929 | 0x0000010c, |
931 | 0x0000010c, |
| 930 | 0x00000000, |
932 | 0x00000000, |
| 931 | 0xc0016900, |
933 | 0xc0016900, |
| 932 | 0x0000010d, |
934 | 0x0000010d, |
| 933 | 0x00000000, |
935 | 0x00000000, |
| 934 | 0xc0016900, |
936 | 0xc0016900, |
| 935 | 0x00000200, |
937 | 0x00000200, |
| 936 | 0x00000000, |
938 | 0x00000000, |
| 937 | 0xc0016900, |
939 | 0xc0016900, |
| 938 | 0x00000343, |
940 | 0x00000343, |
| 939 | 0x00000060, |
941 | 0x00000060, |
| 940 | 0xc0016900, |
942 | 0xc0016900, |
| 941 | 0x00000344, |
943 | 0x00000344, |
| 942 | 0x00000000, |
944 | 0x00000000, |
| 943 | 0xc0016900, |
945 | 0xc0016900, |
| 944 | 0x00000351, |
946 | 0x00000351, |
| 945 | 0x0000aa00, |
947 | 0x0000aa00, |
| 946 | 0xc0016900, |
948 | 0xc0016900, |
| 947 | 0x00000104, |
949 | 0x00000104, |
| 948 | 0x00000000, |
950 | 0x00000000, |
| 949 | 0xc0016900, |
951 | 0xc0016900, |
| 950 | 0x0000010e, |
952 | 0x0000010e, |
| 951 | 0x00000000, |
953 | 0x00000000, |
| 952 | 0xc0046900, |
954 | 0xc0046900, |
| 953 | 0x00000105, |
955 | 0x00000105, |
| 954 | 0x00000000, |
956 | 0x00000000, |
| 955 | 0x00000000, |
957 | 0x00000000, |
| 956 | 0x00000000, |
958 | 0x00000000, |
| 957 | 0x00000000, |
959 | 0x00000000, |
| 958 | 0xc0046900, |
960 | 0xc0046900, |
| 959 | 0x0000030c, |
961 | 0x0000030c, |
| 960 | 0x01000000, |
962 | 0x01000000, |
| 961 | 0x00000000, |
963 | 0x00000000, |
| 962 | 0x00000000, |
964 | 0x00000000, |
| 963 | 0x00000000, |
965 | 0x00000000, |
| 964 | 0xc0016900, |
966 | 0xc0016900, |
| 965 | 0x0000008e, |
967 | 0x0000008e, |
| 966 | 0x0000000f, |
968 | 0x0000000f, |
| 967 | 0xc0016900, |
969 | 0xc0016900, |
| 968 | 0x00000080, |
970 | 0x00000080, |
| 969 | 0x00000000, |
971 | 0x00000000, |
| 970 | 0xc0016900, |
972 | 0xc0016900, |
| 971 | 0x00000083, |
973 | 0x00000083, |
| 972 | 0x0000ffff, |
974 | 0x0000ffff, |
| 973 | 0xc0016900, |
975 | 0xc0016900, |
| 974 | 0x00000084, |
976 | 0x00000084, |
| 975 | 0x00000000, |
977 | 0x00000000, |
| 976 | 0xc0016900, |
978 | 0xc0016900, |
| 977 | 0x00000085, |
979 | 0x00000085, |
| 978 | 0x20002000, |
980 | 0x20002000, |
| 979 | 0xc0016900, |
981 | 0xc0016900, |
| 980 | 0x00000086, |
982 | 0x00000086, |
| 981 | 0x00000000, |
983 | 0x00000000, |
| 982 | 0xc0016900, |
984 | 0xc0016900, |
| 983 | 0x00000087, |
985 | 0x00000087, |
| 984 | 0x20002000, |
986 | 0x20002000, |
| 985 | 0xc0016900, |
987 | 0xc0016900, |
| 986 | 0x00000088, |
988 | 0x00000088, |
| 987 | 0x00000000, |
989 | 0x00000000, |
| 988 | 0xc0016900, |
990 | 0xc0016900, |
| 989 | 0x00000089, |
991 | 0x00000089, |
| 990 | 0x20002000, |
992 | 0x20002000, |
| 991 | 0xc0016900, |
993 | 0xc0016900, |
| 992 | 0x0000008a, |
994 | 0x0000008a, |
| 993 | 0x00000000, |
995 | 0x00000000, |
| 994 | 0xc0016900, |
996 | 0xc0016900, |
| 995 | 0x0000008b, |
997 | 0x0000008b, |
| 996 | 0x20002000, |
998 | 0x20002000, |
| 997 | 0xc0016900, |
999 | 0xc0016900, |
| 998 | 0x0000008c, |
1000 | 0x0000008c, |
| 999 | 0xaaaaaaaa, |
1001 | 0xaaaaaaaa, |
| 1000 | 0xc0016900, |
1002 | 0xc0016900, |
| 1001 | 0x00000094, |
1003 | 0x00000094, |
| 1002 | 0x80000000, |
1004 | 0x80000000, |
| 1003 | 0xc0016900, |
1005 | 0xc0016900, |
| 1004 | 0x00000095, |
1006 | 0x00000095, |
| 1005 | 0x20002000, |
1007 | 0x20002000, |
| 1006 | 0xc0026900, |
1008 | 0xc0026900, |
| 1007 | 0x000000b4, |
1009 | 0x000000b4, |
| 1008 | 0x00000000, |
1010 | 0x00000000, |
| 1009 | 0x3f800000, |
1011 | 0x3f800000, |
| 1010 | 0xc0016900, |
1012 | 0xc0016900, |
| 1011 | 0x00000096, |
1013 | 0x00000096, |
| 1012 | 0x80000000, |
1014 | 0x80000000, |
| 1013 | 0xc0016900, |
1015 | 0xc0016900, |
| 1014 | 0x00000097, |
1016 | 0x00000097, |
| 1015 | 0x20002000, |
1017 | 0x20002000, |
| 1016 | 0xc0026900, |
1018 | 0xc0026900, |
| 1017 | 0x000000b6, |
1019 | 0x000000b6, |
| 1018 | 0x00000000, |
1020 | 0x00000000, |
| 1019 | 0x3f800000, |
1021 | 0x3f800000, |
| 1020 | 0xc0016900, |
1022 | 0xc0016900, |
| 1021 | 0x00000098, |
1023 | 0x00000098, |
| 1022 | 0x80000000, |
1024 | 0x80000000, |
| 1023 | 0xc0016900, |
1025 | 0xc0016900, |
| 1024 | 0x00000099, |
1026 | 0x00000099, |
| 1025 | 0x20002000, |
1027 | 0x20002000, |
| 1026 | 0xc0026900, |
1028 | 0xc0026900, |
| 1027 | 0x000000b8, |
1029 | 0x000000b8, |
| 1028 | 0x00000000, |
1030 | 0x00000000, |
| 1029 | 0x3f800000, |
1031 | 0x3f800000, |
| 1030 | 0xc0016900, |
1032 | 0xc0016900, |
| 1031 | 0x0000009a, |
1033 | 0x0000009a, |
| 1032 | 0x80000000, |
1034 | 0x80000000, |
| 1033 | 0xc0016900, |
1035 | 0xc0016900, |
| 1034 | 0x0000009b, |
1036 | 0x0000009b, |
| 1035 | 0x20002000, |
1037 | 0x20002000, |
| 1036 | 0xc0026900, |
1038 | 0xc0026900, |
| 1037 | 0x000000ba, |
1039 | 0x000000ba, |
| 1038 | 0x00000000, |
1040 | 0x00000000, |
| 1039 | 0x3f800000, |
1041 | 0x3f800000, |
| 1040 | 0xc0016900, |
1042 | 0xc0016900, |
| 1041 | 0x0000009c, |
1043 | 0x0000009c, |
| 1042 | 0x80000000, |
1044 | 0x80000000, |
| 1043 | 0xc0016900, |
1045 | 0xc0016900, |
| 1044 | 0x0000009d, |
1046 | 0x0000009d, |
| 1045 | 0x20002000, |
1047 | 0x20002000, |
| 1046 | 0xc0026900, |
1048 | 0xc0026900, |
| 1047 | 0x000000bc, |
1049 | 0x000000bc, |
| 1048 | 0x00000000, |
1050 | 0x00000000, |
| 1049 | 0x3f800000, |
1051 | 0x3f800000, |
| 1050 | 0xc0016900, |
1052 | 0xc0016900, |
| 1051 | 0x0000009e, |
1053 | 0x0000009e, |
| 1052 | 0x80000000, |
1054 | 0x80000000, |
| 1053 | 0xc0016900, |
1055 | 0xc0016900, |
| 1054 | 0x0000009f, |
1056 | 0x0000009f, |
| 1055 | 0x20002000, |
1057 | 0x20002000, |
| 1056 | 0xc0026900, |
1058 | 0xc0026900, |
| 1057 | 0x000000be, |
1059 | 0x000000be, |
| 1058 | 0x00000000, |
1060 | 0x00000000, |
| 1059 | 0x3f800000, |
1061 | 0x3f800000, |
| 1060 | 0xc0016900, |
1062 | 0xc0016900, |
| 1061 | 0x000000a0, |
1063 | 0x000000a0, |
| 1062 | 0x80000000, |
1064 | 0x80000000, |
| 1063 | 0xc0016900, |
1065 | 0xc0016900, |
| 1064 | 0x000000a1, |
1066 | 0x000000a1, |
| 1065 | 0x20002000, |
1067 | 0x20002000, |
| 1066 | 0xc0026900, |
1068 | 0xc0026900, |
| 1067 | 0x000000c0, |
1069 | 0x000000c0, |
| 1068 | 0x00000000, |
1070 | 0x00000000, |
| 1069 | 0x3f800000, |
1071 | 0x3f800000, |
| 1070 | 0xc0016900, |
1072 | 0xc0016900, |
| 1071 | 0x000000a2, |
1073 | 0x000000a2, |
| 1072 | 0x80000000, |
1074 | 0x80000000, |
| 1073 | 0xc0016900, |
1075 | 0xc0016900, |
| 1074 | 0x000000a3, |
1076 | 0x000000a3, |
| 1075 | 0x20002000, |
1077 | 0x20002000, |
| 1076 | 0xc0026900, |
1078 | 0xc0026900, |
| 1077 | 0x000000c2, |
1079 | 0x000000c2, |
| 1078 | 0x00000000, |
1080 | 0x00000000, |
| 1079 | 0x3f800000, |
1081 | 0x3f800000, |
| 1080 | 0xc0016900, |
1082 | 0xc0016900, |
| 1081 | 0x000000a4, |
1083 | 0x000000a4, |
| 1082 | 0x80000000, |
1084 | 0x80000000, |
| 1083 | 0xc0016900, |
1085 | 0xc0016900, |
| 1084 | 0x000000a5, |
1086 | 0x000000a5, |
| 1085 | 0x20002000, |
1087 | 0x20002000, |
| 1086 | 0xc0026900, |
1088 | 0xc0026900, |
| 1087 | 0x000000c4, |
1089 | 0x000000c4, |
| 1088 | 0x00000000, |
1090 | 0x00000000, |
| 1089 | 0x3f800000, |
1091 | 0x3f800000, |
| 1090 | 0xc0016900, |
1092 | 0xc0016900, |
| 1091 | 0x000000a6, |
1093 | 0x000000a6, |
| 1092 | 0x80000000, |
1094 | 0x80000000, |
| 1093 | 0xc0016900, |
1095 | 0xc0016900, |
| 1094 | 0x000000a7, |
1096 | 0x000000a7, |
| 1095 | 0x20002000, |
1097 | 0x20002000, |
| 1096 | 0xc0026900, |
1098 | 0xc0026900, |
| 1097 | 0x000000c6, |
1099 | 0x000000c6, |
| 1098 | 0x00000000, |
1100 | 0x00000000, |
| 1099 | 0x3f800000, |
1101 | 0x3f800000, |
| 1100 | 0xc0016900, |
1102 | 0xc0016900, |
| 1101 | 0x000000a8, |
1103 | 0x000000a8, |
| 1102 | 0x80000000, |
1104 | 0x80000000, |
| 1103 | 0xc0016900, |
1105 | 0xc0016900, |
| 1104 | 0x000000a9, |
1106 | 0x000000a9, |
| 1105 | 0x20002000, |
1107 | 0x20002000, |
| 1106 | 0xc0026900, |
1108 | 0xc0026900, |
| 1107 | 0x000000c8, |
1109 | 0x000000c8, |
| 1108 | 0x00000000, |
1110 | 0x00000000, |
| 1109 | 0x3f800000, |
1111 | 0x3f800000, |
| 1110 | 0xc0016900, |
1112 | 0xc0016900, |
| 1111 | 0x000000aa, |
1113 | 0x000000aa, |
| 1112 | 0x80000000, |
1114 | 0x80000000, |
| 1113 | 0xc0016900, |
1115 | 0xc0016900, |
| 1114 | 0x000000ab, |
1116 | 0x000000ab, |
| 1115 | 0x20002000, |
1117 | 0x20002000, |
| 1116 | 0xc0026900, |
1118 | 0xc0026900, |
| 1117 | 0x000000ca, |
1119 | 0x000000ca, |
| 1118 | 0x00000000, |
1120 | 0x00000000, |
| 1119 | 0x3f800000, |
1121 | 0x3f800000, |
| 1120 | 0xc0016900, |
1122 | 0xc0016900, |
| 1121 | 0x000000ac, |
1123 | 0x000000ac, |
| 1122 | 0x80000000, |
1124 | 0x80000000, |
| 1123 | 0xc0016900, |
1125 | 0xc0016900, |
| 1124 | 0x000000ad, |
1126 | 0x000000ad, |
| 1125 | 0x20002000, |
1127 | 0x20002000, |
| 1126 | 0xc0026900, |
1128 | 0xc0026900, |
| 1127 | 0x000000cc, |
1129 | 0x000000cc, |
| 1128 | 0x00000000, |
1130 | 0x00000000, |
| 1129 | 0x3f800000, |
1131 | 0x3f800000, |
| 1130 | 0xc0016900, |
1132 | 0xc0016900, |
| 1131 | 0x000000ae, |
1133 | 0x000000ae, |
| 1132 | 0x80000000, |
1134 | 0x80000000, |
| 1133 | 0xc0016900, |
1135 | 0xc0016900, |
| 1134 | 0x000000af, |
1136 | 0x000000af, |
| 1135 | 0x20002000, |
1137 | 0x20002000, |
| 1136 | 0xc0026900, |
1138 | 0xc0026900, |
| 1137 | 0x000000ce, |
1139 | 0x000000ce, |
| 1138 | 0x00000000, |
1140 | 0x00000000, |
| 1139 | 0x3f800000, |
1141 | 0x3f800000, |
| 1140 | 0xc0016900, |
1142 | 0xc0016900, |
| 1141 | 0x000000b0, |
1143 | 0x000000b0, |
| 1142 | 0x80000000, |
1144 | 0x80000000, |
| 1143 | 0xc0016900, |
1145 | 0xc0016900, |
| 1144 | 0x000000b1, |
1146 | 0x000000b1, |
| 1145 | 0x20002000, |
1147 | 0x20002000, |
| 1146 | 0xc0026900, |
1148 | 0xc0026900, |
| 1147 | 0x000000d0, |
1149 | 0x000000d0, |
| 1148 | 0x00000000, |
1150 | 0x00000000, |
| 1149 | 0x3f800000, |
1151 | 0x3f800000, |
| 1150 | 0xc0016900, |
1152 | 0xc0016900, |
| 1151 | 0x000000b2, |
1153 | 0x000000b2, |
| 1152 | 0x80000000, |
1154 | 0x80000000, |
| 1153 | 0xc0016900, |
1155 | 0xc0016900, |
| 1154 | 0x000000b3, |
1156 | 0x000000b3, |
| 1155 | 0x20002000, |
1157 | 0x20002000, |
| 1156 | 0xc0026900, |
1158 | 0xc0026900, |
| 1157 | 0x000000d2, |
1159 | 0x000000d2, |
| 1158 | 0x00000000, |
1160 | 0x00000000, |
| 1159 | 0x3f800000, |
1161 | 0x3f800000, |
| 1160 | 0xc0016900, |
1162 | 0xc0016900, |
| 1161 | 0x00000293, |
1163 | 0x00000293, |
| 1162 | 0x00514000, |
1164 | 0x00514000, |
| 1163 | 0xc0016900, |
1165 | 0xc0016900, |
| 1164 | 0x00000300, |
1166 | 0x00000300, |
| 1165 | 0x00000000, |
1167 | 0x00000000, |
| 1166 | 0xc0016900, |
1168 | 0xc0016900, |
| 1167 | 0x00000301, |
1169 | 0x00000301, |
| 1168 | 0x00000000, |
1170 | 0x00000000, |
| 1169 | 0xc0016900, |
1171 | 0xc0016900, |
| 1170 | 0x00000312, |
1172 | 0x00000312, |
| 1171 | 0xffffffff, |
1173 | 0xffffffff, |
| 1172 | 0xc0016900, |
1174 | 0xc0016900, |
| 1173 | 0x00000307, |
1175 | 0x00000307, |
| 1174 | 0x00000000, |
1176 | 0x00000000, |
| 1175 | 0xc0016900, |
1177 | 0xc0016900, |
| 1176 | 0x00000308, |
1178 | 0x00000308, |
| 1177 | 0x00000000, |
1179 | 0x00000000, |
| 1178 | 0xc0016900, |
1180 | 0xc0016900, |
| 1179 | 0x00000283, |
1181 | 0x00000283, |
| 1180 | 0x00000000, |
1182 | 0x00000000, |
| 1181 | 0xc0016900, |
1183 | 0xc0016900, |
| 1182 | 0x00000292, |
1184 | 0x00000292, |
| 1183 | 0x00000000, |
1185 | 0x00000000, |
| 1184 | 0xc0066900, |
1186 | 0xc0066900, |
| 1185 | 0x0000010f, |
1187 | 0x0000010f, |
| 1186 | 0x00000000, |
1188 | 0x00000000, |
| 1187 | 0x00000000, |
1189 | 0x00000000, |
| 1188 | 0x00000000, |
1190 | 0x00000000, |
| 1189 | 0x00000000, |
1191 | 0x00000000, |
| 1190 | 0x00000000, |
1192 | 0x00000000, |
| 1191 | 0x00000000, |
1193 | 0x00000000, |
| 1192 | 0xc0016900, |
1194 | 0xc0016900, |
| 1193 | 0x00000206, |
1195 | 0x00000206, |
| 1194 | 0x00000000, |
1196 | 0x00000000, |
| 1195 | 0xc0016900, |
1197 | 0xc0016900, |
| 1196 | 0x00000207, |
1198 | 0x00000207, |
| 1197 | 0x00000000, |
1199 | 0x00000000, |
| 1198 | 0xc0016900, |
1200 | 0xc0016900, |
| 1199 | 0x00000208, |
1201 | 0x00000208, |
| 1200 | 0x00000000, |
1202 | 0x00000000, |
| 1201 | 0xc0046900, |
1203 | 0xc0046900, |
| 1202 | 0x00000303, |
1204 | 0x00000303, |
| 1203 | 0x3f800000, |
1205 | 0x3f800000, |
| 1204 | 0x3f800000, |
1206 | 0x3f800000, |
| 1205 | 0x3f800000, |
1207 | 0x3f800000, |
| 1206 | 0x3f800000, |
1208 | 0x3f800000, |
| 1207 | 0xc0016900, |
1209 | 0xc0016900, |
| 1208 | 0x00000205, |
1210 | 0x00000205, |
| 1209 | 0x00000004, |
1211 | 0x00000004, |
| 1210 | 0xc0016900, |
1212 | 0xc0016900, |
| 1211 | 0x00000280, |
1213 | 0x00000280, |
| 1212 | 0x00000000, |
1214 | 0x00000000, |
| 1213 | 0xc0016900, |
1215 | 0xc0016900, |
| 1214 | 0x00000281, |
1216 | 0x00000281, |
| 1215 | 0x00000000, |
1217 | 0x00000000, |
| 1216 | 0xc0016900, |
1218 | 0xc0016900, |
| 1217 | 0x0000037e, |
1219 | 0x0000037e, |
| 1218 | 0x00000000, |
1220 | 0x00000000, |
| 1219 | 0xc0016900, |
1221 | 0xc0016900, |
| 1220 | 0x00000382, |
1222 | 0x00000382, |
| 1221 | 0x00000000, |
1223 | 0x00000000, |
| 1222 | 0xc0016900, |
1224 | 0xc0016900, |
| 1223 | 0x00000380, |
1225 | 0x00000380, |
| 1224 | 0x00000000, |
1226 | 0x00000000, |
| 1225 | 0xc0016900, |
1227 | 0xc0016900, |
| 1226 | 0x00000383, |
1228 | 0x00000383, |
| 1227 | 0x00000000, |
1229 | 0x00000000, |
| 1228 | 0xc0016900, |
1230 | 0xc0016900, |
| 1229 | 0x00000381, |
1231 | 0x00000381, |
| 1230 | 0x00000000, |
1232 | 0x00000000, |
| 1231 | 0xc0016900, |
1233 | 0xc0016900, |
| 1232 | 0x00000282, |
1234 | 0x00000282, |
| 1233 | 0x00000008, |
1235 | 0x00000008, |
| 1234 | 0xc0016900, |
1236 | 0xc0016900, |
| 1235 | 0x00000302, |
1237 | 0x00000302, |
| 1236 | 0x0000002d, |
1238 | 0x0000002d, |
| 1237 | 0xc0016900, |
1239 | 0xc0016900, |
| 1238 | 0x0000037f, |
1240 | 0x0000037f, |
| 1239 | 0x00000000, |
1241 | 0x00000000, |
| 1240 | 0xc0016900, |
1242 | 0xc0016900, |
| 1241 | 0x000001b2, |
1243 | 0x000001b2, |
| 1242 | 0x00000001, |
1244 | 0x00000001, |
| 1243 | 0xc0016900, |
1245 | 0xc0016900, |
| 1244 | 0x000001b6, |
1246 | 0x000001b6, |
| 1245 | 0x00000000, |
1247 | 0x00000000, |
| 1246 | 0xc0016900, |
1248 | 0xc0016900, |
| 1247 | 0x000001b7, |
1249 | 0x000001b7, |
| 1248 | 0x00000000, |
1250 | 0x00000000, |
| 1249 | 0xc0016900, |
1251 | 0xc0016900, |
| 1250 | 0x000001b8, |
1252 | 0x000001b8, |
| 1251 | 0x00000000, |
1253 | 0x00000000, |
| 1252 | 0xc0016900, |
1254 | 0xc0016900, |
| 1253 | 0x000001b9, |
1255 | 0x000001b9, |
| 1254 | 0x00000000, |
1256 | 0x00000000, |
| 1255 | 0xc0016900, |
1257 | 0xc0016900, |
| 1256 | 0x00000225, |
1258 | 0x00000225, |
| 1257 | 0x00000000, |
1259 | 0x00000000, |
| 1258 | 0xc0016900, |
1260 | 0xc0016900, |
| 1259 | 0x00000229, |
1261 | 0x00000229, |
| 1260 | 0x00000000, |
1262 | 0x00000000, |
| 1261 | 0xc0016900, |
1263 | 0xc0016900, |
| 1262 | 0x00000237, |
1264 | 0x00000237, |
| 1263 | 0x00000000, |
1265 | 0x00000000, |
| 1264 | 0xc0016900, |
1266 | 0xc0016900, |
| 1265 | 0x00000100, |
1267 | 0x00000100, |
| 1266 | 0x00000800, |
1268 | 0x00000800, |
| 1267 | 0xc0016900, |
1269 | 0xc0016900, |
| 1268 | 0x00000101, |
1270 | 0x00000101, |
| 1269 | 0x00000000, |
1271 | 0x00000000, |
| 1270 | 0xc0016900, |
1272 | 0xc0016900, |
| 1271 | 0x00000102, |
1273 | 0x00000102, |
| 1272 | 0x00000000, |
1274 | 0x00000000, |
| 1273 | 0xc0016900, |
1275 | 0xc0016900, |
| 1274 | 0x000002a8, |
1276 | 0x000002a8, |
| 1275 | 0x00000000, |
1277 | 0x00000000, |
| 1276 | 0xc0016900, |
1278 | 0xc0016900, |
| 1277 | 0x000002a9, |
1279 | 0x000002a9, |
| 1278 | 0x00000000, |
1280 | 0x00000000, |
| 1279 | 0xc0016900, |
1281 | 0xc0016900, |
| 1280 | 0x00000103, |
1282 | 0x00000103, |
| 1281 | 0x00000000, |
1283 | 0x00000000, |
| 1282 | 0xc0016900, |
1284 | 0xc0016900, |
| 1283 | 0x00000284, |
1285 | 0x00000284, |
| 1284 | 0x00000000, |
1286 | 0x00000000, |
| 1285 | 0xc0016900, |
1287 | 0xc0016900, |
| 1286 | 0x00000290, |
1288 | 0x00000290, |
| 1287 | 0x00000000, |
1289 | 0x00000000, |
| 1288 | 0xc0016900, |
1290 | 0xc0016900, |
| 1289 | 0x00000285, |
1291 | 0x00000285, |
| 1290 | 0x00000000, |
1292 | 0x00000000, |
| 1291 | 0xc0016900, |
1293 | 0xc0016900, |
| 1292 | 0x00000286, |
1294 | 0x00000286, |
| 1293 | 0x00000000, |
1295 | 0x00000000, |
| 1294 | 0xc0016900, |
1296 | 0xc0016900, |
| 1295 | 0x00000287, |
1297 | 0x00000287, |
| 1296 | 0x00000000, |
1298 | 0x00000000, |
| 1297 | 0xc0016900, |
1299 | 0xc0016900, |
| 1298 | 0x00000288, |
1300 | 0x00000288, |
| 1299 | 0x00000000, |
1301 | 0x00000000, |
| 1300 | 0xc0016900, |
1302 | 0xc0016900, |
| 1301 | 0x00000289, |
1303 | 0x00000289, |
| 1302 | 0x00000000, |
1304 | 0x00000000, |
| 1303 | 0xc0016900, |
1305 | 0xc0016900, |
| 1304 | 0x0000028a, |
1306 | 0x0000028a, |
| 1305 | 0x00000000, |
1307 | 0x00000000, |
| 1306 | 0xc0016900, |
1308 | 0xc0016900, |
| 1307 | 0x0000028b, |
1309 | 0x0000028b, |
| 1308 | 0x00000000, |
1310 | 0x00000000, |
| 1309 | 0xc0016900, |
1311 | 0xc0016900, |
| 1310 | 0x0000028c, |
1312 | 0x0000028c, |
| 1311 | 0x00000000, |
1313 | 0x00000000, |
| 1312 | 0xc0016900, |
1314 | 0xc0016900, |
| 1313 | 0x0000028d, |
1315 | 0x0000028d, |
| 1314 | 0x00000000, |
1316 | 0x00000000, |
| 1315 | 0xc0016900, |
1317 | 0xc0016900, |
| 1316 | 0x0000028e, |
1318 | 0x0000028e, |
| 1317 | 0x00000000, |
1319 | 0x00000000, |
| 1318 | 0xc0016900, |
1320 | 0xc0016900, |
| 1319 | 0x0000028f, |
1321 | 0x0000028f, |
| 1320 | 0x00000000, |
1322 | 0x00000000, |
| 1321 | 0xc0016900, |
1323 | 0xc0016900, |
| 1322 | 0x000002a1, |
1324 | 0x000002a1, |
| 1323 | 0x00000000, |
1325 | 0x00000000, |
| 1324 | 0xc0016900, |
1326 | 0xc0016900, |
| 1325 | 0x000002a5, |
1327 | 0x000002a5, |
| 1326 | 0x00000000, |
1328 | 0x00000000, |
| 1327 | 0xc0016900, |
1329 | 0xc0016900, |
| 1328 | 0x000002ac, |
1330 | 0x000002ac, |
| 1329 | 0x00000000, |
1331 | 0x00000000, |
| 1330 | 0xc0016900, |
1332 | 0xc0016900, |
| 1331 | 0x000002ad, |
1333 | 0x000002ad, |
| 1332 | 0x00000000, |
1334 | 0x00000000, |
| 1333 | 0xc0016900, |
1335 | 0xc0016900, |
| 1334 | 0x000002ae, |
1336 | 0x000002ae, |
| 1335 | 0x00000000, |
1337 | 0x00000000, |
| 1336 | 0xc0016900, |
1338 | 0xc0016900, |
| 1337 | 0x000002c8, |
1339 | 0x000002c8, |
| 1338 | 0x00000000, |
1340 | 0x00000000, |
| 1339 | 0xc0016900, |
1341 | 0xc0016900, |
| 1340 | 0x00000206, |
1342 | 0x00000206, |
| 1341 | 0x00000100, |
1343 | 0x00000100, |
| 1342 | 0xc0016900, |
1344 | 0xc0016900, |
| 1343 | 0x00000204, |
1345 | 0x00000204, |
| 1344 | 0x00010000, |
1346 | 0x00010000, |
| 1345 | 0xc0036e00, |
1347 | 0xc0036e00, |
| 1346 | 0x00000000, |
1348 | 0x00000000, |
| 1347 | 0x00000012, |
1349 | 0x00000012, |
| 1348 | 0x00000000, |
1350 | 0x00000000, |
| 1349 | 0x00000000, |
1351 | 0x00000000, |
| 1350 | 0xc0016900, |
1352 | 0xc0016900, |
| 1351 | 0x0000008f, |
1353 | 0x0000008f, |
| 1352 | 0x0000000f, |
1354 | 0x0000000f, |
| 1353 | 0xc0016900, |
1355 | 0xc0016900, |
| 1354 | 0x000001e8, |
1356 | 0x000001e8, |
| 1355 | 0x00000001, |
1357 | 0x00000001, |
| 1356 | 0xc0016900, |
1358 | 0xc0016900, |
| 1357 | 0x00000202, |
1359 | 0x00000202, |
| 1358 | 0x00cc0000, |
1360 | 0x00cc0000, |
| 1359 | 0xc0016900, |
1361 | 0xc0016900, |
| 1360 | 0x00000205, |
1362 | 0x00000205, |
| 1361 | 0x00000244, |
1363 | 0x00000244, |
| 1362 | 0xc0016900, |
1364 | 0xc0016900, |
| 1363 | 0x00000203, |
1365 | 0x00000203, |
| 1364 | 0x00000210, |
1366 | 0x00000210, |
| 1365 | 0xc0016900, |
1367 | 0xc0016900, |
| 1366 | 0x000001b1, |
1368 | 0x000001b1, |
| 1367 | 0x00000000, |
1369 | 0x00000000, |
| 1368 | 0xc0016900, |
1370 | 0xc0016900, |
| 1369 | 0x00000185, |
1371 | 0x00000185, |
| 1370 | 0x00000000, |
1372 | 0x00000000, |
| 1371 | 0xc0016900, |
1373 | 0xc0016900, |
| 1372 | 0x000001b3, |
1374 | 0x000001b3, |
| 1373 | 0x00000001, |
1375 | 0x00000001, |
| 1374 | 0xc0016900, |
1376 | 0xc0016900, |
| 1375 | 0x000001b4, |
1377 | 0x000001b4, |
| 1376 | 0x00000000, |
1378 | 0x00000000, |
| 1377 | 0xc0016900, |
1379 | 0xc0016900, |
| 1378 | 0x00000191, |
1380 | 0x00000191, |
| 1379 | 0x00000b00, |
1381 | 0x00000b00, |
| 1380 | 0xc0016900, |
1382 | 0xc0016900, |
| 1381 | 0x000001b5, |
1383 | 0x000001b5, |
| 1382 | 0x00000000, |
1384 | 0x00000000, |
| 1383 | }; |
1385 | }; |
| 1384 | 1386 | ||
| 1385 | const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state); |
1387 | const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state); |
| 1386 | const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state); |
1388 | const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state); |
| 1387 | 1389 | ||
| 1388 | 1390 | ||
| 1389 | int R600_solid_ps(struct radeon_device *rdev, uint32_t* shader); |
1391 | int R600_solid_ps(struct radeon_device *rdev, uint32_t* shader); |
| 1390 | int R600_solid_vs(struct radeon_device *rdev, uint32_t* shader); |
1392 | int R600_solid_vs(struct radeon_device *rdev, uint32_t* shader); |
| 1391 | 1393 | ||
| 1392 | #define COLOR_8_8_8_8 0x1a |
1394 | #define COLOR_8_8_8_8 0x1a |
| 1393 | 1395 | ||
| 1394 | /* emits 21 on rv770+, 23 on r600 */ |
1396 | /* emits 21 on rv770+, 23 on r600 */ |
| 1395 | static void |
1397 | static void |
| 1396 | set_render_target(struct radeon_device *rdev, int format, |
1398 | set_render_target(struct radeon_device *rdev, int format, |
| 1397 | int w, int h, u64 gpu_addr) |
1399 | int w, int h, u64 gpu_addr) |
| 1398 | { |
1400 | { |
| 1399 | u32 cb_color_info; |
1401 | u32 cb_color_info; |
| 1400 | int pitch, slice; |
1402 | int pitch, slice; |
| 1401 | 1403 | ||
| 1402 | h = (h + 7) & ~7; |
1404 | h = (h + 7) & ~7; |
| 1403 | if (h < 8) |
1405 | if (h < 8) |
| 1404 | h = 8; |
1406 | h = 8; |
| 1405 | 1407 | ||
| 1406 | cb_color_info = ((format << 2) | (1 << 27)); |
1408 | cb_color_info = ((format << 2) | (1 << 27)); |
| 1407 | pitch = (w / 8) - 1; |
1409 | pitch = (w / 8) - 1; |
| 1408 | slice = ((w * h) / 64) - 1; |
1410 | slice = ((w * h) / 64) - 1; |
| 1409 | 1411 | ||
| 1410 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
1412 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 1411 | radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
1413 | radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 1412 | radeon_ring_write(rdev, gpu_addr >> 8); |
1414 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 1413 | 1415 | ||
| 1414 | if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { |
1416 | if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { |
| 1415 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); |
1417 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); |
| 1416 | radeon_ring_write(rdev, 2 << 0); |
1418 | radeon_ring_write(rdev, 2 << 0); |
| 1417 | } |
1419 | } |
| 1418 | 1420 | ||
| 1419 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
1421 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 1420 | radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
1422 | radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 1421 | radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); |
1423 | radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); |
| 1422 | 1424 | ||
| 1423 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
1425 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 1424 | radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
1426 | radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 1425 | radeon_ring_write(rdev, 0); |
1427 | radeon_ring_write(rdev, 0); |
| 1426 | 1428 | ||
| 1427 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
1429 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 1428 | radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
1430 | radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 1429 | radeon_ring_write(rdev, cb_color_info); |
1431 | radeon_ring_write(rdev, cb_color_info); |
| 1430 | 1432 | ||
| 1431 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
1433 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 1432 | radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
1434 | radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 1433 | radeon_ring_write(rdev, 0); |
1435 | radeon_ring_write(rdev, 0); |
| 1434 | 1436 | ||
| 1435 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
1437 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 1436 | radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
1438 | radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 1437 | radeon_ring_write(rdev, 0); |
1439 | radeon_ring_write(rdev, 0); |
| 1438 | 1440 | ||
| 1439 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
1441 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 1440 | radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
1442 | radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 1441 | radeon_ring_write(rdev, 0); |
1443 | radeon_ring_write(rdev, 0); |
| 1442 | } |
1444 | } |
| 1443 | 1445 | ||
| 1444 | 1446 | ||
| 1445 | /* emits 5dw */ |
1447 | /* emits 5dw */ |
| 1446 | static void |
1448 | static void |
| 1447 | cp_set_surface_sync(struct radeon_device *rdev, |
1449 | cp_set_surface_sync(struct radeon_device *rdev, |
| 1448 | u32 sync_type, u32 size, |
1450 | u32 sync_type, u32 size, |
| 1449 | u64 mc_addr) |
1451 | u64 mc_addr) |
| 1450 | { |
1452 | { |
| 1451 | u32 cp_coher_size; |
1453 | u32 cp_coher_size; |
| 1452 | 1454 | ||
| 1453 | if (size == 0xffffffff) |
1455 | if (size == 0xffffffff) |
| 1454 | cp_coher_size = 0xffffffff; |
1456 | cp_coher_size = 0xffffffff; |
| 1455 | else |
1457 | else |
| 1456 | cp_coher_size = ((size + 255) >> 8); |
1458 | cp_coher_size = ((size + 255) >> 8); |
| 1457 | 1459 | ||
| 1458 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
1460 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 1459 | radeon_ring_write(rdev, sync_type); |
1461 | radeon_ring_write(rdev, sync_type); |
| 1460 | radeon_ring_write(rdev, cp_coher_size); |
1462 | radeon_ring_write(rdev, cp_coher_size); |
| 1461 | radeon_ring_write(rdev, mc_addr >> 8); |
1463 | radeon_ring_write(rdev, mc_addr >> 8); |
| 1462 | radeon_ring_write(rdev, 10); /* poll interval */ |
1464 | radeon_ring_write(rdev, 10); /* poll interval */ |
| 1463 | } |
1465 | } |
| 1464 | 1466 | ||
| 1465 | /* emits 14 */ |
1467 | /* emits 14 */ |
| 1466 | static void |
1468 | static void |
| 1467 | set_default_state(struct radeon_device *rdev, |
1469 | set_default_state(struct radeon_device *rdev, |
| 1468 | u64 state_gpu_addr, u32 state_len) |
1470 | u64 state_gpu_addr, u32 state_len) |
| 1469 | { |
1471 | { |
| 1470 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; |
1472 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; |
| 1471 | u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; |
1473 | u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; |
| 1472 | int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; |
1474 | int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; |
| 1473 | int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
1475 | int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
| 1474 | int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
1476 | int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
| 1475 | u64 gpu_addr; |
1477 | u64 gpu_addr; |
| 1476 | int dwords; |
1478 | int dwords; |
| 1477 | 1479 | ||
| 1478 | switch (rdev->family) { |
1480 | switch (rdev->family) { |
| 1479 | case CHIP_R600: |
1481 | case CHIP_R600: |
| 1480 | num_ps_gprs = 192; |
1482 | num_ps_gprs = 192; |
| 1481 | num_vs_gprs = 56; |
1483 | num_vs_gprs = 56; |
| 1482 | num_temp_gprs = 4; |
1484 | num_temp_gprs = 4; |
| 1483 | num_gs_gprs = 0; |
1485 | num_gs_gprs = 0; |
| 1484 | num_es_gprs = 0; |
1486 | num_es_gprs = 0; |
| 1485 | num_ps_threads = 136; |
1487 | num_ps_threads = 136; |
| 1486 | num_vs_threads = 48; |
1488 | num_vs_threads = 48; |
| 1487 | num_gs_threads = 4; |
1489 | num_gs_threads = 4; |
| 1488 | num_es_threads = 4; |
1490 | num_es_threads = 4; |
| 1489 | num_ps_stack_entries = 128; |
1491 | num_ps_stack_entries = 128; |
| 1490 | num_vs_stack_entries = 128; |
1492 | num_vs_stack_entries = 128; |
| 1491 | num_gs_stack_entries = 0; |
1493 | num_gs_stack_entries = 0; |
| 1492 | num_es_stack_entries = 0; |
1494 | num_es_stack_entries = 0; |
| 1493 | break; |
1495 | break; |
| 1494 | case CHIP_RV630: |
1496 | case CHIP_RV630: |
| 1495 | case CHIP_RV635: |
1497 | case CHIP_RV635: |
| 1496 | num_ps_gprs = 84; |
1498 | num_ps_gprs = 84; |
| 1497 | num_vs_gprs = 36; |
1499 | num_vs_gprs = 36; |
| 1498 | num_temp_gprs = 4; |
1500 | num_temp_gprs = 4; |
| 1499 | num_gs_gprs = 0; |
1501 | num_gs_gprs = 0; |
| 1500 | num_es_gprs = 0; |
1502 | num_es_gprs = 0; |
| 1501 | num_ps_threads = 144; |
1503 | num_ps_threads = 144; |
| 1502 | num_vs_threads = 40; |
1504 | num_vs_threads = 40; |
| 1503 | num_gs_threads = 4; |
1505 | num_gs_threads = 4; |
| 1504 | num_es_threads = 4; |
1506 | num_es_threads = 4; |
| 1505 | num_ps_stack_entries = 40; |
1507 | num_ps_stack_entries = 40; |
| 1506 | num_vs_stack_entries = 40; |
1508 | num_vs_stack_entries = 40; |
| 1507 | num_gs_stack_entries = 32; |
1509 | num_gs_stack_entries = 32; |
| 1508 | num_es_stack_entries = 16; |
1510 | num_es_stack_entries = 16; |
| 1509 | break; |
1511 | break; |
| 1510 | case CHIP_RV610: |
1512 | case CHIP_RV610: |
| 1511 | case CHIP_RV620: |
1513 | case CHIP_RV620: |
| 1512 | case CHIP_RS780: |
1514 | case CHIP_RS780: |
| 1513 | case CHIP_RS880: |
1515 | case CHIP_RS880: |
| 1514 | default: |
1516 | default: |
| 1515 | num_ps_gprs = 84; |
1517 | num_ps_gprs = 84; |
| 1516 | num_vs_gprs = 36; |
1518 | num_vs_gprs = 36; |
| 1517 | num_temp_gprs = 4; |
1519 | num_temp_gprs = 4; |
| 1518 | num_gs_gprs = 0; |
1520 | num_gs_gprs = 0; |
| 1519 | num_es_gprs = 0; |
1521 | num_es_gprs = 0; |
| 1520 | num_ps_threads = 136; |
1522 | num_ps_threads = 136; |
| 1521 | num_vs_threads = 48; |
1523 | num_vs_threads = 48; |
| 1522 | num_gs_threads = 4; |
1524 | num_gs_threads = 4; |
| 1523 | num_es_threads = 4; |
1525 | num_es_threads = 4; |
| 1524 | num_ps_stack_entries = 40; |
1526 | num_ps_stack_entries = 40; |
| 1525 | num_vs_stack_entries = 40; |
1527 | num_vs_stack_entries = 40; |
| 1526 | num_gs_stack_entries = 32; |
1528 | num_gs_stack_entries = 32; |
| 1527 | num_es_stack_entries = 16; |
1529 | num_es_stack_entries = 16; |
| 1528 | break; |
1530 | break; |
| 1529 | case CHIP_RV670: |
1531 | case CHIP_RV670: |
| 1530 | num_ps_gprs = 144; |
1532 | num_ps_gprs = 144; |
| 1531 | num_vs_gprs = 40; |
1533 | num_vs_gprs = 40; |
| 1532 | num_temp_gprs = 4; |
1534 | num_temp_gprs = 4; |
| 1533 | num_gs_gprs = 0; |
1535 | num_gs_gprs = 0; |
| 1534 | num_es_gprs = 0; |
1536 | num_es_gprs = 0; |
| 1535 | num_ps_threads = 136; |
1537 | num_ps_threads = 136; |
| 1536 | num_vs_threads = 48; |
1538 | num_vs_threads = 48; |
| 1537 | num_gs_threads = 4; |
1539 | num_gs_threads = 4; |
| 1538 | num_es_threads = 4; |
1540 | num_es_threads = 4; |
| 1539 | num_ps_stack_entries = 40; |
1541 | num_ps_stack_entries = 40; |
| 1540 | num_vs_stack_entries = 40; |
1542 | num_vs_stack_entries = 40; |
| 1541 | num_gs_stack_entries = 32; |
1543 | num_gs_stack_entries = 32; |
| 1542 | num_es_stack_entries = 16; |
1544 | num_es_stack_entries = 16; |
| 1543 | break; |
1545 | break; |
| 1544 | case CHIP_RV770: |
1546 | case CHIP_RV770: |
| 1545 | num_ps_gprs = 192; |
1547 | num_ps_gprs = 192; |
| 1546 | num_vs_gprs = 56; |
1548 | num_vs_gprs = 56; |
| 1547 | num_temp_gprs = 4; |
1549 | num_temp_gprs = 4; |
| 1548 | num_gs_gprs = 0; |
1550 | num_gs_gprs = 0; |
| 1549 | num_es_gprs = 0; |
1551 | num_es_gprs = 0; |
| 1550 | num_ps_threads = 188; |
1552 | num_ps_threads = 188; |
| 1551 | num_vs_threads = 60; |
1553 | num_vs_threads = 60; |
| 1552 | num_gs_threads = 0; |
1554 | num_gs_threads = 0; |
| 1553 | num_es_threads = 0; |
1555 | num_es_threads = 0; |
| 1554 | num_ps_stack_entries = 256; |
1556 | num_ps_stack_entries = 256; |
| 1555 | num_vs_stack_entries = 256; |
1557 | num_vs_stack_entries = 256; |
| 1556 | num_gs_stack_entries = 0; |
1558 | num_gs_stack_entries = 0; |
| 1557 | num_es_stack_entries = 0; |
1559 | num_es_stack_entries = 0; |
| 1558 | break; |
1560 | break; |
| 1559 | case CHIP_RV730: |
1561 | case CHIP_RV730: |
| 1560 | case CHIP_RV740: |
1562 | case CHIP_RV740: |
| 1561 | num_ps_gprs = 84; |
1563 | num_ps_gprs = 84; |
| 1562 | num_vs_gprs = 36; |
1564 | num_vs_gprs = 36; |
| 1563 | num_temp_gprs = 4; |
1565 | num_temp_gprs = 4; |
| 1564 | num_gs_gprs = 0; |
1566 | num_gs_gprs = 0; |
| 1565 | num_es_gprs = 0; |
1567 | num_es_gprs = 0; |
| 1566 | num_ps_threads = 188; |
1568 | num_ps_threads = 188; |
| 1567 | num_vs_threads = 60; |
1569 | num_vs_threads = 60; |
| 1568 | num_gs_threads = 0; |
1570 | num_gs_threads = 0; |
| 1569 | num_es_threads = 0; |
1571 | num_es_threads = 0; |
| 1570 | num_ps_stack_entries = 128; |
1572 | num_ps_stack_entries = 128; |
| 1571 | num_vs_stack_entries = 128; |
1573 | num_vs_stack_entries = 128; |
| 1572 | num_gs_stack_entries = 0; |
1574 | num_gs_stack_entries = 0; |
| 1573 | num_es_stack_entries = 0; |
1575 | num_es_stack_entries = 0; |
| 1574 | break; |
1576 | break; |
| 1575 | case CHIP_RV710: |
1577 | case CHIP_RV710: |
| 1576 | num_ps_gprs = 192; |
1578 | num_ps_gprs = 192; |
| 1577 | num_vs_gprs = 56; |
1579 | num_vs_gprs = 56; |
| 1578 | num_temp_gprs = 4; |
1580 | num_temp_gprs = 4; |
| 1579 | num_gs_gprs = 0; |
1581 | num_gs_gprs = 0; |
| 1580 | num_es_gprs = 0; |
1582 | num_es_gprs = 0; |
| 1581 | num_ps_threads = 144; |
1583 | num_ps_threads = 144; |
| 1582 | num_vs_threads = 48; |
1584 | num_vs_threads = 48; |
| 1583 | num_gs_threads = 0; |
1585 | num_gs_threads = 0; |
| 1584 | num_es_threads = 0; |
1586 | num_es_threads = 0; |
| 1585 | num_ps_stack_entries = 128; |
1587 | num_ps_stack_entries = 128; |
| 1586 | num_vs_stack_entries = 128; |
1588 | num_vs_stack_entries = 128; |
| 1587 | num_gs_stack_entries = 0; |
1589 | num_gs_stack_entries = 0; |
| 1588 | num_es_stack_entries = 0; |
1590 | num_es_stack_entries = 0; |
| 1589 | break; |
1591 | break; |
| 1590 | } |
1592 | } |
| 1591 | 1593 | ||
| 1592 | if ((rdev->family == CHIP_RV610) || |
1594 | if ((rdev->family == CHIP_RV610) || |
| 1593 | (rdev->family == CHIP_RV620) || |
1595 | (rdev->family == CHIP_RV620) || |
| 1594 | (rdev->family == CHIP_RS780) || |
1596 | (rdev->family == CHIP_RS780) || |
| 1595 | (rdev->family == CHIP_RS880) || |
1597 | (rdev->family == CHIP_RS880) || |
| 1596 | (rdev->family == CHIP_RV710)) |
1598 | (rdev->family == CHIP_RV710)) |
| 1597 | sq_config = 0; |
1599 | sq_config = 0; |
| 1598 | else |
1600 | else |
| 1599 | sq_config = VC_ENABLE; |
1601 | sq_config = VC_ENABLE; |
| 1600 | 1602 | ||
| 1601 | sq_config |= (DX9_CONSTS | |
1603 | sq_config |= (DX9_CONSTS | |
| 1602 | ALU_INST_PREFER_VECTOR | |
1604 | ALU_INST_PREFER_VECTOR | |
| 1603 | PS_PRIO(0) | |
1605 | PS_PRIO(0) | |
| 1604 | VS_PRIO(1) | |
1606 | VS_PRIO(1) | |
| 1605 | GS_PRIO(2) | |
1607 | GS_PRIO(2) | |
| 1606 | ES_PRIO(3)); |
1608 | ES_PRIO(3)); |
| 1607 | 1609 | ||
| 1608 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | |
1610 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | |
| 1609 | NUM_VS_GPRS(num_vs_gprs) | |
1611 | NUM_VS_GPRS(num_vs_gprs) | |
| 1610 | NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
1612 | NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
| 1611 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
1613 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
| 1612 | NUM_ES_GPRS(num_es_gprs)); |
1614 | NUM_ES_GPRS(num_es_gprs)); |
| 1613 | sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
1615 | sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
| 1614 | NUM_VS_THREADS(num_vs_threads) | |
1616 | NUM_VS_THREADS(num_vs_threads) | |
| 1615 | NUM_GS_THREADS(num_gs_threads) | |
1617 | NUM_GS_THREADS(num_gs_threads) | |
| 1616 | NUM_ES_THREADS(num_es_threads)); |
1618 | NUM_ES_THREADS(num_es_threads)); |
| 1617 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
1619 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
| 1618 | NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
1620 | NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
| 1619 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
1621 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
| 1620 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
1622 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
| 1621 | 1623 | ||
| 1622 | /* emit an IB pointing at default state */ |
1624 | /* emit an IB pointing at default state */ |
| 1623 | dwords = (state_len + 0xf) & ~0xf; |
1625 | dwords = (state_len + 0xf) & ~0xf; |
| 1624 | gpu_addr = state_gpu_addr; |
1626 | gpu_addr = state_gpu_addr; |
| 1625 | 1627 | ||
| 1626 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
1628 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
| 1627 | radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); |
1629 | radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); |
| 1628 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
1630 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
| 1629 | radeon_ring_write(rdev, dwords); |
1631 | radeon_ring_write(rdev, dwords); |
| 1630 | 1632 | ||
| 1631 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); |
1633 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); |
| 1632 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); |
1634 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); |
| 1633 | /* SQ config */ |
1635 | /* SQ config */ |
| 1634 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
1636 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
| 1635 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
1637 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| 1636 | radeon_ring_write(rdev, sq_config); |
1638 | radeon_ring_write(rdev, sq_config); |
| 1637 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
1639 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
| 1638 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
1640 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
| 1639 | radeon_ring_write(rdev, sq_thread_resource_mgmt); |
1641 | radeon_ring_write(rdev, sq_thread_resource_mgmt); |
| 1640 | radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
1642 | radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
| 1641 | radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
1643 | radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
| 1642 | } |
1644 | } |
| 1643 | 1645 | ||
| 1644 | /* emits 12 */ |
1646 | /* emits 12 */ |
| 1645 | static void |
1647 | static void |
| 1646 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
1648 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
| 1647 | int x2, int y2) |
1649 | int x2, int y2) |
| 1648 | { |
1650 | { |
| 1649 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
1651 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 1650 | radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
1652 | radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 1651 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
1653 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
| 1652 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
1654 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| 1653 | 1655 | ||
| 1654 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
1656 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 1655 | radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
1657 | radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 1656 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
1658 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| 1657 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
1659 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| 1658 | 1660 | ||
| 1659 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
1661 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 1660 | radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
1662 | radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 1661 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
1663 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| 1662 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
1664 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| 1663 | } |
1665 | } |
| 1664 | 1666 | ||
| 1665 | static void |
1667 | static void |
| 1666 | draw_auto(struct radeon_device *rdev) |
1668 | draw_auto(struct radeon_device *rdev) |
| 1667 | { |
1669 | { |
| 1668 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
1670 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 1669 | radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
1671 | radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| 1670 | radeon_ring_write(rdev, DI_PT_RECTLIST); |
1672 | radeon_ring_write(rdev, DI_PT_RECTLIST); |
| 1671 | 1673 | ||
| 1672 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
1674 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
| 1673 | radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); |
1675 | radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); |
| 1674 | 1676 | ||
| 1675 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
1677 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
| 1676 | radeon_ring_write(rdev, 1); |
1678 | radeon_ring_write(rdev, 1); |
| 1677 | 1679 | ||
| 1678 | radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
1680 | radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
| 1679 | radeon_ring_write(rdev, 3); |
1681 | radeon_ring_write(rdev, 3); |
| 1680 | radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
1682 | radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
| 1681 | 1683 | ||
| 1682 | } |
1684 | } |
| 1683 | 1685 | ||
| 1684 | /* ALU clause insts */ |
1686 | /* ALU clause insts */ |
| 1685 | #define SRC0_SEL(x) (x) |
1687 | #define SRC0_SEL(x) (x) |
| 1686 | #define SRC1_SEL(x) (x) |
1688 | #define SRC1_SEL(x) (x) |
| 1687 | #define SRC2_SEL(x) (x) |
1689 | #define SRC2_SEL(x) (x) |
| 1688 | /* src[0-2]_sel */ |
1690 | /* src[0-2]_sel */ |
| 1689 | /* 0-127 GPR */ |
1691 | /* 0-127 GPR */ |
| 1690 | /* 128-159 kcache constants bank 0 */ |
1692 | /* 128-159 kcache constants bank 0 */ |
| 1691 | /* 160-191 kcache constants bank 1 */ |
1693 | /* 160-191 kcache constants bank 1 */ |
| 1692 | /* 248-255 special SQ_ALU_SRC_* (0, 1, etc.) */ |
1694 | /* 248-255 special SQ_ALU_SRC_* (0, 1, etc.) */ |
| 1693 | 1695 | ||
| 1694 | #define SRC0_REL(x) (x) |
1696 | #define SRC0_REL(x) (x) |
| 1695 | #define SRC1_REL(x) (x) |
1697 | #define SRC1_REL(x) (x) |
| 1696 | #define SRC2_REL(x) (x) |
1698 | #define SRC2_REL(x) (x) |
| 1697 | /* elem */ |
1699 | /* elem */ |
| 1698 | #define SRC0_ELEM(x) (x) |
1700 | #define SRC0_ELEM(x) (x) |
| 1699 | #define SRC1_ELEM(x) (x) |
1701 | #define SRC1_ELEM(x) (x) |
| 1700 | #define SRC2_ELEM(x) (x) |
1702 | #define SRC2_ELEM(x) (x) |
| 1701 | #define ELEM_X 0 |
1703 | #define ELEM_X 0 |
| 1702 | #define ELEM_Y 1 |
1704 | #define ELEM_Y 1 |
| 1703 | #define ELEM_Z 2 |
1705 | #define ELEM_Z 2 |
| 1704 | #define ELEM_W 3 |
1706 | #define ELEM_W 3 |
| 1705 | /* neg */ |
1707 | /* neg */ |
| 1706 | #define SRC0_NEG(x) (x) |
1708 | #define SRC0_NEG(x) (x) |
| 1707 | #define SRC1_NEG(x) (x) |
1709 | #define SRC1_NEG(x) (x) |
| 1708 | #define SRC2_NEG(x) (x) |
1710 | #define SRC2_NEG(x) (x) |
| 1709 | /* im */ |
1711 | /* im */ |
| 1710 | #define INDEX_MODE(x) (x) /* SQ_INDEX_* */ |
1712 | #define INDEX_MODE(x) (x) /* SQ_INDEX_* */ |
| 1711 | /* ps */ |
1713 | /* ps */ |
| 1712 | #define PRED_SEL(x) (x) /* SQ_PRED_SEL_* */ |
1714 | #define PRED_SEL(x) (x) /* SQ_PRED_SEL_* */ |
| 1713 | /* last */ |
1715 | /* last */ |
| 1714 | #define LAST(x) (x) |
1716 | #define LAST(x) (x) |
| 1715 | /* abs */ |
1717 | /* abs */ |
| 1716 | #define SRC0_ABS(x) (x) |
1718 | #define SRC0_ABS(x) (x) |
| 1717 | #define SRC1_ABS(x) (x) |
1719 | #define SRC1_ABS(x) (x) |
| 1718 | /* uem */ |
1720 | /* uem */ |
| 1719 | #define UPDATE_EXECUTE_MASK(x) (x) |
1721 | #define UPDATE_EXECUTE_MASK(x) (x) |
| 1720 | /* up */ |
1722 | /* up */ |
| 1721 | #define UPDATE_PRED(x) (x) |
1723 | #define UPDATE_PRED(x) (x) |
| 1722 | /* wm */ |
1724 | /* wm */ |
| 1723 | #define WRITE_MASK(x) (x) |
1725 | #define WRITE_MASK(x) (x) |
| 1724 | /* fm */ |
1726 | /* fm */ |
| 1725 | #define FOG_MERGE(x) (x) |
1727 | #define FOG_MERGE(x) (x) |
| 1726 | /* omod */ |
1728 | /* omod */ |
| 1727 | #define OMOD(x) (x) /* SQ_ALU_OMOD_* */ |
1729 | #define OMOD(x) (x) /* SQ_ALU_OMOD_* */ |
| 1728 | /* alu inst */ |
1730 | /* alu inst */ |
| 1729 | #define ALU_INST(x) (x) /* SQ_ALU_INST_* */ |
1731 | #define ALU_INST(x) (x) /* SQ_ALU_INST_* */ |
| 1730 | /*bs */ |
1732 | /*bs */ |
| 1731 | #define BANK_SWIZZLE(x) (x) /* SQ_ALU_VEC_* */ |
1733 | #define BANK_SWIZZLE(x) (x) /* SQ_ALU_VEC_* */ |
| 1732 | #define DST_GPR(x) (x) |
1734 | #define DST_GPR(x) (x) |
| 1733 | #define DST_REL(x) (x) |
1735 | #define DST_REL(x) (x) |
| 1734 | #define DST_ELEM(x) (x) |
1736 | #define DST_ELEM(x) (x) |
| 1735 | #define CLAMP(x) (x) |
1737 | #define CLAMP(x) (x) |
| 1736 | 1738 | ||
| 1737 | #define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \ |
1739 | #define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \ |
| 1738 | (((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \ |
1740 | (((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \ |
| 1739 | ((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \ |
1741 | ((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \ |
| 1740 | ((im) << 26) | ((ps) << 29) | ((last) << 31)) |
1742 | ((im) << 26) | ((ps) << 29) | ((last) << 31)) |
| 1741 | 1743 | ||
| 1742 | /* R7xx has alu_inst at a different slot, and no fog merge any more (no fix function fog any more) */ |
1744 | /* R7xx has alu_inst at a different slot, and no fog merge any more (no fix function fog any more) */ |
| 1743 | #define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
1745 | #define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
| 1744 | (((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ |
1746 | (((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ |
| 1745 | ((fm) << 5) | ((omod) << 6) | ((alu_inst) << 8) | ((bs) << 18) | ((dst_gpr) << 21) | \ |
1747 | ((fm) << 5) | ((omod) << 6) | ((alu_inst) << 8) | ((bs) << 18) | ((dst_gpr) << 21) | \ |
| 1746 | ((dr) << 28) | ((de) << 29) | ((clamp) << 31)) |
1748 | ((dr) << 28) | ((de) << 29) | ((clamp) << 31)) |
| 1747 | 1749 | ||
| 1748 | #define R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
1750 | #define R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
| 1749 | (((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ |
1751 | (((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ |
| 1750 | ((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \ |
1752 | ((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \ |
| 1751 | ((dr) << 28) | ((de) << 29) | ((clamp) << 31)) |
1753 | ((dr) << 28) | ((de) << 29) | ((clamp) << 31)) |
| 1752 | 1754 | ||
| 1753 | /* This is a general chipset macro, but due to selection by chipid typically not usable in static arrays */ |
1755 | /* This is a general chipset macro, but due to selection by chipid typically not usable in static arrays */ |
| 1754 | /* Fog is NOT USED on R7xx, even if specified. */ |
1756 | /* Fog is NOT USED on R7xx, even if specified. */ |
| 1755 | #define ALU_DWORD1_OP2(chipid, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
1757 | #define ALU_DWORD1_OP2(chipid, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
| 1756 | ((chipid) < CHIP_RV770 ? \ |
1758 | ((chipid) < CHIP_RV770 ? \ |
| 1757 | R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \ |
1759 | R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \ |
| 1758 | R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp)) |
1760 | R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp)) |
| 1759 | 1761 | ||
| 1760 | #define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
1762 | #define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
| 1761 | (((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \ |
1763 | (((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \ |
| 1762 | ((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \ |
1764 | ((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \ |
| 1763 | ((de) << 29) | ((clamp) << 31)) |
1765 | ((de) << 29) | ((clamp) << 31)) |
| 1764 | 1766 | ||
| 1765 | /* CF insts */ |
1767 | /* CF insts */ |
| 1766 | /* addr */ |
1768 | /* addr */ |
| 1767 | #define ADDR(x) (x) |
1769 | #define ADDR(x) (x) |
| 1768 | /* pc */ |
1770 | /* pc */ |
| 1769 | #define POP_COUNT(x) (x) |
1771 | #define POP_COUNT(x) (x) |
| 1770 | /* const */ |
1772 | /* const */ |
| 1771 | #define CF_CONST(x) (x) |
1773 | #define CF_CONST(x) (x) |
| 1772 | /* cond */ |
1774 | /* cond */ |
| 1773 | #define COND(x) (x) /* SQ_COND_* */ |
1775 | #define COND(x) (x) /* SQ_COND_* */ |
| 1774 | /* count */ |
1776 | /* count */ |
| 1775 | #define I_COUNT(x) ((x) ? ((x) - 1) : 0) |
1777 | #define I_COUNT(x) ((x) ? ((x) - 1) : 0) |
| 1776 | /*r7xx */ |
1778 | /*r7xx */ |
| 1777 | #define COUNT_3(x) (x) |
1779 | #define COUNT_3(x) (x) |
| 1778 | /* call count */ |
1780 | /* call count */ |
| 1779 | #define CALL_COUNT(x) (x) |
1781 | #define CALL_COUNT(x) (x) |
| 1780 | /* eop */ |
1782 | /* eop */ |
| 1781 | #define END_OF_PROGRAM(x) (x) |
1783 | #define END_OF_PROGRAM(x) (x) |
| 1782 | /* vpm */ |
1784 | /* vpm */ |
| 1783 | #define VALID_PIXEL_MODE(x) (x) |
1785 | #define VALID_PIXEL_MODE(x) (x) |
| 1784 | /* cf inst */ |
1786 | /* cf inst */ |
| 1785 | #define CF_INST(x) (x) /* SQ_CF_INST_* */ |
1787 | #define CF_INST(x) (x) /* SQ_CF_INST_* */ |
| 1786 | 1788 | ||
| 1787 | /* wqm */ |
1789 | /* wqm */ |
| 1788 | #define WHOLE_QUAD_MODE(x) (x) |
1790 | #define WHOLE_QUAD_MODE(x) (x) |
| 1789 | /* barrier */ |
1791 | /* barrier */ |
| 1790 | #define BARRIER(x) (x) |
1792 | #define BARRIER(x) (x) |
| 1791 | /*kb0 */ |
1793 | /*kb0 */ |
| 1792 | #define KCACHE_BANK0(x) (x) |
1794 | #define KCACHE_BANK0(x) (x) |
| 1793 | /*kb1 */ |
1795 | /*kb1 */ |
| 1794 | #define KCACHE_BANK1(x) (x) |
1796 | #define KCACHE_BANK1(x) (x) |
| 1795 | /* km0/1 */ |
1797 | /* km0/1 */ |
| 1796 | #define KCACHE_MODE0(x) (x) |
1798 | #define KCACHE_MODE0(x) (x) |
| 1797 | #define KCACHE_MODE1(x) (x) /* SQ_CF_KCACHE_* */ |
1799 | #define KCACHE_MODE1(x) (x) /* SQ_CF_KCACHE_* */ |
| 1798 | /* */ |
1800 | /* */ |
| 1799 | #define KCACHE_ADDR0(x) (x) |
1801 | #define KCACHE_ADDR0(x) (x) |
| 1800 | #define KCACHE_ADDR1(x) (x) |
1802 | #define KCACHE_ADDR1(x) (x) |
| 1801 | /* uw */ |
1803 | /* uw */ |
| 1802 | #define USES_WATERFALL(x) (x) |
1804 | #define USES_WATERFALL(x) (x) |
| 1803 | 1805 | ||
| 1804 | #define ARRAY_BASE(x) (x) |
1806 | #define ARRAY_BASE(x) (x) |
| 1805 | /* export pixel */ |
1807 | /* export pixel */ |
| 1806 | #define CF_PIXEL_MRT0 0 |
1808 | #define CF_PIXEL_MRT0 0 |
| 1807 | #define CF_PIXEL_MRT1 1 |
1809 | #define CF_PIXEL_MRT1 1 |
| 1808 | #define CF_PIXEL_MRT2 2 |
1810 | #define CF_PIXEL_MRT2 2 |
| 1809 | #define CF_PIXEL_MRT3 3 |
1811 | #define CF_PIXEL_MRT3 3 |
| 1810 | #define CF_PIXEL_MRT4 4 |
1812 | #define CF_PIXEL_MRT4 4 |
| 1811 | #define CF_PIXEL_MRT5 5 |
1813 | #define CF_PIXEL_MRT5 5 |
| 1812 | #define CF_PIXEL_MRT6 6 |
1814 | #define CF_PIXEL_MRT6 6 |
| 1813 | #define CF_PIXEL_MRT7 7 |
1815 | #define CF_PIXEL_MRT7 7 |
| 1814 | /* *_FOG: r6xx only */ |
1816 | /* *_FOG: r6xx only */ |
| 1815 | #define CF_PIXEL_MRT0_FOG 16 |
1817 | #define CF_PIXEL_MRT0_FOG 16 |
| 1816 | #define CF_PIXEL_MRT1_FOG 17 |
1818 | #define CF_PIXEL_MRT1_FOG 17 |
| 1817 | #define CF_PIXEL_MRT2_FOG 18 |
1819 | #define CF_PIXEL_MRT2_FOG 18 |
| 1818 | #define CF_PIXEL_MRT3_FOG 19 |
1820 | #define CF_PIXEL_MRT3_FOG 19 |
| 1819 | #define CF_PIXEL_MRT4_FOG 20 |
1821 | #define CF_PIXEL_MRT4_FOG 20 |
| 1820 | #define CF_PIXEL_MRT5_FOG 21 |
1822 | #define CF_PIXEL_MRT5_FOG 21 |
| 1821 | #define CF_PIXEL_MRT6_FOG 22 |
1823 | #define CF_PIXEL_MRT6_FOG 22 |
| 1822 | #define CF_PIXEL_MRT7_FOG 23 |
1824 | #define CF_PIXEL_MRT7_FOG 23 |
| 1823 | #define CF_PIXEL_Z 61 |
1825 | #define CF_PIXEL_Z 61 |
| 1824 | /* export pos */ |
1826 | /* export pos */ |
| 1825 | #define CF_POS0 60 |
1827 | #define CF_POS0 60 |
| 1826 | #define CF_POS1 61 |
1828 | #define CF_POS1 61 |
| 1827 | #define CF_POS2 62 |
1829 | #define CF_POS2 62 |
| 1828 | #define CF_POS3 63 |
1830 | #define CF_POS3 63 |
| 1829 | /* export param */ |
1831 | /* export param */ |
| 1830 | /* 0...31 */ |
1832 | /* 0...31 */ |
| 1831 | #define TYPE(x) (x) /* SQ_EXPORT_* */ |
1833 | #define TYPE(x) (x) /* SQ_EXPORT_* */ |
| 1832 | #if 0 |
1834 | #if 0 |
| 1833 | /* type export */ |
1835 | /* type export */ |
| 1834 | #define SQ_EXPORT_PIXEL 0 |
1836 | #define SQ_EXPORT_PIXEL 0 |
| 1835 | #define SQ_EXPORT_POS 1 |
1837 | #define SQ_EXPORT_POS 1 |
| 1836 | #define SQ_EXPORT_PARAM 2 |
1838 | #define SQ_EXPORT_PARAM 2 |
| 1837 | /* reserved 3 */ |
1839 | /* reserved 3 */ |
| 1838 | /* type mem */ |
1840 | /* type mem */ |
| 1839 | #define SQ_EXPORT_WRITE 0 |
1841 | #define SQ_EXPORT_WRITE 0 |
| 1840 | #define SQ_EXPORT_WRITE_IND 1 |
1842 | #define SQ_EXPORT_WRITE_IND 1 |
| 1841 | #define SQ_EXPORT_WRITE_ACK 2 |
1843 | #define SQ_EXPORT_WRITE_ACK 2 |
| 1842 | #define SQ_EXPORT_WRITE_IND_ACK 3 |
1844 | #define SQ_EXPORT_WRITE_IND_ACK 3 |
| 1843 | #endif |
1845 | #endif |
| 1844 | 1846 | ||
| 1845 | #define RW_GPR(x) (x) |
1847 | #define RW_GPR(x) (x) |
| 1846 | #define RW_REL(x) (x) |
1848 | #define RW_REL(x) (x) |
| 1847 | #define ABSOLUTE 0 |
1849 | #define ABSOLUTE 0 |
| 1848 | #define RELATIVE 1 |
1850 | #define RELATIVE 1 |
| 1849 | #define INDEX_GPR(x) (x) |
1851 | #define INDEX_GPR(x) (x) |
| 1850 | #define ELEM_SIZE(x) (x ? (x - 1) : 0) |
1852 | #define ELEM_SIZE(x) (x ? (x - 1) : 0) |
| 1851 | #define COMP_MASK(x) (x) |
1853 | #define COMP_MASK(x) (x) |
| 1852 | #define R6xx_ELEM_LOOP(x) (x) |
1854 | #define R6xx_ELEM_LOOP(x) (x) |
| 1853 | #define BURST_COUNT(x) (x ? (x - 1) : 0) |
1855 | #define BURST_COUNT(x) (x ? (x - 1) : 0) |
| 1854 | 1856 | ||
| 1855 | /* swiz */ |
1857 | /* swiz */ |
| 1856 | #define SRC_SEL_X(x) (x) /* SQ_SEL_* each */ |
1858 | #define SRC_SEL_X(x) (x) /* SQ_SEL_* each */ |
| 1857 | #define SRC_SEL_Y(x) (x) |
1859 | #define SRC_SEL_Y(x) (x) |
| 1858 | #define SRC_SEL_Z(x) (x) |
1860 | #define SRC_SEL_Z(x) (x) |
| 1859 | #define SRC_SEL_W(x) (x) |
1861 | #define SRC_SEL_W(x) (x) |
| 1860 | 1862 | ||
| 1861 | #define CF_DWORD0(addr) (addr) |
1863 | #define CF_DWORD0(addr) (addr) |
| 1862 | /* R7xx has another entry (COUNT3), but that is only used for adding a bit to count. */ |
1864 | /* R7xx has another entry (COUNT3), but that is only used for adding a bit to count. */ |
| 1863 | /* We allow one more bit for count in the argument of the macro on R7xx instead. */ |
1865 | /* We allow one more bit for count in the argument of the macro on R7xx instead. */ |
| 1864 | /* R6xx: [0,7] R7xx: [1,16] */ |
1866 | /* R6xx: [0,7] R7xx: [1,16] */ |
| 1865 | #define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \ |
1867 | #define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \ |
| 1866 | (((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | (((count) & 7) << 10) | (((count) >> 3) << 19) | \ |
1868 | (((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | (((count) & 7) << 10) | (((count) >> 3) << 19) | \ |
| 1867 | ((call_count) << 13) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)) |
1869 | ((call_count) << 13) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)) |
| 1868 | 1870 | ||
| 1869 | #define CF_ALU_DWORD0(addr, kb0, kb1, km0) (((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30)) |
1871 | #define CF_ALU_DWORD0(addr, kb0, kb1, km0) (((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30)) |
| 1870 | #define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \ |
1872 | #define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \ |
| 1871 | (((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \ |
1873 | (((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \ |
| 1872 | ((count) << 18) | ((uw) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31)) |
1874 | ((count) << 18) | ((uw) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31)) |
| 1873 | 1875 | ||
| 1874 | #define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \ |
1876 | #define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \ |
| 1875 | (((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \ |
1877 | (((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \ |
| 1876 | ((es) << 30)) |
1878 | ((es) << 30)) |
| 1877 | /* R7xx apparently doesn't have the ELEM_LOOP entry any more */ |
1879 | /* R7xx apparently doesn't have the ELEM_LOOP entry any more */ |
| 1878 | /* We still expose it, but ELEM_LOOP is explicitely R6xx now. */ |
1880 | /* We still expose it, but ELEM_LOOP is explicitely R6xx now. */ |
| 1879 | /* TODO: is this just forgotten in the docs, or really not available any more? */ |
1881 | /* TODO: is this just forgotten in the docs, or really not available any more? */ |
| 1880 | #define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \ |
1882 | #define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \ |
| 1881 | (((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \ |
1883 | (((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \ |
| 1882 | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)) |
1884 | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)) |
| 1883 | #define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \ |
1885 | #define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \ |
| 1884 | (((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | ((el) << 16) | \ |
1886 | (((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | ((el) << 16) | \ |
| 1885 | ((bc) << 17) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | \ |
1887 | ((bc) << 17) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | \ |
| 1886 | ((wqm) << 30) | ((b) << 31)) |
1888 | ((wqm) << 30) | ((b) << 31)) |
| 1887 | 1889 | ||
| 1888 | /* VTX clause insts */ |
1890 | /* VTX clause insts */ |
| 1889 | /* vxt insts */ |
1891 | /* vxt insts */ |
| 1890 | #define VTX_INST(x) (x) /* SQ_VTX_INST_* */ |
1892 | #define VTX_INST(x) (x) /* SQ_VTX_INST_* */ |
| 1891 | 1893 | ||
| 1892 | /* fetch type */ |
1894 | /* fetch type */ |
| 1893 | #define FETCH_TYPE(x) (x) /* SQ_VTX_FETCH_* */ |
1895 | #define FETCH_TYPE(x) (x) /* SQ_VTX_FETCH_* */ |
| 1894 | 1896 | ||
| 1895 | #define FETCH_WHOLE_QUAD(x) (x) |
1897 | #define FETCH_WHOLE_QUAD(x) (x) |
| 1896 | #define BUFFER_ID(x) (x) |
1898 | #define BUFFER_ID(x) (x) |
| 1897 | #define SRC_GPR(x) (x) |
1899 | #define SRC_GPR(x) (x) |
| 1898 | #define SRC_REL(x) (x) |
1900 | #define SRC_REL(x) (x) |
| 1899 | #define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0) |
1901 | #define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0) |
| 1900 | 1902 | ||
| 1901 | #define SEMANTIC_ID(x) (x) |
1903 | #define SEMANTIC_ID(x) (x) |
| 1902 | #define DST_SEL_X(x) (x) |
1904 | #define DST_SEL_X(x) (x) |
| 1903 | #define DST_SEL_Y(x) (x) |
1905 | #define DST_SEL_Y(x) (x) |
| 1904 | #define DST_SEL_Z(x) (x) |
1906 | #define DST_SEL_Z(x) (x) |
| 1905 | #define DST_SEL_W(x) (x) |
1907 | #define DST_SEL_W(x) (x) |
| 1906 | #define USE_CONST_FIELDS(x) (x) |
1908 | #define USE_CONST_FIELDS(x) (x) |
| 1907 | #define DATA_FORMAT(x) (x) |
1909 | #define DATA_FORMAT(x) (x) |
| 1908 | /* num format */ |
1910 | /* num format */ |
| 1909 | #define NUM_FORMAT_ALL(x) (x) /* SQ_NUM_FORMAT_* */ |
1911 | #define NUM_FORMAT_ALL(x) (x) /* SQ_NUM_FORMAT_* */ |
| 1910 | /* format comp */ |
1912 | /* format comp */ |
| 1911 | #define FORMAT_COMP_ALL(x) (x) /* SQ_FORMAT_COMP_* */ |
1913 | #define FORMAT_COMP_ALL(x) (x) /* SQ_FORMAT_COMP_* */ |
| 1912 | /* sma */ |
1914 | /* sma */ |
| 1913 | #define SRF_MODE_ALL(x) (x) |
1915 | #define SRF_MODE_ALL(x) (x) |
| 1914 | #define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0 |
1916 | #define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0 |
| 1915 | #define SRF_MODE_NO_ZERO 1 |
1917 | #define SRF_MODE_NO_ZERO 1 |
| 1916 | #define OFFSET(x) (x) |
1918 | #define OFFSET(x) (x) |
| 1917 | /* endian swap */ |
1919 | /* endian swap */ |
| 1918 | #define ENDIAN_SWAP(x) (x) /* SQ_ENDIAN_* */ |
1920 | #define ENDIAN_SWAP(x) (x) /* SQ_ENDIAN_* */ |
| 1919 | #define CONST_BUF_NO_STRIDE(x) (x) |
1921 | #define CONST_BUF_NO_STRIDE(x) (x) |
| 1920 | /* mf */ |
1922 | /* mf */ |
| 1921 | #define MEGA_FETCH(x) (x) |
1923 | #define MEGA_FETCH(x) (x) |
| 1922 | 1924 | ||
| 1923 | #define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \ |
1925 | #define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \ |
| 1924 | (((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \ |
1926 | (((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \ |
| 1925 | ((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26)) |
1927 | ((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26)) |
| 1926 | #define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ |
1928 | #define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ |
| 1927 | (((semantic_id) << 0) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
1929 | (((semantic_id) << 0) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
| 1928 | ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)) |
1930 | ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)) |
| 1929 | #define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ |
1931 | #define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ |
| 1930 | (((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
1932 | (((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
| 1931 | ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)) |
1933 | ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)) |
| 1932 | #define VTX_DWORD2(offset, es, cbns, mf) \ |
1934 | #define VTX_DWORD2(offset, es, cbns, mf) \ |
| 1933 | (((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19)) |
1935 | (((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19)) |
| 1934 | #define VTX_DWORD_PAD 0x00000000 |
1936 | #define VTX_DWORD_PAD 0x00000000 |
| 1935 | 1937 | ||
| 1936 | 1938 | ||
| 1937 | int R600_solid_vs(struct radeon_device *rdev, uint32_t* shader) |
1939 | int R600_solid_vs(struct radeon_device *rdev, uint32_t* shader) |
| 1938 | { |
1940 | { |
| 1939 | int i=0; |
1941 | int i=0; |
| 1940 | 1942 | ||
| 1941 | /* 0 */ |
1943 | /* 0 */ |
| 1942 | shader[i++] = CF_DWORD0(ADDR(4)); |
1944 | shader[i++] = CF_DWORD0(ADDR(4)); |
| 1943 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
1945 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
| 1944 | CF_CONST(0), |
1946 | CF_CONST(0), |
| 1945 | COND(SQ_CF_COND_ACTIVE), |
1947 | COND(SQ_CF_COND_ACTIVE), |
| 1946 | I_COUNT(1), |
1948 | I_COUNT(1), |
| 1947 | CALL_COUNT(0), |
1949 | CALL_COUNT(0), |
| 1948 | END_OF_PROGRAM(0), |
1950 | END_OF_PROGRAM(0), |
| 1949 | VALID_PIXEL_MODE(0), |
1951 | VALID_PIXEL_MODE(0), |
| 1950 | CF_INST(SQ_CF_INST_VTX), |
1952 | CF_INST(SQ_CF_INST_VTX), |
| 1951 | WHOLE_QUAD_MODE(0), |
1953 | WHOLE_QUAD_MODE(0), |
| 1952 | BARRIER(1)); |
1954 | BARRIER(1)); |
| 1953 | /* 1 */ |
1955 | /* 1 */ |
| 1954 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), |
1956 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), |
| 1955 | TYPE(SQ_EXPORT_POS), |
1957 | TYPE(SQ_EXPORT_POS), |
| 1956 | RW_GPR(1), |
1958 | RW_GPR(1), |
| 1957 | RW_REL(ABSOLUTE), |
1959 | RW_REL(ABSOLUTE), |
| 1958 | INDEX_GPR(0), |
1960 | INDEX_GPR(0), |
| 1959 | ELEM_SIZE(0)); |
1961 | ELEM_SIZE(0)); |
| 1960 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
1962 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
| 1961 | SRC_SEL_Y(SQ_SEL_Y), |
1963 | SRC_SEL_Y(SQ_SEL_Y), |
| 1962 | SRC_SEL_Z(SQ_SEL_Z), |
1964 | SRC_SEL_Z(SQ_SEL_Z), |
| 1963 | SRC_SEL_W(SQ_SEL_W), |
1965 | SRC_SEL_W(SQ_SEL_W), |
| 1964 | R6xx_ELEM_LOOP(0), |
1966 | R6xx_ELEM_LOOP(0), |
| 1965 | BURST_COUNT(1), |
1967 | BURST_COUNT(1), |
| 1966 | END_OF_PROGRAM(0), |
1968 | END_OF_PROGRAM(0), |
| 1967 | VALID_PIXEL_MODE(0), |
1969 | VALID_PIXEL_MODE(0), |
| 1968 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
1970 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
| 1969 | WHOLE_QUAD_MODE(0), |
1971 | WHOLE_QUAD_MODE(0), |
| 1970 | BARRIER(1)); |
1972 | BARRIER(1)); |
| 1971 | /* 2 - always export a param whether it's used or not */ |
1973 | /* 2 - always export a param whether it's used or not */ |
| 1972 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), |
1974 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), |
| 1973 | TYPE(SQ_EXPORT_PARAM), |
1975 | TYPE(SQ_EXPORT_PARAM), |
| 1974 | RW_GPR(0), |
1976 | RW_GPR(0), |
| 1975 | RW_REL(ABSOLUTE), |
1977 | RW_REL(ABSOLUTE), |
| 1976 | INDEX_GPR(0), |
1978 | INDEX_GPR(0), |
| 1977 | ELEM_SIZE(0)); |
1979 | ELEM_SIZE(0)); |
| 1978 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
1980 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
| 1979 | SRC_SEL_Y(SQ_SEL_Y), |
1981 | SRC_SEL_Y(SQ_SEL_Y), |
| 1980 | SRC_SEL_Z(SQ_SEL_Z), |
1982 | SRC_SEL_Z(SQ_SEL_Z), |
| 1981 | SRC_SEL_W(SQ_SEL_W), |
1983 | SRC_SEL_W(SQ_SEL_W), |
| 1982 | R6xx_ELEM_LOOP(0), |
1984 | R6xx_ELEM_LOOP(0), |
| 1983 | BURST_COUNT(0), |
1985 | BURST_COUNT(0), |
| 1984 | END_OF_PROGRAM(1), |
1986 | END_OF_PROGRAM(1), |
| 1985 | VALID_PIXEL_MODE(0), |
1987 | VALID_PIXEL_MODE(0), |
| 1986 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
1988 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
| 1987 | WHOLE_QUAD_MODE(0), |
1989 | WHOLE_QUAD_MODE(0), |
| 1988 | BARRIER(0)); |
1990 | BARRIER(0)); |
| 1989 | /* 3 - padding */ |
1991 | /* 3 - padding */ |
| 1990 | shader[i++] = 0x00000000; |
1992 | shader[i++] = 0x00000000; |
| 1991 | shader[i++] = 0x00000000; |
1993 | shader[i++] = 0x00000000; |
| 1992 | /* 4/5 */ |
1994 | /* 4/5 */ |
| 1993 | shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), |
1995 | shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), |
| 1994 | FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), |
1996 | FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), |
| 1995 | FETCH_WHOLE_QUAD(0), |
1997 | FETCH_WHOLE_QUAD(0), |
| 1996 | BUFFER_ID(0), |
1998 | BUFFER_ID(0), |
| 1997 | SRC_GPR(0), |
1999 | SRC_GPR(0), |
| 1998 | SRC_REL(ABSOLUTE), |
2000 | SRC_REL(ABSOLUTE), |
| 1999 | SRC_SEL_X(SQ_SEL_X), |
2001 | SRC_SEL_X(SQ_SEL_X), |
| 2000 | MEGA_FETCH_COUNT(8)); |
2002 | MEGA_FETCH_COUNT(8)); |
| 2001 | shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), |
2003 | shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), |
| 2002 | DST_REL(0), |
2004 | DST_REL(0), |
| 2003 | DST_SEL_X(SQ_SEL_X), |
2005 | DST_SEL_X(SQ_SEL_X), |
| 2004 | DST_SEL_Y(SQ_SEL_Y), |
2006 | DST_SEL_Y(SQ_SEL_Y), |
| 2005 | DST_SEL_Z(SQ_SEL_0), |
2007 | DST_SEL_Z(SQ_SEL_0), |
| 2006 | DST_SEL_W(SQ_SEL_1), |
2008 | DST_SEL_W(SQ_SEL_1), |
| 2007 | USE_CONST_FIELDS(0), |
2009 | USE_CONST_FIELDS(0), |
| 2008 | DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ |
2010 | DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ |
| 2009 | NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ |
2011 | NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ |
| 2010 | FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ |
2012 | FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ |
| 2011 | SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); |
2013 | SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); |
| 2012 | shader[i++] = VTX_DWORD2(OFFSET(0), |
2014 | shader[i++] = VTX_DWORD2(OFFSET(0), |
| 2013 | ENDIAN_SWAP(ENDIAN_NONE), |
2015 | ENDIAN_SWAP(ENDIAN_NONE), |
| 2014 | CONST_BUF_NO_STRIDE(0), |
2016 | CONST_BUF_NO_STRIDE(0), |
| 2015 | MEGA_FETCH(1)); |
2017 | MEGA_FETCH(1)); |
| 2016 | shader[i++] = VTX_DWORD_PAD; |
2018 | shader[i++] = VTX_DWORD_PAD; |
| 2017 | 2019 | ||
| 2018 | return i; |
2020 | return i; |
| 2019 | } |
2021 | } |
| 2020 | 2022 | ||
| 2021 | int R600_solid_ps(struct radeon_device *rdev, uint32_t* shader) |
2023 | int R600_solid_ps(struct radeon_device *rdev, uint32_t* shader) |
| 2022 | { |
2024 | { |
| 2023 | int i=0; |
2025 | int i=0; |
| 2024 | 2026 | ||
| 2025 | /* 0 */ |
2027 | /* 0 */ |
| 2026 | shader[i++] = CF_ALU_DWORD0(ADDR(2), |
2028 | shader[i++] = CF_ALU_DWORD0(ADDR(2), |
| 2027 | KCACHE_BANK0(0), |
2029 | KCACHE_BANK0(0), |
| 2028 | KCACHE_BANK1(0), |
2030 | KCACHE_BANK1(0), |
| 2029 | KCACHE_MODE0(SQ_CF_KCACHE_NOP)); |
2031 | KCACHE_MODE0(SQ_CF_KCACHE_NOP)); |
| 2030 | shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), |
2032 | shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), |
| 2031 | KCACHE_ADDR0(0), |
2033 | KCACHE_ADDR0(0), |
| 2032 | KCACHE_ADDR1(0), |
2034 | KCACHE_ADDR1(0), |
| 2033 | I_COUNT(4), |
2035 | I_COUNT(4), |
| 2034 | USES_WATERFALL(0), |
2036 | USES_WATERFALL(0), |
| 2035 | CF_INST(SQ_CF_INST_ALU), |
2037 | CF_INST(SQ_CF_INST_ALU), |
| 2036 | WHOLE_QUAD_MODE(0), |
2038 | WHOLE_QUAD_MODE(0), |
| 2037 | BARRIER(1)); |
2039 | BARRIER(1)); |
| 2038 | /* 1 */ |
2040 | /* 1 */ |
| 2039 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), |
2041 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), |
| 2040 | TYPE(SQ_EXPORT_PIXEL), |
2042 | TYPE(SQ_EXPORT_PIXEL), |
| 2041 | RW_GPR(0), |
2043 | RW_GPR(0), |
| 2042 | RW_REL(ABSOLUTE), |
2044 | RW_REL(ABSOLUTE), |
| 2043 | INDEX_GPR(0), |
2045 | INDEX_GPR(0), |
| 2044 | ELEM_SIZE(1)); |
2046 | ELEM_SIZE(1)); |
| 2045 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
2047 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
| 2046 | SRC_SEL_Y(SQ_SEL_Y), |
2048 | SRC_SEL_Y(SQ_SEL_Y), |
| 2047 | SRC_SEL_Z(SQ_SEL_Z), |
2049 | SRC_SEL_Z(SQ_SEL_Z), |
| 2048 | SRC_SEL_W(SQ_SEL_W), |
2050 | SRC_SEL_W(SQ_SEL_W), |
| 2049 | R6xx_ELEM_LOOP(0), |
2051 | R6xx_ELEM_LOOP(0), |
| 2050 | BURST_COUNT(1), |
2052 | BURST_COUNT(1), |
| 2051 | END_OF_PROGRAM(1), |
2053 | END_OF_PROGRAM(1), |
| 2052 | VALID_PIXEL_MODE(0), |
2054 | VALID_PIXEL_MODE(0), |
| 2053 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
2055 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
| 2054 | WHOLE_QUAD_MODE(0), |
2056 | WHOLE_QUAD_MODE(0), |
| 2055 | BARRIER(1)); |
2057 | BARRIER(1)); |
| 2056 | 2058 | ||
| 2057 | /* 2 */ |
2059 | /* 2 */ |
| 2058 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
2060 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
| 2059 | SRC0_REL(ABSOLUTE), |
2061 | SRC0_REL(ABSOLUTE), |
| 2060 | SRC0_ELEM(ELEM_X), |
2062 | SRC0_ELEM(ELEM_X), |
| 2061 | SRC0_NEG(0), |
2063 | SRC0_NEG(0), |
| 2062 | SRC1_SEL(0), |
2064 | SRC1_SEL(0), |
| 2063 | SRC1_REL(ABSOLUTE), |
2065 | SRC1_REL(ABSOLUTE), |
| 2064 | SRC1_ELEM(ELEM_X), |
2066 | SRC1_ELEM(ELEM_X), |
| 2065 | SRC1_NEG(0), |
2067 | SRC1_NEG(0), |
| 2066 | INDEX_MODE(SQ_INDEX_AR_X), |
2068 | INDEX_MODE(SQ_INDEX_AR_X), |
| 2067 | PRED_SEL(SQ_PRED_SEL_OFF), |
2069 | PRED_SEL(SQ_PRED_SEL_OFF), |
| 2068 | LAST(0)); |
2070 | LAST(0)); |
| 2069 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
2071 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
| 2070 | SRC0_ABS(0), |
2072 | SRC0_ABS(0), |
| 2071 | SRC1_ABS(0), |
2073 | SRC1_ABS(0), |
| 2072 | UPDATE_EXECUTE_MASK(0), |
2074 | UPDATE_EXECUTE_MASK(0), |
| 2073 | UPDATE_PRED(0), |
2075 | UPDATE_PRED(0), |
| 2074 | WRITE_MASK(1), |
2076 | WRITE_MASK(1), |
| 2075 | FOG_MERGE(0), |
2077 | FOG_MERGE(0), |
| 2076 | OMOD(SQ_ALU_OMOD_OFF), |
2078 | OMOD(SQ_ALU_OMOD_OFF), |
| 2077 | ALU_INST(SQ_OP2_INST_MOV), |
2079 | ALU_INST(SQ_OP2_INST_MOV), |
| 2078 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
2080 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
| 2079 | DST_GPR(0), |
2081 | DST_GPR(0), |
| 2080 | DST_REL(ABSOLUTE), |
2082 | DST_REL(ABSOLUTE), |
| 2081 | DST_ELEM(ELEM_X), |
2083 | DST_ELEM(ELEM_X), |
| 2082 | CLAMP(1)); |
2084 | CLAMP(1)); |
| 2083 | /* 3 */ |
2085 | /* 3 */ |
| 2084 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
2086 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
| 2085 | SRC0_REL(ABSOLUTE), |
2087 | SRC0_REL(ABSOLUTE), |
| 2086 | SRC0_ELEM(ELEM_Y), |
2088 | SRC0_ELEM(ELEM_Y), |
| 2087 | SRC0_NEG(0), |
2089 | SRC0_NEG(0), |
| 2088 | SRC1_SEL(0), |
2090 | SRC1_SEL(0), |
| 2089 | SRC1_REL(ABSOLUTE), |
2091 | SRC1_REL(ABSOLUTE), |
| 2090 | SRC1_ELEM(ELEM_Y), |
2092 | SRC1_ELEM(ELEM_Y), |
| 2091 | SRC1_NEG(0), |
2093 | SRC1_NEG(0), |
| 2092 | INDEX_MODE(SQ_INDEX_AR_X), |
2094 | INDEX_MODE(SQ_INDEX_AR_X), |
| 2093 | PRED_SEL(SQ_PRED_SEL_OFF), |
2095 | PRED_SEL(SQ_PRED_SEL_OFF), |
| 2094 | LAST(0)); |
2096 | LAST(0)); |
| 2095 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
2097 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
| 2096 | SRC0_ABS(0), |
2098 | SRC0_ABS(0), |
| 2097 | SRC1_ABS(0), |
2099 | SRC1_ABS(0), |
| 2098 | UPDATE_EXECUTE_MASK(0), |
2100 | UPDATE_EXECUTE_MASK(0), |
| 2099 | UPDATE_PRED(0), |
2101 | UPDATE_PRED(0), |
| 2100 | WRITE_MASK(1), |
2102 | WRITE_MASK(1), |
| 2101 | FOG_MERGE(0), |
2103 | FOG_MERGE(0), |
| 2102 | OMOD(SQ_ALU_OMOD_OFF), |
2104 | OMOD(SQ_ALU_OMOD_OFF), |
| 2103 | ALU_INST(SQ_OP2_INST_MOV), |
2105 | ALU_INST(SQ_OP2_INST_MOV), |
| 2104 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
2106 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
| 2105 | DST_GPR(0), |
2107 | DST_GPR(0), |
| 2106 | DST_REL(ABSOLUTE), |
2108 | DST_REL(ABSOLUTE), |
| 2107 | DST_ELEM(ELEM_Y), |
2109 | DST_ELEM(ELEM_Y), |
| 2108 | CLAMP(1)); |
2110 | CLAMP(1)); |
| 2109 | /* 4 */ |
2111 | /* 4 */ |
| 2110 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
2112 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
| 2111 | SRC0_REL(ABSOLUTE), |
2113 | SRC0_REL(ABSOLUTE), |
| 2112 | SRC0_ELEM(ELEM_Z), |
2114 | SRC0_ELEM(ELEM_Z), |
| 2113 | SRC0_NEG(0), |
2115 | SRC0_NEG(0), |
| 2114 | SRC1_SEL(0), |
2116 | SRC1_SEL(0), |
| 2115 | SRC1_REL(ABSOLUTE), |
2117 | SRC1_REL(ABSOLUTE), |
| 2116 | SRC1_ELEM(ELEM_Z), |
2118 | SRC1_ELEM(ELEM_Z), |
| 2117 | SRC1_NEG(0), |
2119 | SRC1_NEG(0), |
| 2118 | INDEX_MODE(SQ_INDEX_AR_X), |
2120 | INDEX_MODE(SQ_INDEX_AR_X), |
| 2119 | PRED_SEL(SQ_PRED_SEL_OFF), |
2121 | PRED_SEL(SQ_PRED_SEL_OFF), |
| 2120 | LAST(0)); |
2122 | LAST(0)); |
| 2121 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
2123 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
| 2122 | SRC0_ABS(0), |
2124 | SRC0_ABS(0), |
| 2123 | SRC1_ABS(0), |
2125 | SRC1_ABS(0), |
| 2124 | UPDATE_EXECUTE_MASK(0), |
2126 | UPDATE_EXECUTE_MASK(0), |
| 2125 | UPDATE_PRED(0), |
2127 | UPDATE_PRED(0), |
| 2126 | WRITE_MASK(1), |
2128 | WRITE_MASK(1), |
| 2127 | FOG_MERGE(0), |
2129 | FOG_MERGE(0), |
| 2128 | OMOD(SQ_ALU_OMOD_OFF), |
2130 | OMOD(SQ_ALU_OMOD_OFF), |
| 2129 | ALU_INST(SQ_OP2_INST_MOV), |
2131 | ALU_INST(SQ_OP2_INST_MOV), |
| 2130 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
2132 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
| 2131 | DST_GPR(0), |
2133 | DST_GPR(0), |
| 2132 | DST_REL(ABSOLUTE), |
2134 | DST_REL(ABSOLUTE), |
| 2133 | DST_ELEM(ELEM_Z), |
2135 | DST_ELEM(ELEM_Z), |
| 2134 | CLAMP(1)); |
2136 | CLAMP(1)); |
| 2135 | /* 5 */ |
2137 | /* 5 */ |
| 2136 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
2138 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
| 2137 | SRC0_REL(ABSOLUTE), |
2139 | SRC0_REL(ABSOLUTE), |
| 2138 | SRC0_ELEM(ELEM_W), |
2140 | SRC0_ELEM(ELEM_W), |
| 2139 | SRC0_NEG(0), |
2141 | SRC0_NEG(0), |
| 2140 | SRC1_SEL(0), |
2142 | SRC1_SEL(0), |
| 2141 | SRC1_REL(ABSOLUTE), |
2143 | SRC1_REL(ABSOLUTE), |
| 2142 | SRC1_ELEM(ELEM_W), |
2144 | SRC1_ELEM(ELEM_W), |
| 2143 | SRC1_NEG(0), |
2145 | SRC1_NEG(0), |
| 2144 | INDEX_MODE(SQ_INDEX_AR_X), |
2146 | INDEX_MODE(SQ_INDEX_AR_X), |
| 2145 | PRED_SEL(SQ_PRED_SEL_OFF), |
2147 | PRED_SEL(SQ_PRED_SEL_OFF), |
| 2146 | LAST(1)); |
2148 | LAST(1)); |
| 2147 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
2149 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
| 2148 | SRC0_ABS(0), |
2150 | SRC0_ABS(0), |
| 2149 | SRC1_ABS(0), |
2151 | SRC1_ABS(0), |
| 2150 | UPDATE_EXECUTE_MASK(0), |
2152 | UPDATE_EXECUTE_MASK(0), |
| 2151 | UPDATE_PRED(0), |
2153 | UPDATE_PRED(0), |
| 2152 | WRITE_MASK(1), |
2154 | WRITE_MASK(1), |
| 2153 | FOG_MERGE(0), |
2155 | FOG_MERGE(0), |
| 2154 | OMOD(SQ_ALU_OMOD_OFF), |
2156 | OMOD(SQ_ALU_OMOD_OFF), |
| 2155 | ALU_INST(SQ_OP2_INST_MOV), |
2157 | ALU_INST(SQ_OP2_INST_MOV), |
| 2156 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
2158 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
| 2157 | DST_GPR(0), |
2159 | DST_GPR(0), |
| 2158 | DST_REL(ABSOLUTE), |
2160 | DST_REL(ABSOLUTE), |
| 2159 | DST_ELEM(ELEM_W), |
2161 | DST_ELEM(ELEM_W), |
| 2160 | CLAMP(1)); |
2162 | CLAMP(1)); |
| 2161 | 2163 | ||
| 2162 | return i; |
2164 | return i; |
| 2163 | } |
2165 | } |
| 2164 | 2166 | ||
| 2165 | static inline void |
2167 | static inline void |
| 2166 | memcpy_toio(volatile void __iomem *dst, const void *src, int count) |
2168 | memcpy_toio(volatile void __iomem *dst, const void *src, int count) |
| 2167 | { |
2169 | { |
| 2168 | __memcpy((void __force *)dst, src, count); |
2170 | __memcpy((void __force *)dst, src, count); |
| 2169 | } |
2171 | } |
| 2170 | 2172 | ||
| 2171 | #define EFLOAT(val) \ |
2173 | #define EFLOAT(val) \ |
| 2172 | do { \ |
2174 | do { \ |
| 2173 | union { float f; uint32_t d; } a; \ |
2175 | union { float f; uint32_t d; } a; \ |
| 2174 | a.f = (val); \ |
2176 | a.f = (val); \ |
| 2175 | radeon_ring_write(rdev, a.d); \ |
2177 | radeon_ring_write(rdev, a.d); \ |
| 2176 | } while (0) |
2178 | } while (0) |
| 2177 | 2179 | ||
| 2178 | int r600_2D_test(struct radeon_device *rdev) |
2180 | int r600_2D_test(struct radeon_device *rdev) |
| 2179 | { |
2181 | { |
| 2180 | uint32_t ps_shader[16]; |
2182 | uint32_t ps_shader[16]; |
| 2181 | uint32_t vs_shader[16]; |
2183 | uint32_t vs_shader[16]; |
| 2182 | 2184 | ||
| 2183 | u32 packet2s[16]; |
2185 | u32 packet2s[16]; |
| 2184 | int num_packet2s = 0; |
2186 | int num_packet2s = 0; |
| 2185 | 2187 | ||
| 2186 | uint32_t pitch; |
2188 | uint32_t pitch; |
| 2187 | uint32_t offset; |
2189 | uint32_t offset; |
| 2188 | 2190 | ||
| 2189 | int state_len; |
2191 | int state_len; |
| 2190 | int dwords; |
2192 | int dwords; |
| 2191 | u32 obj_size; |
2193 | u32 obj_size; |
| 2192 | 2194 | ||
| 2193 | u32 state_offset = 0; |
2195 | u32 state_offset = 0; |
| 2194 | u64 state_gpu_addr = 0; |
2196 | u64 state_gpu_addr = 0; |
| 2195 | 2197 | ||
| 2196 | u32 vs_offset; |
2198 | u32 vs_offset; |
| 2197 | u32 ps_offset; |
2199 | u32 ps_offset; |
| 2198 | u32 vb_offset; |
2200 | u32 vb_offset; |
| 2199 | 2201 | ||
| 2200 | int vs_size; |
2202 | int vs_size; |
| 2201 | int ps_size; |
2203 | int ps_size; |
| 2202 | 2204 | ||
| 2203 | float *vb; |
2205 | float *vb; |
| 2204 | void *ptr; |
2206 | void *ptr; |
| 2205 | 2207 | ||
| 2206 | struct radeon_bo *state_obj; |
2208 | struct radeon_bo *state_obj; |
| 2207 | 2209 | ||
| 2208 | int r; |
2210 | int r; |
| 2209 | 2211 | ||
| 2210 | ENTER(); |
2212 | ENTER(); |
| 2211 | 2213 | ||
| 2212 | pitch = (1024*4)/64; |
2214 | pitch = (1024*4)/64; |
| 2213 | offset = rdev->mc.vram_start; |
2215 | offset = rdev->mc.vram_start; |
| 2214 | ps_size = R600_solid_ps(rdev, ps_shader); |
2216 | ps_size = R600_solid_ps(rdev, ps_shader); |
| 2215 | vs_size = R600_solid_vs(rdev, vs_shader); |
2217 | vs_size = R600_solid_vs(rdev, vs_shader); |
| 2216 | 2218 | ||
| 2217 | if (rdev->family >= CHIP_RV770) |
2219 | if (rdev->family >= CHIP_RV770) |
| 2218 | state_len = r7xx_default_size; |
2220 | state_len = r7xx_default_size; |
| 2219 | else |
2221 | else |
| 2220 | state_len = r6xx_default_size; |
2222 | state_len = r6xx_default_size; |
| 2221 | 2223 | ||
| 2222 | dwords = state_len; |
2224 | dwords = state_len; |
| 2223 | 2225 | ||
| 2224 | while (dwords & 0xf) { |
2226 | while (dwords & 0xf) { |
| 2225 | packet2s[num_packet2s++] = PACKET2(0); |
2227 | packet2s[num_packet2s++] = PACKET2(0); |
| 2226 | dwords++; |
2228 | dwords++; |
| 2227 | } |
2229 | } |
| 2228 | 2230 | ||
| 2229 | obj_size = dwords * 4; |
2231 | obj_size = dwords * 4; |
| 2230 | obj_size = ALIGN(obj_size, 256); |
2232 | obj_size = ALIGN(obj_size, 256); |
| 2231 | 2233 | ||
| 2232 | vs_offset = obj_size; |
2234 | vs_offset = obj_size; |
| 2233 | obj_size += vs_size * 4; |
2235 | obj_size += vs_size * 4; |
| 2234 | obj_size = ALIGN(obj_size, 256); |
2236 | obj_size = ALIGN(obj_size, 256); |
| 2235 | 2237 | ||
| 2236 | ps_offset = obj_size; |
2238 | ps_offset = obj_size; |
| 2237 | obj_size += ps_size * 4; |
2239 | obj_size += ps_size * 4; |
| 2238 | obj_size = ALIGN(obj_size, 256); |
2240 | obj_size = ALIGN(obj_size, 256); |
| 2239 | 2241 | ||
| 2240 | vb_offset = obj_size; |
2242 | vb_offset = obj_size; |
| 2241 | obj_size += 32*4; |
2243 | obj_size += 32*4; |
| 2242 | obj_size = ALIGN(obj_size, 256); |
2244 | obj_size = ALIGN(obj_size, 256); |
| 2243 | 2245 | ||
| 2244 | r = radeon_bo_create(rdev, NULL, obj_size, true, RADEON_GEM_DOMAIN_VRAM, |
2246 | r = radeon_bo_create(rdev, NULL, obj_size, true, RADEON_GEM_DOMAIN_VRAM, |
| 2245 | &state_obj); |
2247 | &state_obj); |
| 2246 | if (r) { |
2248 | if (r) { |
| 2247 | DRM_ERROR("r600 failed to allocate state buffer\n"); |
2249 | DRM_ERROR("r600 failed to allocate state buffer\n"); |
| 2248 | return r; |
2250 | return r; |
| 2249 | } |
2251 | } |
| 2250 | 2252 | ||
| 2251 | DRM_DEBUG("r6xx state allocated bo %08x vs %08x ps %08x\n", |
2253 | DRM_DEBUG("r6xx state allocated bo %08x vs %08x ps %08x\n", |
| 2252 | obj_size, vs_offset, ps_offset); |
2254 | obj_size, vs_offset, ps_offset); |
| 2253 | 2255 | ||
| 2254 | r = radeon_bo_pin(state_obj, RADEON_GEM_DOMAIN_VRAM, |
2256 | r = radeon_bo_pin(state_obj, RADEON_GEM_DOMAIN_VRAM, |
| 2255 | &state_gpu_addr); |
2257 | &state_gpu_addr); |
| 2256 | if (r) { |
2258 | if (r) { |
| 2257 | DRM_ERROR("failed to pin state object %d\n", r); |
2259 | DRM_ERROR("failed to pin state object %d\n", r); |
| 2258 | return r; |
2260 | return r; |
| 2259 | }; |
2261 | }; |
| 2260 | 2262 | ||
| 2261 | r = radeon_bo_kmap(state_obj, &ptr); |
2263 | r = radeon_bo_kmap(state_obj, &ptr); |
| 2262 | if (r) { |
2264 | if (r) { |
| 2263 | DRM_ERROR("failed to map state object %d\n", r); |
2265 | DRM_ERROR("failed to map state object %d\n", r); |
| 2264 | return r; |
2266 | return r; |
| 2265 | }; |
2267 | }; |
| 2266 | 2268 | ||
| 2267 | if (rdev->family >= CHIP_RV770) |
2269 | if (rdev->family >= CHIP_RV770) |
| 2268 | memcpy_toio(ptr + state_offset, |
2270 | memcpy_toio(ptr + state_offset, |
| 2269 | r7xx_default_state, state_len * 4); |
2271 | r7xx_default_state, state_len * 4); |
| 2270 | else |
2272 | else |
| 2271 | memcpy_toio(ptr + state_offset, |
2273 | memcpy_toio(ptr + state_offset, |
| 2272 | r6xx_default_state, state_len * 4); |
2274 | r6xx_default_state, state_len * 4); |
| 2273 | 2275 | ||
| 2274 | if (num_packet2s) |
2276 | if (num_packet2s) |
| 2275 | memcpy_toio(ptr + state_offset + (state_len * 4), |
2277 | memcpy_toio(ptr + state_offset + (state_len * 4), |
| 2276 | packet2s, num_packet2s * 4); |
2278 | packet2s, num_packet2s * 4); |
| 2277 | 2279 | ||
| 2278 | memcpy(ptr + vs_offset, vs_shader, vs_size * 4); |
2280 | memcpy(ptr + vs_offset, vs_shader, vs_size * 4); |
| 2279 | memcpy(ptr + ps_offset, ps_shader, ps_size * 4); |
2281 | memcpy(ptr + ps_offset, ps_shader, ps_size * 4); |
| 2280 | 2282 | ||
| 2281 | 2283 | ||
| 2282 | vb = (float*)(ptr + vb_offset); |
2284 | vb = (float*)(ptr + vb_offset); |
| 2283 | 2285 | ||
| 2284 | vb[0] = (float)64; |
2286 | vb[0] = (float)64; |
| 2285 | vb[1] = (float)64; |
2287 | vb[1] = (float)64; |
| 2286 | 2288 | ||
| 2287 | vb[2] = (float)64; |
2289 | vb[2] = (float)64; |
| 2288 | vb[3] = (float)(64+128); |
2290 | vb[3] = (float)(64+128); |
| 2289 | 2291 | ||
| 2290 | vb[4] = (float)(64+128); |
2292 | vb[4] = (float)(64+128); |
| 2291 | vb[5] = (float)(64+128); |
2293 | vb[5] = (float)(64+128); |
| 2292 | 2294 | ||
| 2293 | int vb_index = 3; |
2295 | int vb_index = 3; |
| 2294 | int vb_size = vb_index * 8; |
2296 | int vb_size = vb_index * 8; |
| 2295 | int vtx_num_entries = vb_size / 4; |
2297 | int vtx_num_entries = vb_size / 4; |
| 2296 | 2298 | ||
| 2297 | // radeon_bo_kunmap(state_obj); |
2299 | // radeon_bo_kunmap(state_obj); |
| 2298 | 2300 | ||
| 2299 | r = radeon_ring_lock(rdev, 1024); |
2301 | r = radeon_ring_lock(rdev, 1024); |
| 2300 | if (r) { |
2302 | if (r) { |
| 2301 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
2303 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
| 2302 | return r; |
2304 | return r; |
| 2303 | } |
2305 | } |
| 2304 | 2306 | ||
| 2305 | set_default_state(rdev, state_gpu_addr, state_len); |
2307 | set_default_state(rdev, state_gpu_addr, state_len); |
| 2306 | 2308 | ||
| 2307 | 2309 | ||
| 2308 | u64 gpu_addr; |
2310 | u64 gpu_addr; |
| 2309 | u32 sq_pgm_resources; |
2311 | u32 sq_pgm_resources; |
| 2310 | 2312 | ||
| 2311 | /* setup shader regs */ |
2313 | /* setup shader regs */ |
| 2312 | 2314 | ||
| 2313 | /* VS */ |
2315 | /* VS */ |
| 2314 | 2316 | ||
| 2315 | sq_pgm_resources = (2 << 0); |
2317 | sq_pgm_resources = (2 << 0); |
| 2316 | gpu_addr = state_gpu_addr + vs_offset; |
2318 | gpu_addr = state_gpu_addr + vs_offset; |
| 2317 | 2319 | ||
| 2318 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
2320 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 2319 | radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
2321 | radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 2320 | radeon_ring_write(rdev, gpu_addr >> 8); |
2322 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 2321 | 2323 | ||
| 2322 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
2324 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 2323 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
2325 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 2324 | radeon_ring_write(rdev, sq_pgm_resources); |
2326 | radeon_ring_write(rdev, sq_pgm_resources); |
| 2325 | 2327 | ||
| 2326 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
2328 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 2327 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
2329 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 2328 | radeon_ring_write(rdev, 0); |
2330 | radeon_ring_write(rdev, 0); |
| 2329 | 2331 | ||
| 2330 | /* PS */ |
2332 | /* PS */ |
| 2331 | 2333 | ||
| 2332 | sq_pgm_resources = (1 << 0); |
2334 | sq_pgm_resources = (1 << 0); |
| 2333 | gpu_addr = state_gpu_addr + ps_offset; |
2335 | gpu_addr = state_gpu_addr + ps_offset; |
| 2334 | 2336 | ||
| 2335 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
2337 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 2336 | radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
2338 | radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 2337 | radeon_ring_write(rdev, gpu_addr >> 8); |
2339 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 2338 | 2340 | ||
| 2339 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
2341 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 2340 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
2342 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 2341 | radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); |
2343 | radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); |
| 2342 | 2344 | ||
| 2343 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
2345 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 2344 | radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
2346 | radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 2345 | radeon_ring_write(rdev, 2); |
2347 | radeon_ring_write(rdev, 2); |
| 2346 | 2348 | ||
| 2347 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
2349 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 2348 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
2350 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 2349 | radeon_ring_write(rdev, 0); |
2351 | radeon_ring_write(rdev, 0); |
| 2350 | 2352 | ||
| 2351 | gpu_addr = state_gpu_addr + vs_offset; |
2353 | gpu_addr = state_gpu_addr + vs_offset; |
| 2352 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
2354 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
| 2353 | 2355 | ||
| 2354 | 2356 | ||
| 2355 | set_render_target(rdev, COLOR_8_8_8_8, 1024, 768, /* FIXME */ |
2357 | set_render_target(rdev, COLOR_8_8_8_8, 1024, 768, /* FIXME */ |
| 2356 | rdev->mc.vram_start); |
2358 | rdev->mc.vram_start); |
| 2357 | 2359 | ||
| 2358 | set_scissors(rdev, 0, 0, 1024, 768); |
2360 | set_scissors(rdev, 0, 0, 1024, 768); |
| 2359 | 2361 | ||
| 2360 | 2362 | ||
| 2361 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_ALU_CONST, 4)); |
2363 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_ALU_CONST, 4)); |
| 2362 | radeon_ring_write(rdev, (SQ_ALU_CONSTANT0_0 - PACKET3_SET_ALU_CONST_OFFSET) >> 2); |
2364 | radeon_ring_write(rdev, (SQ_ALU_CONSTANT0_0 - PACKET3_SET_ALU_CONST_OFFSET) >> 2); |
| 2363 | EFLOAT(0.0f); /* r */ |
2365 | EFLOAT(0.0f); /* r */ |
| 2364 | EFLOAT(1.0f); /* g */ |
2366 | EFLOAT(1.0f); /* g */ |
| 2365 | EFLOAT(0.0f); /* b */ |
2367 | EFLOAT(0.0f); /* b */ |
| 2366 | EFLOAT(1.0f); /* a */ |
2368 | EFLOAT(1.0f); /* a */ |
| 2367 | 2369 | ||
| 2368 | u32 sq_vtx_constant_word2; |
2370 | u32 sq_vtx_constant_word2; |
| 2369 | 2371 | ||
| 2370 | gpu_addr = state_gpu_addr + vb_offset; |
2372 | gpu_addr = state_gpu_addr + vb_offset; |
| 2371 | 2373 | ||
| 2372 | sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (8 << 8)); |
2374 | sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (8 << 8)); |
| 2373 | 2375 | ||
| 2374 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); |
2376 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); |
| 2375 | radeon_ring_write(rdev, 0x460); |
2377 | radeon_ring_write(rdev, 0x460); |
| 2376 | radeon_ring_write(rdev, gpu_addr & 0xffffffff); /* 0: BASE_ADDRESS */ |
2378 | radeon_ring_write(rdev, gpu_addr & 0xffffffff); /* 0: BASE_ADDRESS */ |
| 2377 | radeon_ring_write(rdev, (vtx_num_entries << 2) - 1); /* 1: SIZE */ |
2379 | radeon_ring_write(rdev, (vtx_num_entries << 2) - 1); /* 1: SIZE */ |
| 2378 | radeon_ring_write(rdev, sq_vtx_constant_word2); /* 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN */ |
2380 | radeon_ring_write(rdev, sq_vtx_constant_word2); /* 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN */ |
| 2379 | radeon_ring_write(rdev, 1 << 0); /* 3: MEM_REQUEST_SIZE ?!? */ |
2381 | radeon_ring_write(rdev, 1 << 0); /* 3: MEM_REQUEST_SIZE ?!? */ |
| 2380 | radeon_ring_write(rdev, 0); |
2382 | radeon_ring_write(rdev, 0); |
| 2381 | radeon_ring_write(rdev, 0); |
2383 | radeon_ring_write(rdev, 0); |
| 2382 | radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); |
2384 | radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); |
| 2383 | 2385 | ||
| 2384 | if ((rdev->family == CHIP_RV610) || |
2386 | if ((rdev->family == CHIP_RV610) || |
| 2385 | (rdev->family == CHIP_RV620) || |
2387 | (rdev->family == CHIP_RV620) || |
| 2386 | (rdev->family == CHIP_RS780) || |
2388 | (rdev->family == CHIP_RS780) || |
| 2387 | (rdev->family == CHIP_RS880) || |
2389 | (rdev->family == CHIP_RS880) || |
| 2388 | (rdev->family == CHIP_RV710)) |
2390 | (rdev->family == CHIP_RV710)) |
| 2389 | cp_set_surface_sync(rdev, |
2391 | cp_set_surface_sync(rdev, |
| 2390 | PACKET3_TC_ACTION_ENA, 24, gpu_addr); |
2392 | PACKET3_TC_ACTION_ENA, 24, gpu_addr); |
| 2391 | else |
2393 | else |
| 2392 | cp_set_surface_sync(rdev, |
2394 | cp_set_surface_sync(rdev, |
| 2393 | PACKET3_VC_ACTION_ENA, 24, gpu_addr); |
2395 | PACKET3_VC_ACTION_ENA, 24, gpu_addr); |
| 2394 | 2396 | ||
| 2395 | draw_auto(rdev); |
2397 | draw_auto(rdev); |
| 2396 | 2398 | ||
| 2397 | cp_set_surface_sync(rdev, PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
2399 | cp_set_surface_sync(rdev, PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
| 2398 | 1024*4*512, offset); |
2400 | 1024*4*512, offset); |
| 2399 | 2401 | ||
| 2400 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); |
2402 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); |
| 2401 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); |
2403 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); |
| 2402 | /* wait for 3D idle clean */ |
2404 | /* wait for 3D idle clean */ |
| 2403 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2405 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 2404 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
2406 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| 2405 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); |
2407 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); |
| 2406 | 2408 | ||
| 2407 | radeon_ring_unlock_commit(rdev); |
2409 | radeon_ring_unlock_commit(rdev); |
| 2408 | 2410 | ||
| 2409 | r600_ring_test(rdev); |
2411 | r600_ring_test(rdev); |
| 2410 | 2412 | ||
| 2411 | LEAVE(); |
2413 | LEAVE(); |
| 2412 | return r; |
2414 | return r; |
| 2413 | } |
2415 | } |
| 2414 | 2416 | ||
| 2415 | > |
2417 | > |
| 2416 | 2418 | ||
| 2417 | > |
2419 | > |
| 2418 | > |
2420 | > |
| 2419 | > |
2421 | > |