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Rev 5271 Rev 6104
Line 36... Line 36...
36
 
36
 
37
/* 1 second timeout */
37
/* 1 second timeout */
Line 38... Line 38...
38
#define VCE_IDLE_TIMEOUT_MS	1000
38
#define VCE_IDLE_TIMEOUT_MS	1000
-
 
39
 
39
 
40
/* Firmware Names */
Line -... Line 41...
-
 
41
#define FIRMWARE_TAHITI	"radeon/TAHITI_vce.bin"
40
/* Firmware Names */
42
#define FIRMWARE_BONAIRE	"radeon/BONAIRE_vce.bin"
Line 41... Line 43...
41
#define FIRMWARE_BONAIRE	"radeon/BONAIRE_vce.bin"
43
 
Line 42... Line 44...
42
 
44
MODULE_FIRMWARE(FIRMWARE_TAHITI);
Line 61... Line 63...
61
	int i, r;
63
	int i, r;
Line 62... Line 64...
62
 
64
 
Line 63... Line 65...
63
	INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler);
65
	INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler);
-
 
66
 
-
 
67
	switch (rdev->family) {
-
 
68
	case CHIP_TAHITI:
-
 
69
	case CHIP_PITCAIRN:
-
 
70
	case CHIP_VERDE:
-
 
71
	case CHIP_OLAND:
-
 
72
	case CHIP_ARUBA:
-
 
73
		fw_name = FIRMWARE_TAHITI;
64
 
74
		break;
65
	switch (rdev->family) {
75
 
66
	case CHIP_BONAIRE:
76
	case CHIP_BONAIRE:
67
	case CHIP_KAVERI:
77
	case CHIP_KAVERI:
68
	case CHIP_KABINI:
78
	case CHIP_KABINI:
Line 116... Line 126...
116
		 start, mid, end, rdev->vce.fb_version);
126
		 start, mid, end, rdev->vce.fb_version);
Line 117... Line 127...
117
 
127
 
Line 118... Line 128...
118
	rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8);
128
	rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8);
119
 
129
 
-
 
130
	/* we can only work with this fw version for now */
-
 
131
	if ((rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) &&
120
	/* we can only work with this fw version for now */
132
	    (rdev->vce.fw_version != ((50 << 24) | (0 << 16) | (1 << 8))) &&
Line 121... Line 133...
121
	if (rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8)))
133
	    (rdev->vce.fw_version != ((50 << 24) | (1 << 16) | (2 << 8))))
Line -... Line 134...
-
 
134
		return -EINVAL;
122
		return -EINVAL;
135
 
-
 
136
	/* allocate firmware, stack and heap BO */
123
 
137
 
124
	/* allocate firmware, stack and heap BO */
138
	if (rdev->family < CHIP_BONAIRE)
125
 
139
		size = vce_v1_0_bo_size(rdev);
126
	size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) +
140
	else
127
	       RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE;
141
		size = vce_v2_0_bo_size(rdev);
128
	r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
142
	r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
Line 223... Line 237...
223
		radeon_bo_unreserve(rdev->vce.vcpu_bo);
237
		radeon_bo_unreserve(rdev->vce.vcpu_bo);
224
		dev_err(rdev->dev, "(%d) VCE map failed\n", r);
238
		dev_err(rdev->dev, "(%d) VCE map failed\n", r);
225
		return r;
239
		return r;
226
	}
240
	}
Line -... Line 241...
-
 
241
 
-
 
242
	memset(cpu_addr, 0, radeon_bo_size(rdev->vce.vcpu_bo));
-
 
243
	if (rdev->family < CHIP_BONAIRE)
-
 
244
		r = vce_v1_0_load_fw(rdev, cpu_addr);
227
 
245
	else
Line 228... Line 246...
228
	memcpy(cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size);
246
		memcpy(cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size);
Line 229... Line 247...
229
 
247
 
Line 230... Line 248...
230
	radeon_bo_kunmap(rdev->vce.vcpu_bo);
248
	radeon_bo_kunmap(rdev->vce.vcpu_bo);
231
 
249
 
Line 232... Line 250...
232
	radeon_bo_unreserve(rdev->vce.vcpu_bo);
250
	radeon_bo_unreserve(rdev->vce.vcpu_bo);
233
 
251
 
234
	return 0;
252
	return r;
Line 341... Line 359...
341
 
359
 
Line 342... Line 360...
342
	dummy = ib.gpu_addr + 1024;
360
	dummy = ib.gpu_addr + 1024;
343
 
361
 
344
	/* stitch together an VCE create msg */
362
	/* stitch together an VCE create msg */
345
	ib.length_dw = 0;
363
	ib.length_dw = 0;
346
	ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
364
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
347
	ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
365
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
348
	ib.ptr[ib.length_dw++] = handle;
366
	ib.ptr[ib.length_dw++] = cpu_to_le32(handle);
349
 
367
 
350
	ib.ptr[ib.length_dw++] = 0x00000030; /* len */
368
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000030); /* len */
351
	ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */
369
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x01000001); /* create cmd */
352
	ib.ptr[ib.length_dw++] = 0x00000000;
370
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000000);
353
	ib.ptr[ib.length_dw++] = 0x00000042;
371
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000042);
354
	ib.ptr[ib.length_dw++] = 0x0000000a;
372
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000a);
355
	ib.ptr[ib.length_dw++] = 0x00000001;
373
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
356
	ib.ptr[ib.length_dw++] = 0x00000080;
374
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000080);
357
	ib.ptr[ib.length_dw++] = 0x00000060;
375
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000060);
358
	ib.ptr[ib.length_dw++] = 0x00000100;
376
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000100);
359
	ib.ptr[ib.length_dw++] = 0x00000100;
377
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000100);
360
	ib.ptr[ib.length_dw++] = 0x0000000c;
378
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c);
361
	ib.ptr[ib.length_dw++] = 0x00000000;
379
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000000);
362
 
380
 
363
	ib.ptr[ib.length_dw++] = 0x00000014; /* len */
381
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000014); /* len */
364
	ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
382
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x05000005); /* feedback buffer */
365
	ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
383
	ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));
Line 366... Line 384...
366
	ib.ptr[ib.length_dw++] = dummy;
384
	ib.ptr[ib.length_dw++] = cpu_to_le32(dummy);
367
	ib.ptr[ib.length_dw++] = 0x00000001;
385
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
Line 368... Line 386...
368
 
386
 
369
	for (i = ib.length_dw; i < ib_size_dw; ++i)
387
	for (i = ib.length_dw; i < ib_size_dw; ++i)
370
		ib.ptr[i] = 0x0;
388
		ib.ptr[i] = cpu_to_le32(0x0);
371
 
389
 
Line 408... Line 426...
408
 
426
 
Line 409... Line 427...
409
	dummy = ib.gpu_addr + 1024;
427
	dummy = ib.gpu_addr + 1024;
410
 
428
 
411
	/* stitch together an VCE destroy msg */
429
	/* stitch together an VCE destroy msg */
412
	ib.length_dw = 0;
430
	ib.length_dw = 0;
413
	ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
431
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
414
	ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
432
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
415
	ib.ptr[ib.length_dw++] = handle;
433
	ib.ptr[ib.length_dw++] = cpu_to_le32(handle);
416
 
434
 
417
	ib.ptr[ib.length_dw++] = 0x00000014; /* len */
435
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000014); /* len */
418
	ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
436
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x05000005); /* feedback buffer */
419
	ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
437
	ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));
Line 420... Line 438...
420
	ib.ptr[ib.length_dw++] = dummy;
438
	ib.ptr[ib.length_dw++] = cpu_to_le32(dummy);
421
	ib.ptr[ib.length_dw++] = 0x00000001;
439
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
Line 422... Line 440...
422
 
440
 
423
	ib.ptr[ib.length_dw++] = 0x00000008; /* len */
441
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000008); /* len */
Line 424... Line 442...
424
	ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */
442
	ib.ptr[ib.length_dw++] = cpu_to_le32(0x02000001); /* destroy cmd */
425
 
443
 
426
	for (i = ib.length_dw; i < ib_size_dw; ++i)
444
	for (i = ib.length_dw; i < ib_size_dw; ++i)
427
		ib.ptr[i] = 0x0;
445
		ib.ptr[i] = cpu_to_le32(0x0);
Line 491... Line 509...
491
/**
509
/**
492
 * radeon_vce_validate_handle - validate stream handle
510
 * radeon_vce_validate_handle - validate stream handle
493
 *
511
 *
494
 * @p: parser context
512
 * @p: parser context
495
 * @handle: handle to validate
513
 * @handle: handle to validate
-
 
514
 * @allocated: allocated a new handle?
496
 *
515
 *
497
 * Validates the handle and return the found session index or -EINVAL
516
 * Validates the handle and return the found session index or -EINVAL
498
 * we we don't have another free session index.
517
 * we we don't have another free session index.
499
 */
518
 */
500
int radeon_vce_validate_handle(struct radeon_cs_parser *p, uint32_t handle)
519
static int radeon_vce_validate_handle(struct radeon_cs_parser *p,
-
 
520
				      uint32_t handle, bool *allocated)
501
{
521
{
502
	unsigned i;
522
	unsigned i;
Line -... Line 523...
-
 
523
 
-
 
524
	*allocated = false;
503
 
525
 
504
	/* validate the handle */
526
	/* validate the handle */
505
	for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
527
	for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
-
 
528
		if (atomic_read(&p->rdev->vce.handles[i]) == handle) {
-
 
529
			if (p->rdev->vce.filp[i] != p->filp) {
-
 
530
				DRM_ERROR("VCE handle collision detected!\n");
-
 
531
				return -EINVAL;
506
		if (atomic_read(&p->rdev->vce.handles[i]) == handle)
532
			}
507
			return i;
533
			return i;
-
 
534
		}
Line 508... Line 535...
508
	}
535
	}
509
 
536
 
510
	/* handle not found try to alloc a new one */
537
	/* handle not found try to alloc a new one */
511
	for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
538
	for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
512
		if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) {
539
		if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) {
-
 
540
			p->rdev->vce.filp[i] = p->filp;
513
			p->rdev->vce.filp[i] = p->filp;
541
			p->rdev->vce.img_size[i] = 0;
514
			p->rdev->vce.img_size[i] = 0;
542
			*allocated = true;
515
			return i;
543
			return i;
Line 516... Line 544...
516
		}
544
		}
Line 527... Line 555...
527
 *
555
 *
528
 */
556
 */
529
int radeon_vce_cs_parse(struct radeon_cs_parser *p)
557
int radeon_vce_cs_parse(struct radeon_cs_parser *p)
530
{
558
{
531
	int session_idx = -1;
559
	int session_idx = -1;
532
	bool destroyed = false;
560
	bool destroyed = false, created = false, allocated = false;
533
	uint32_t tmp, handle = 0;
561
	uint32_t tmp, handle = 0;
534
	uint32_t *size = &tmp;
562
	uint32_t *size = &tmp;
535
	int i, r;
563
	int i, r = 0;
Line 536... Line 564...
536
 
564
 
537
	while (p->idx < p->chunk_ib->length_dw) {
565
	while (p->idx < p->chunk_ib->length_dw) {
538
		uint32_t len = radeon_get_ib_value(p, p->idx);
566
		uint32_t len = radeon_get_ib_value(p, p->idx);
Line 539... Line 567...
539
		uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);
567
		uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);
540
 
568
 
541
		if ((len < 8) || (len & 3)) {
569
		if ((len < 8) || (len & 3)) {
-
 
570
			DRM_ERROR("invalid VCE command length (%d)!\n", len);
542
			DRM_ERROR("invalid VCE command length (%d)!\n", len);
571
			r = -EINVAL;
Line 543... Line 572...
543
                	return -EINVAL;
572
			goto out;
544
		}
573
		}
545
 
574
 
-
 
575
		if (destroyed) {
546
		if (destroyed) {
576
			DRM_ERROR("No other command allowed after destroy!\n");
Line 547... Line 577...
547
			DRM_ERROR("No other command allowed after destroy!\n");
577
			r = -EINVAL;
548
			return -EINVAL;
578
			goto out;
549
		}
579
		}
550
 
580
 
-
 
581
		switch (cmd) {
551
		switch (cmd) {
582
		case 0x00000001: // session
552
		case 0x00000001: // session
583
			handle = radeon_get_ib_value(p, p->idx + 2);
553
			handle = radeon_get_ib_value(p, p->idx + 2);
584
			session_idx = radeon_vce_validate_handle(p, handle,
554
			session_idx = radeon_vce_validate_handle(p, handle);
585
								 &allocated);
Line 555... Line 586...
555
			if (session_idx < 0)
586
			if (session_idx < 0)
556
				return session_idx;
587
				return session_idx;
Line 557... Line 588...
557
			size = &p->rdev->vce.img_size[session_idx];
588
			size = &p->rdev->vce.img_size[session_idx];
-
 
589
			break;
-
 
590
 
-
 
591
		case 0x00000002: // task info
-
 
592
			break;
-
 
593
 
-
 
594
		case 0x01000001: // create
-
 
595
			created = true;
558
			break;
596
			if (!allocated) {
559
 
597
				DRM_ERROR("Handle already in use!\n");
560
		case 0x00000002: // task info
598
				r = -EINVAL;
561
			break;
599
				goto out;
Line 562... Line 600...
562
 
600
			}
563
		case 0x01000001: // create
601
 
564
			*size = radeon_get_ib_value(p, p->idx + 8) *
602
			*size = radeon_get_ib_value(p, p->idx + 8) *
565
				radeon_get_ib_value(p, p->idx + 10) *
603
				radeon_get_ib_value(p, p->idx + 10) *
566
				8 * 3 / 2;
604
				8 * 3 / 2;
-
 
605
			break;
567
			break;
606
 
Line 568... Line 607...
568
 
607
		case 0x04000001: // config extension
569
		case 0x04000001: // config extension
608
		case 0x04000002: // pic control
570
		case 0x04000002: // pic control
609
		case 0x04000005: // rate control
571
		case 0x04000005: // rate control
610
		case 0x04000007: // motion estimation
572
		case 0x04000007: // motion estimation
611
		case 0x04000008: // rdo
Line 573... Line 612...
573
		case 0x04000008: // rdo
612
		case 0x04000009: // vui
574
			break;
613
			break;
575
 
614
 
576
		case 0x03000001: // encode
615
		case 0x03000001: // encode
577
			r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9,
616
			r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9,
Line 578... Line 617...
578
						*size);
617
						*size);
579
			if (r)
618
			if (r)
580
				return r;
619
				goto out;
Line 581... Line 620...
581
 
620
 
582
			r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11,
621
			r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11,
583
						*size / 3);
622
						*size / 3);
584
			if (r)
623
			if (r)
585
				return r;
624
				goto out;
586
			break;
625
			break;
Line 587... Line 626...
587
 
626
 
588
		case 0x02000001: // destroy
627
		case 0x02000001: // destroy
589
			destroyed = true;
628
			destroyed = true;
590
			break;
629
			break;
591
 
630
 
592
		case 0x05000001: // context buffer
631
		case 0x05000001: // context buffer
593
			r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
632
			r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
Line 594... Line 633...
594
						*size * 2);
633
						*size * 2);
595
			if (r)
634
			if (r)
596
				return r;
635
				goto out;
597
			break;
636
			break;
598
 
637
 
599
		case 0x05000004: // video bitstream buffer
638
		case 0x05000004: // video bitstream buffer
Line 600... Line 639...
600
			tmp = radeon_get_ib_value(p, p->idx + 4);
639
			tmp = radeon_get_ib_value(p, p->idx + 4);
601
			r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
640
			r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
602
						tmp);
641
						tmp);
-
 
642
			if (r)
603
			if (r)
643
				goto out;
Line 604... Line 644...
604
				return r;
644
			break;
605
			break;
645
 
606
 
646
		case 0x05000005: // feedback buffer
-
 
647
			r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
607
		case 0x05000005: // feedback buffer
648
						4096);
Line 608... Line 649...
608
			r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
649
			if (r)
609
						4096);
650
				goto out;
Line 610... Line 651...
610
			if (r)
651
			break;
-
 
652
 
-
 
653
		default:
-
 
654
			DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
-
 
655
			r = -EINVAL;
-
 
656
			goto out;
-
 
657
		}
-
 
658
 
611
				return r;
659
		if (session_idx == -1) {
-
 
660
			DRM_ERROR("no session command at start of IB\n");
-
 
661
			r = -EINVAL;
612
			break;
662
			goto out;
613
 
663
		}
614
		default:
664
 
Line 615... Line 665...
615
			DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
665
		p->idx += len / 4;
616
			return -EINVAL;
666
	}
Line 617... Line 667...
617
		}
667
 
618
 
668
	if (allocated && !created) {
619
		if (session_idx == -1) {
669
		DRM_ERROR("New session without create command!\n");
Line 647... Line 697...
647
			       struct radeon_semaphore *semaphore,
697
			       struct radeon_semaphore *semaphore,
648
			       bool emit_wait)
698
			       bool emit_wait)
649
{
699
{
650
	uint64_t addr = semaphore->gpu_addr;
700
	uint64_t addr = semaphore->gpu_addr;
Line 651... Line 701...
651
 
701
 
652
	radeon_ring_write(ring, VCE_CMD_SEMAPHORE);
702
	radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE));
653
	radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
703
	radeon_ring_write(ring, cpu_to_le32((addr >> 3) & 0x000FFFFF));
654
	radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
704
	radeon_ring_write(ring, cpu_to_le32((addr >> 23) & 0x000FFFFF));
655
	radeon_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
705
	radeon_ring_write(ring, cpu_to_le32(0x01003000 | (emit_wait ? 1 : 0)));
656
	if (!emit_wait)
706
	if (!emit_wait)
Line 657... Line 707...
657
		radeon_ring_write(ring, VCE_CMD_END);
707
		radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
658
 
708
 
Line 659... Line 709...
659
	return true;
709
	return true;
Line 667... Line 717...
667
 *
717
 *
668
 */
718
 */
669
void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
719
void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
670
{
720
{
671
	struct radeon_ring *ring = &rdev->ring[ib->ring];
721
	struct radeon_ring *ring = &rdev->ring[ib->ring];
672
	radeon_ring_write(ring, VCE_CMD_IB);
722
	radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB));
673
	radeon_ring_write(ring, ib->gpu_addr);
723
	radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr));
674
	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
724
	radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr)));
675
	radeon_ring_write(ring, ib->length_dw);
725
	radeon_ring_write(ring, cpu_to_le32(ib->length_dw));
676
}
726
}
Line 677... Line 727...
677
 
727
 
678
/**
728
/**
679
 * radeon_vce_fence_emit - add a fence command to the ring
729
 * radeon_vce_fence_emit - add a fence command to the ring
Line 686... Line 736...
686
			   struct radeon_fence *fence)
736
			   struct radeon_fence *fence)
687
{
737
{
688
	struct radeon_ring *ring = &rdev->ring[fence->ring];
738
	struct radeon_ring *ring = &rdev->ring[fence->ring];
689
	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
739
	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
Line 690... Line 740...
690
 
740
 
691
	radeon_ring_write(ring, VCE_CMD_FENCE);
741
	radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE));
692
	radeon_ring_write(ring, addr);
742
	radeon_ring_write(ring, cpu_to_le32(addr));
693
	radeon_ring_write(ring, upper_32_bits(addr));
743
	radeon_ring_write(ring, cpu_to_le32(upper_32_bits(addr)));
694
	radeon_ring_write(ring, fence->seq);
744
	radeon_ring_write(ring, cpu_to_le32(fence->seq));
695
	radeon_ring_write(ring, VCE_CMD_TRAP);
745
	radeon_ring_write(ring, cpu_to_le32(VCE_CMD_TRAP));
696
	radeon_ring_write(ring, VCE_CMD_END);
746
	radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
Line 697... Line 747...
697
}
747
}
698
 
748
 
699
/**
749
/**
Line 713... Line 763...
713
	if (r) {
763
	if (r) {
714
		DRM_ERROR("radeon: vce failed to lock ring %d (%d).\n",
764
		DRM_ERROR("radeon: vce failed to lock ring %d (%d).\n",
715
			  ring->idx, r);
765
			  ring->idx, r);
716
		return r;
766
		return r;
717
	}
767
	}
718
	radeon_ring_write(ring, VCE_CMD_END);
768
	radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
719
	radeon_ring_unlock_commit(rdev, ring, false);
769
	radeon_ring_unlock_commit(rdev, ring, false);
Line 720... Line 770...
720
 
770
 
721
	for (i = 0; i < rdev->usec_timeout; i++) {
771
	for (i = 0; i < rdev->usec_timeout; i++) {
722
	        if (vce_v1_0_get_rptr(rdev, ring) != rptr)
772
	        if (vce_v1_0_get_rptr(rdev, ring) != rptr)