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Rev 5078 | Rev 5271 | ||
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Line 124... | Line 124... | ||
124 | /* allocate firmware, stack and heap BO */ |
124 | /* allocate firmware, stack and heap BO */ |
Line 125... | Line 125... | ||
125 | 125 | ||
126 | size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) + |
126 | size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) + |
127 | RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE; |
127 | RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE; |
128 | r = radeon_bo_create(rdev, size, PAGE_SIZE, true, |
128 | r = radeon_bo_create(rdev, size, PAGE_SIZE, true, |
- | 129 | RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL, |
|
129 | RADEON_GEM_DOMAIN_VRAM, 0, NULL, &rdev->vce.vcpu_bo); |
130 | &rdev->vce.vcpu_bo); |
130 | if (r) { |
131 | if (r) { |
131 | dev_err(rdev->dev, "(%d) failed to allocate VCE bo\n", r); |
132 | dev_err(rdev->dev, "(%d) failed to allocate VCE bo\n", r); |
132 | return r; |
133 | return r; |
Line 450... | Line 451... | ||
450 | */ |
451 | */ |
451 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, |
452 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, |
452 | unsigned size) |
453 | unsigned size) |
453 | { |
454 | { |
454 | struct radeon_cs_chunk *relocs_chunk; |
455 | struct radeon_cs_chunk *relocs_chunk; |
455 | struct radeon_cs_reloc *reloc; |
456 | struct radeon_bo_list *reloc; |
456 | uint64_t start, end, offset; |
457 | uint64_t start, end, offset; |
457 | unsigned idx; |
458 | unsigned idx; |
Line 458... | Line 459... | ||
458 | 459 | ||
459 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
460 | relocs_chunk = p->chunk_relocs; |
460 | offset = radeon_get_ib_value(p, lo); |
461 | offset = radeon_get_ib_value(p, lo); |
Line 461... | Line 462... | ||
461 | idx = radeon_get_ib_value(p, hi); |
462 | idx = radeon_get_ib_value(p, hi); |
462 | 463 | ||
463 | if (idx >= relocs_chunk->length_dw) { |
464 | if (idx >= relocs_chunk->length_dw) { |
464 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
465 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
465 | idx, relocs_chunk->length_dw); |
466 | idx, relocs_chunk->length_dw); |
Line 466... | Line 467... | ||
466 | return -EINVAL; |
467 | return -EINVAL; |
467 | } |
468 | } |
468 | 469 | ||
469 | reloc = p->relocs_ptr[(idx / 4)]; |
470 | reloc = &p->relocs[(idx / 4)]; |
Line 470... | Line 471... | ||
470 | start = reloc->gpu_offset; |
471 | start = reloc->gpu_offset; |
Line 531... | Line 532... | ||
531 | bool destroyed = false; |
532 | bool destroyed = false; |
532 | uint32_t tmp, handle = 0; |
533 | uint32_t tmp, handle = 0; |
533 | uint32_t *size = &tmp; |
534 | uint32_t *size = &tmp; |
534 | int i, r; |
535 | int i, r; |
Line 535... | Line 536... | ||
535 | 536 | ||
536 | while (p->idx < p->chunks[p->chunk_ib_idx].length_dw) { |
537 | while (p->idx < p->chunk_ib->length_dw) { |
537 | uint32_t len = radeon_get_ib_value(p, p->idx); |
538 | uint32_t len = radeon_get_ib_value(p, p->idx); |
Line 538... | Line 539... | ||
538 | uint32_t cmd = radeon_get_ib_value(p, p->idx + 1); |
539 | uint32_t cmd = radeon_get_ib_value(p, p->idx + 1); |
539 | 540 |