WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_uvd.c


/*
 * Copyright 2011 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Christian König 
 */
 
#include 
#include 
#include 
#include 
 
#include "radeon.h"
#include "r600d.h"
 
/* 1 second timeout */
#define UVD_IDLE_TIMEOUT_MS	1000
 
/* Firmware Names */
#define FIRMWARE_R600		"radeon/R600_uvd.bin"
#define FIRMWARE_RS780		"radeon/RS780_uvd.bin"
#define FIRMWARE_RV770		"radeon/RV770_uvd.bin"
#define FIRMWARE_RV710		"radeon/RV710_uvd.bin"
#define FIRMWARE_CYPRESS	"radeon/CYPRESS_uvd.bin"
#define FIRMWARE_SUMO		"radeon/SUMO_uvd.bin"
#define FIRMWARE_TAHITI		"radeon/TAHITI_uvd.bin"
#define FIRMWARE_BONAIRE	"radeon/BONAIRE_uvd.bin"
 
MODULE_FIRMWARE(FIRMWARE_R600);
MODULE_FIRMWARE(FIRMWARE_RS780);
MODULE_FIRMWARE(FIRMWARE_RV770);
MODULE_FIRMWARE(FIRMWARE_RV710);
MODULE_FIRMWARE(FIRMWARE_CYPRESS);
MODULE_FIRMWARE(FIRMWARE_SUMO);
MODULE_FIRMWARE(FIRMWARE_TAHITI);
MODULE_FIRMWARE(FIRMWARE_BONAIRE);
 
static void radeon_uvd_idle_work_handler(struct work_struct *work);
 
int radeon_uvd_init(struct radeon_device *rdev)
{
	unsigned long bo_size;
	const char *fw_name;
	int i, r;
 
//   INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
 
	switch (rdev->family) {
	case CHIP_RV610:
	case CHIP_RV630:
	case CHIP_RV670:
	case CHIP_RV620:
	case CHIP_RV635:
		fw_name = FIRMWARE_R600;
		break;
 
	case CHIP_RS780:
	case CHIP_RS880:
		fw_name = FIRMWARE_RS780;
		break;
 
	case CHIP_RV770:
		fw_name = FIRMWARE_RV770;
		break;
 
	case CHIP_RV710:
	case CHIP_RV730:
	case CHIP_RV740:
		fw_name = FIRMWARE_RV710;
		break;
 
	case CHIP_CYPRESS:
	case CHIP_HEMLOCK:
	case CHIP_JUNIPER:
	case CHIP_REDWOOD:
	case CHIP_CEDAR:
		fw_name = FIRMWARE_CYPRESS;
		break;
 
	case CHIP_SUMO:
	case CHIP_SUMO2:
	case CHIP_PALM:
	case CHIP_CAYMAN:
	case CHIP_BARTS:
	case CHIP_TURKS:
	case CHIP_CAICOS:
		fw_name = FIRMWARE_SUMO;
		break;
 
	case CHIP_TAHITI:
	case CHIP_VERDE:
	case CHIP_PITCAIRN:
	case CHIP_ARUBA:
	case CHIP_OLAND:
		fw_name = FIRMWARE_TAHITI;
		break;
 
	case CHIP_BONAIRE:
	case CHIP_KABINI:
	case CHIP_KAVERI:
	case CHIP_HAWAII:
	case CHIP_MULLINS:
		fw_name = FIRMWARE_BONAIRE;
		break;
 
	default:
		return -EINVAL;
	}
 
	r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
	if (r) {
		dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
			fw_name);
		return r;
	}
 
	bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
		  RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
		  RADEON_GPU_PAGE_SIZE;
	r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
			     RADEON_GEM_DOMAIN_VRAM, 0, NULL,
			     NULL, &rdev->uvd.vcpu_bo);
	if (r) {
		dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
		return r;
	}
 
	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
	if (r) {
		radeon_bo_unref(&rdev->uvd.vcpu_bo);
		dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
		return r;
	}
 
	r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
			  &rdev->uvd.gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->uvd.vcpu_bo);
		radeon_bo_unref(&rdev->uvd.vcpu_bo);
		dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
		return r;
	}
 
	r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
	if (r) {
		dev_err(rdev->dev, "(%d) UVD map failed\n", r);
		return r;
	}
 
	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 
	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
		atomic_set(&rdev->uvd.handles[i], 0);
		rdev->uvd.filp[i] = NULL;
		rdev->uvd.img_size[i] = 0;
	}
 
	return 0;
}
 
void radeon_uvd_fini(struct radeon_device *rdev)
{
	int r;
 
	if (rdev->uvd.vcpu_bo == NULL)
		return;
 
	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
	if (!r) {
		radeon_bo_kunmap(rdev->uvd.vcpu_bo);
		radeon_bo_unpin(rdev->uvd.vcpu_bo);
		radeon_bo_unreserve(rdev->uvd.vcpu_bo);
	}
 
	radeon_bo_unref(&rdev->uvd.vcpu_bo);
 
	radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
 
	release_firmware(rdev->uvd_fw);
}
 
int radeon_uvd_suspend(struct radeon_device *rdev)
{
 
 
	int i, r;
 
	if (rdev->uvd.vcpu_bo == NULL)
		return 0;
 
	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
		uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
		if (handle != 0) {
			struct radeon_fence *fence;
 
 
			radeon_uvd_note_usage(rdev);
 
			r = radeon_uvd_get_destroy_msg(rdev,
				R600_RING_TYPE_UVD_INDEX, handle, &fence);
			if (r) {
				DRM_ERROR("Error destroying UVD (%d)!\n", r);
				continue;
			}
 
			radeon_fence_wait(fence, false);
			radeon_fence_unref(&fence);
 
			rdev->uvd.filp[i] = NULL;
			atomic_set(&rdev->uvd.handles[i], 0);
		}
	}
 
	return 0;
}
 
int radeon_uvd_resume(struct radeon_device *rdev)
{
	unsigned size;
	void *ptr;
 
	if (rdev->uvd.vcpu_bo == NULL)
		return -EINVAL;
 
	memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
 
	size = radeon_bo_size(rdev->uvd.vcpu_bo);
	size -= rdev->uvd_fw->size;
 
	ptr = rdev->uvd.cpu_addr;
	ptr += rdev->uvd_fw->size;
 
 
 
 
 
 
	memset(ptr, 0, size);
 
	return 0;
}
 
void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
				       uint32_t allowed_domains)
{
	int i;
 
	for (i = 0; i < rbo->placement.num_placement; ++i) {
		rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
		rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
	}
 
	/* If it must be in VRAM it must be in the first segment as well */
	if (allowed_domains == RADEON_GEM_DOMAIN_VRAM)
		return;
 
	/* abort if we already have more than one placement */
	if (rbo->placement.num_placement > 1)
		return;
 
	/* add another 256MB segment */
	rbo->placements[1] = rbo->placements[0];
	rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
	rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
	rbo->placement.num_placement++;
	rbo->placement.num_busy_placement++;
}
 
void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
{
	int i, r;
	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
		uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
		if (handle != 0 && rdev->uvd.filp[i] == filp) {
			struct radeon_fence *fence;
 
			radeon_uvd_note_usage(rdev);
 
			r = radeon_uvd_get_destroy_msg(rdev,
				R600_RING_TYPE_UVD_INDEX, handle, &fence);
			if (r) {
				DRM_ERROR("Error destroying UVD (%d)!\n", r);
				continue;
			}
 
			radeon_fence_wait(fence, false);
			radeon_fence_unref(&fence);
 
			rdev->uvd.filp[i] = NULL;
			atomic_set(&rdev->uvd.handles[i], 0);
		}
	}
}
 
static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
{
	unsigned stream_type = msg[4];
	unsigned width = msg[6];
	unsigned height = msg[7];
	unsigned dpb_size = msg[9];
	unsigned pitch = msg[28];
 
	unsigned width_in_mb = width / 16;
	unsigned height_in_mb = ALIGN(height / 16, 2);
 
	unsigned image_size, tmp, min_dpb_size;
 
	image_size = width * height;
	image_size += image_size / 2;
	image_size = ALIGN(image_size, 1024);
 
	switch (stream_type) {
	case 0: /* H264 */
 
		/* reference picture buffer */
		min_dpb_size = image_size * 17;
 
		/* macroblock context buffer */
		min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
 
		/* IT surface buffer */
		min_dpb_size += width_in_mb * height_in_mb * 32;
		break;
 
	case 1: /* VC1 */
 
		/* reference picture buffer */
		min_dpb_size = image_size * 3;
 
		/* CONTEXT_BUFFER */
		min_dpb_size += width_in_mb * height_in_mb * 128;
 
		/* IT surface buffer */
		min_dpb_size += width_in_mb * 64;
 
		/* DB surface buffer */
		min_dpb_size += width_in_mb * 128;
 
		/* BP */
		tmp = max(width_in_mb, height_in_mb);
		min_dpb_size += ALIGN(tmp * 7 * 16, 64);
		break;
 
	case 3: /* MPEG2 */
 
		/* reference picture buffer */
		min_dpb_size = image_size * 3;
		break;
 
	case 4: /* MPEG4 */
 
		/* reference picture buffer */
		min_dpb_size = image_size * 3;
 
		/* CM */
		min_dpb_size += width_in_mb * height_in_mb * 64;
 
		/* IT surface buffer */
		min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
		break;
 
	default:
		DRM_ERROR("UVD codec not handled %d!\n", stream_type);
		return -EINVAL;
	}
 
	if (width > pitch) {
		DRM_ERROR("Invalid UVD decoding target pitch!\n");
		return -EINVAL;
	}
 
	if (dpb_size < min_dpb_size) {
		DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
			  dpb_size, min_dpb_size);
		return -EINVAL;
	}
 
	buf_sizes[0x1] = dpb_size;
	buf_sizes[0x2] = image_size;
	return 0;
}
 
static int radeon_uvd_validate_codec(struct radeon_cs_parser *p,
				     unsigned stream_type)
{
	switch (stream_type) {
	case 0: /* H264 */
	case 1: /* VC1 */
		/* always supported */
		return 0;
 
	case 3: /* MPEG2 */
	case 4: /* MPEG4 */
		/* only since UVD 3 */
		if (p->rdev->family >= CHIP_PALM)
			return 0;
 
		/* fall through */
	default:
		DRM_ERROR("UVD codec not supported by hardware %d!\n",
			  stream_type);
		return -EINVAL;
	}
}
 
static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
			     unsigned offset, unsigned buf_sizes[])
{
	int32_t *msg, msg_type, handle;
	unsigned img_size = 0;
	struct fence *f;
	void *ptr;
 
	int i, r;
 
	if (offset & 0x3F) {
		DRM_ERROR("UVD messages must be 64 byte aligned!\n");
		return -EINVAL;
	}
 
	f = reservation_object_get_excl(bo->tbo.resv);
	if (f) {
		r = radeon_fence_wait((struct radeon_fence *)f, false);
		if (r) {
			DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
			return r;
		}
	}
 
	r = radeon_bo_kmap(bo, &ptr);
	if (r) {
		DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
		return r;
	}
 
	msg = ptr + offset;
 
	msg_type = msg[1];
	handle = msg[2];
 
	if (handle == 0) {
		DRM_ERROR("Invalid UVD handle!\n");
		return -EINVAL;
	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
	switch (msg_type) {
	case 0:
		/* it's a create msg, calc image size (width * height) */
		img_size = msg[7] * msg[8];
 
		r = radeon_uvd_validate_codec(p, msg[4]);
		radeon_bo_kunmap(bo);
		if (r)
			return r;
 
		/* try to alloc a new handle */
		for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
			if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
				DRM_ERROR("Handle 0x%x already in use!\n", handle);
				return -EINVAL;
			}
 
			if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
				p->rdev->uvd.filp[i] = p->filp;
				p->rdev->uvd.img_size[i] = img_size;
				return 0;
			}
		}
 
		DRM_ERROR("No more free UVD handles!\n");
		return -EINVAL;
 
	case 1:
		/* it's a decode msg, validate codec and calc buffer sizes */
		r = radeon_uvd_validate_codec(p, msg[4]);
		if (!r)
			r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
		radeon_bo_kunmap(bo);
		if (r)
			return r;
 
		/* validate the handle */
		for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
			if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
				if (p->rdev->uvd.filp[i] != p->filp) {
					DRM_ERROR("UVD handle collision detected!\n");
					return -EINVAL;
				}
				return 0;
			}
		}
 
		DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
		return -ENOENT;
 
	case 2:
		/* it's a destroy msg, free the handle */
 
		for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
			atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
		radeon_bo_kunmap(bo);
		return 0;
 
	default:
 
		DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
		return -EINVAL;
	}
 
	BUG();
	return -EINVAL;
}
 
static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
			       int data0, int data1,
			       unsigned buf_sizes[], bool *has_msg_cmd)
{
	struct radeon_cs_chunk *relocs_chunk;
	struct radeon_bo_list *reloc;
	unsigned idx, cmd, offset;
	uint64_t start, end;
	int r;
 
	relocs_chunk = p->chunk_relocs;
	offset = radeon_get_ib_value(p, data0);
	idx = radeon_get_ib_value(p, data1);
	if (idx >= relocs_chunk->length_dw) {
		DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
			  idx, relocs_chunk->length_dw);
		return -EINVAL;
	}
 
	reloc = &p->relocs[(idx / 4)];
	start = reloc->gpu_offset;
	end = start + radeon_bo_size(reloc->robj);
	start += offset;
 
	p->ib.ptr[data0] = start & 0xFFFFFFFF;
	p->ib.ptr[data1] = start >> 32;
 
	cmd = radeon_get_ib_value(p, p->idx) >> 1;
 
	if (cmd < 0x4) {
		if (end <= start) {
			DRM_ERROR("invalid reloc offset %X!\n", offset);
			return -EINVAL;
		}
		if ((end - start) < buf_sizes[cmd]) {
			DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
				  (unsigned)(end - start), buf_sizes[cmd]);
			return -EINVAL;
		}
 
	} else if (cmd != 0x100) {
		DRM_ERROR("invalid UVD command %X!\n", cmd);
		return -EINVAL;
	}
 
	if ((start >> 28) != ((end - 1) >> 28)) {
		DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
			  start, end);
		return -EINVAL;
	}
 
	/* TODO: is this still necessary on NI+ ? */
	if ((cmd == 0 || cmd == 0x3) &&
	    (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
		DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
			  start, end);
		return -EINVAL;
	}
 
	if (cmd == 0) {
		if (*has_msg_cmd) {
			DRM_ERROR("More than one message in a UVD-IB!\n");
			return -EINVAL;
		}
		*has_msg_cmd = true;
		r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
		if (r)
			return r;
	} else if (!*has_msg_cmd) {
		DRM_ERROR("Message needed before other commands are send!\n");
		return -EINVAL;
	}
 
	return 0;
}
 
static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
			     struct radeon_cs_packet *pkt,
			     int *data0, int *data1,
			     unsigned buf_sizes[],
			     bool *has_msg_cmd)
{
	int i, r;
 
	p->idx++;
	for (i = 0; i <= pkt->count; ++i) {
		switch (pkt->reg + i*4) {
		case UVD_GPCOM_VCPU_DATA0:
			*data0 = p->idx;
			break;
		case UVD_GPCOM_VCPU_DATA1:
			*data1 = p->idx;
			break;
		case UVD_GPCOM_VCPU_CMD:
			r = radeon_uvd_cs_reloc(p, *data0, *data1,
						buf_sizes, has_msg_cmd);
			if (r)
				return r;
			break;
		case UVD_ENGINE_CNTL:
			break;
		default:
			DRM_ERROR("Invalid reg 0x%X!\n",
				  pkt->reg + i*4);
			return -EINVAL;
		}
		p->idx++;
	}
	return 0;
}
 
int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
{
	struct radeon_cs_packet pkt;
	int r, data0 = 0, data1 = 0;
 
	/* does the IB has a msg command */
	bool has_msg_cmd = false;
 
	/* minimum buffer sizes */
	unsigned buf_sizes[] = {
		[0x00000000]	=	2048,
		[0x00000001]	=	32 * 1024 * 1024,
		[0x00000002]	=	2048 * 1152 * 3,
		[0x00000003]	=	2048,
	};
 
	if (p->chunk_ib->length_dw % 16) {
		DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
			  p->chunk_ib->length_dw);
		return -EINVAL;
	}
 
	if (p->chunk_relocs == NULL) {
		DRM_ERROR("No relocation chunk !\n");
		return -EINVAL;
	}
 
 
	do {
		r = radeon_cs_packet_parse(p, &pkt, p->idx);
		if (r)
			return r;
		switch (pkt.type) {
		case RADEON_PACKET_TYPE0:
			r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
					      buf_sizes, &has_msg_cmd);
			if (r)
				return r;
			break;
		case RADEON_PACKET_TYPE2:
			p->idx += pkt.count + 2;
			break;
		default:
			DRM_ERROR("Unknown packet type %d !\n", pkt.type);
			return -EINVAL;
		}
	} while (p->idx < p->chunk_ib->length_dw);
 
	if (!has_msg_cmd) {
		DRM_ERROR("UVD-IBs need a msg command!\n");
		return -EINVAL;
	}
 
	return 0;
}
 
static int radeon_uvd_send_msg(struct radeon_device *rdev,
			       int ring, uint64_t addr,
			       struct radeon_fence **fence)
{
	struct radeon_ib ib;
	int i, r;
 
	r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
	if (r)
		return r;
 
	ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
	ib.ptr[1] = addr;
	ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
	ib.ptr[3] = addr >> 32;
	ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
	ib.ptr[5] = 0;
	for (i = 6; i < 16; ++i)
		ib.ptr[i] = PACKET2(0);
	ib.length_dw = 16;
 
	r = radeon_ib_schedule(rdev, &ib, NULL, false);
 
	if (fence)
		*fence = radeon_fence_ref(ib.fence);
 
	radeon_ib_free(rdev, &ib);
	return r;
}
 
/* multiple fence commands without any stream commands in between can
   crash the vcpu so just try to emmit a dummy create/destroy msg to
   avoid this */
int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
			      uint32_t handle, struct radeon_fence **fence)
{
	/* we use the last page of the vcpu bo for the UVD message */
	uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
		RADEON_GPU_PAGE_SIZE;
 
	uint32_t *msg = rdev->uvd.cpu_addr + offs;
	uint64_t addr = rdev->uvd.gpu_addr + offs;
 
	int r, i;
 
	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
	if (r)
		return r;
 
	/* stitch together an UVD create msg */
	msg[0] = cpu_to_le32(0x00000de4);
	msg[1] = cpu_to_le32(0x00000000);
	msg[2] = cpu_to_le32(handle);
	msg[3] = cpu_to_le32(0x00000000);
	msg[4] = cpu_to_le32(0x00000000);
	msg[5] = cpu_to_le32(0x00000000);
	msg[6] = cpu_to_le32(0x00000000);
	msg[7] = cpu_to_le32(0x00000780);
	msg[8] = cpu_to_le32(0x00000440);
	msg[9] = cpu_to_le32(0x00000000);
	msg[10] = cpu_to_le32(0x01b37000);
	for (i = 11; i < 1024; ++i)
		msg[i] = cpu_to_le32(0x0);
 
	r = radeon_uvd_send_msg(rdev, ring, addr, fence);
	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
	return r;
}
 
int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
			       uint32_t handle, struct radeon_fence **fence)
{
	/* we use the last page of the vcpu bo for the UVD message */
	uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
		RADEON_GPU_PAGE_SIZE;
 
	uint32_t *msg = rdev->uvd.cpu_addr + offs;
	uint64_t addr = rdev->uvd.gpu_addr + offs;
 
	int r, i;
 
	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
	if (r)
		return r;
 
	/* stitch together an UVD destroy msg */
	msg[0] = cpu_to_le32(0x00000de4);
	msg[1] = cpu_to_le32(0x00000002);
	msg[2] = cpu_to_le32(handle);
	msg[3] = cpu_to_le32(0x00000000);
	for (i = 4; i < 1024; ++i)
		msg[i] = cpu_to_le32(0x0);
 
	r = radeon_uvd_send_msg(rdev, ring, addr, fence);
	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
	return r;
}
 
/**
 * radeon_uvd_count_handles - count number of open streams
 *
 * @rdev: radeon_device pointer
 * @sd: number of SD streams
 * @hd: number of HD streams
 *
 * Count the number of open SD/HD streams as a hint for power mangement
 */
static void radeon_uvd_count_handles(struct radeon_device *rdev,
				     unsigned *sd, unsigned *hd)
{
	unsigned i;
 
	*sd = 0;
	*hd = 0;
 
	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
		if (!atomic_read(&rdev->uvd.handles[i]))
			continue;
 
		if (rdev->uvd.img_size[i] >= 720*576)
			++(*hd);
		else
			++(*sd);
	}
}
 
static void radeon_uvd_idle_work_handler(struct work_struct *work)
{
	struct radeon_device *rdev =
		container_of(work, struct radeon_device, uvd.idle_work.work);
 
	if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
		if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
			radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
						 &rdev->pm.dpm.hd);
			radeon_dpm_enable_uvd(rdev, false);
		} else {
			radeon_set_uvd_clocks(rdev, 0, 0);
		}
	} else {
		schedule_delayed_work(&rdev->uvd.idle_work,
				      msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
	}
}
 
void radeon_uvd_note_usage(struct radeon_device *rdev)
{
	bool streams_changed = false;
	bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
	set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
					    msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 
	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
		unsigned hd = 0, sd = 0;
		radeon_uvd_count_handles(rdev, &sd, &hd);
		if ((rdev->pm.dpm.sd != sd) ||
		    (rdev->pm.dpm.hd != hd)) {
			rdev->pm.dpm.sd = sd;
			rdev->pm.dpm.hd = hd;
			/* disable this for now */
			/*streams_changed = true;*/
		}
	}
 
	if (set_clocks || streams_changed) {
		if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
			radeon_dpm_enable_uvd(rdev, true);
		} else {
			radeon_set_uvd_clocks(rdev, 53300, 40000);
		}
	}
}
 
static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
					      unsigned target_freq,
					      unsigned pd_min,
					      unsigned pd_even)
{
	unsigned post_div = vco_freq / target_freq;
 
	/* adjust to post divider minimum value */
	if (post_div < pd_min)
		post_div = pd_min;
 
	/* we alway need a frequency less than or equal the target */
	if ((vco_freq / post_div) > target_freq)
		post_div += 1;
 
	/* post dividers above a certain value must be even */
	if (post_div > pd_even && post_div % 2)
		post_div += 1;
 
	return post_div;
}
 
/**
 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
 *
 * @rdev: radeon_device pointer
 * @vclk: wanted VCLK
 * @dclk: wanted DCLK
 * @vco_min: minimum VCO frequency
 * @vco_max: maximum VCO frequency
 * @fb_factor: factor to multiply vco freq with
 * @fb_mask: limit and bitmask for feedback divider
 * @pd_min: post divider minimum
 * @pd_max: post divider maximum
 * @pd_even: post divider must be even above this value
 * @optimal_fb_div: resulting feedback divider
 * @optimal_vclk_div: resulting vclk post divider
 * @optimal_dclk_div: resulting dclk post divider
 *
 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
 * Returns zero on success -EINVAL on error.
 */
int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
				  unsigned vclk, unsigned dclk,
				  unsigned vco_min, unsigned vco_max,
				  unsigned fb_factor, unsigned fb_mask,
				  unsigned pd_min, unsigned pd_max,
				  unsigned pd_even,
				  unsigned *optimal_fb_div,
				  unsigned *optimal_vclk_div,
				  unsigned *optimal_dclk_div)
{
	unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
 
	/* start off with something large */
	unsigned optimal_score = ~0;
 
	/* loop through vco from low to high */
	vco_min = max(max(vco_min, vclk), dclk);
	for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
 
		uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
		unsigned vclk_div, dclk_div, score;
 
		do_div(fb_div, ref_freq);
 
		/* fb div out of range ? */
		if (fb_div > fb_mask)
			break; /* it can oly get worse */
 
		fb_div &= fb_mask;
 
		/* calc vclk divider with current vco freq */
		vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
							 pd_min, pd_even);
		if (vclk_div > pd_max)
			break; /* vco is too big, it has to stop */
 
		/* calc dclk divider with current vco freq */
		dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
							 pd_min, pd_even);
		if (vclk_div > pd_max)
			break; /* vco is too big, it has to stop */
 
		/* calc score with current vco freq */
		score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
 
		/* determine if this vco setting is better than current optimal settings */
		if (score < optimal_score) {
			*optimal_fb_div = fb_div;
			*optimal_vclk_div = vclk_div;
			*optimal_dclk_div = dclk_div;
			optimal_score = score;
			if (optimal_score == 0)
				break; /* it can't get better than this */
		}
	}
 
	/* did we found a valid setup ? */
	if (optimal_score == ~0)
		return -EINVAL;
 
	return 0;
}
 
int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
				unsigned cg_upll_func_cntl)
{
	unsigned i;
 
	/* make sure UPLL_CTLREQ is deasserted */
	WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 
	mdelay(10);
 
	/* assert UPLL_CTLREQ */
	WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
 
	/* wait for CTLACK and CTLACK2 to get asserted */
	for (i = 0; i < 100; ++i) {
		uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
		if ((RREG32(cg_upll_func_cntl) & mask) == mask)
			break;
		mdelay(10);
	}
 
	/* deassert UPLL_CTLREQ */
	WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 
	if (i == 100) {
		DRM_ERROR("Timeout setting UVD clocks!\n");
		return -ETIMEDOUT;
	}
 
	return 0;
}

Rev 5271	Rev 6104
1	/*	1	/*
2	* Copyright 2011 Advanced Micro Devices, Inc.	2	* Copyright 2011 Advanced Micro Devices, Inc.
3	* All Rights Reserved.	3	* All Rights Reserved.
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the	6	* copy of this software and associated documentation files (the
7	* "Software"), to deal in the Software without restriction, including	7	* "Software"), to deal in the Software without restriction, including
8	* without limitation the rights to use, copy, modify, merge, publish,	8	* without limitation the rights to use, copy, modify, merge, publish,
9	* distribute, sub license, and/or sell copies of the Software, and to	9	* distribute, sub license, and/or sell copies of the Software, and to
10	* permit persons to whom the Software is furnished to do so, subject to	10	* permit persons to whom the Software is furnished to do so, subject to
11	* the following conditions:	11	* the following conditions:
12	*	12	*
13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19	* USE OR OTHER DEALINGS IN THE SOFTWARE.	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
20	*	20	*
21	* The above copyright notice and this permission notice (including the	21	* The above copyright notice and this permission notice (including the
22	* next paragraph) shall be included in all copies or substantial portions	22	* next paragraph) shall be included in all copies or substantial portions
23	* of the Software.	23	* of the Software.
24	*	24	*
25	*/	25	*/
26	/*	26	/*
27	* Authors:	27	* Authors:
28	* Christian König	28	* Christian König
29	*/	29	*/
30		30
31	#include	31	#include
32	#include	32	#include
33	#include	33	#include
34	#include	34	#include
35		35
36	#include "radeon.h"	36	#include "radeon.h"
37	#include "r600d.h"	37	#include "r600d.h"
38		38
39	/* 1 second timeout */	39	/* 1 second timeout */
40	#define UVD_IDLE_TIMEOUT_MS 1000	40	#define UVD_IDLE_TIMEOUT_MS 1000
41		41
42	/* Firmware Names */	42	/* Firmware Names */
-		43	#define FIRMWARE_R600 "radeon/R600_uvd.bin"
-		44	#define FIRMWARE_RS780 "radeon/RS780_uvd.bin"
-		45	#define FIRMWARE_RV770 "radeon/RV770_uvd.bin"
43	#define FIRMWARE_RV710 "radeon/RV710_uvd.bin"	46	#define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
44	#define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"	47	#define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
45	#define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"	48	#define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"
46	#define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"	49	#define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"
47	#define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin"	50	#define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin"
48		51
49	MODULE_FIRMWARE(FIRMWARE_R600);	52	MODULE_FIRMWARE(FIRMWARE_R600);
50	MODULE_FIRMWARE(FIRMWARE_RS780);	53	MODULE_FIRMWARE(FIRMWARE_RS780);
51	MODULE_FIRMWARE(FIRMWARE_RV770);	54	MODULE_FIRMWARE(FIRMWARE_RV770);
52	MODULE_FIRMWARE(FIRMWARE_RV710);	55	MODULE_FIRMWARE(FIRMWARE_RV710);
53	MODULE_FIRMWARE(FIRMWARE_CYPRESS);	56	MODULE_FIRMWARE(FIRMWARE_CYPRESS);
54	MODULE_FIRMWARE(FIRMWARE_SUMO);	57	MODULE_FIRMWARE(FIRMWARE_SUMO);
55	MODULE_FIRMWARE(FIRMWARE_TAHITI);	58	MODULE_FIRMWARE(FIRMWARE_TAHITI);
56	MODULE_FIRMWARE(FIRMWARE_BONAIRE);	59	MODULE_FIRMWARE(FIRMWARE_BONAIRE);
57		60
58	static void radeon_uvd_idle_work_handler(struct work_struct *work);	61	static void radeon_uvd_idle_work_handler(struct work_struct *work);
59		62
60	int radeon_uvd_init(struct radeon_device *rdev)	63	int radeon_uvd_init(struct radeon_device *rdev)
61	{	64	{
62	unsigned long bo_size;	65	unsigned long bo_size;
63	const char *fw_name;	66	const char *fw_name;
64	int i, r;	67	int i, r;
65		68
66	// INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);	69	// INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
67		70
68	switch (rdev->family) {	71	switch (rdev->family) {
-		72	case CHIP_RV610:
-		73	case CHIP_RV630:
-		74	case CHIP_RV670:
-		75	case CHIP_RV620:
-		76	case CHIP_RV635:
-		77	fw_name = FIRMWARE_R600;
-		78	break;
-		79
-		80	case CHIP_RS780:
-		81	case CHIP_RS880:
-		82	fw_name = FIRMWARE_RS780;
-		83	break;
-		84
-		85	case CHIP_RV770:
-		86	fw_name = FIRMWARE_RV770;
-		87	break;
-		88
69	case CHIP_RV710:	89	case CHIP_RV710:
70	case CHIP_RV730:	90	case CHIP_RV730:
71	case CHIP_RV740:	91	case CHIP_RV740:
72	fw_name = FIRMWARE_RV710;	92	fw_name = FIRMWARE_RV710;
73	break;	93	break;
74		94
75	case CHIP_CYPRESS:	95	case CHIP_CYPRESS:
76	case CHIP_HEMLOCK:	96	case CHIP_HEMLOCK:
77	case CHIP_JUNIPER:	97	case CHIP_JUNIPER:
78	case CHIP_REDWOOD:	98	case CHIP_REDWOOD:
79	case CHIP_CEDAR:	99	case CHIP_CEDAR:
80	fw_name = FIRMWARE_CYPRESS;	100	fw_name = FIRMWARE_CYPRESS;
81	break;	101	break;
82		102
83	case CHIP_SUMO:	103	case CHIP_SUMO:
84	case CHIP_SUMO2:	104	case CHIP_SUMO2:
85	case CHIP_PALM:	105	case CHIP_PALM:
86	case CHIP_CAYMAN:	106	case CHIP_CAYMAN:
87	case CHIP_BARTS:	107	case CHIP_BARTS:
88	case CHIP_TURKS:	108	case CHIP_TURKS:
89	case CHIP_CAICOS:	109	case CHIP_CAICOS:
90	fw_name = FIRMWARE_SUMO;	110	fw_name = FIRMWARE_SUMO;
91	break;	111	break;
92		112
93	case CHIP_TAHITI:	113	case CHIP_TAHITI:
94	case CHIP_VERDE:	114	case CHIP_VERDE:
95	case CHIP_PITCAIRN:	115	case CHIP_PITCAIRN:
96	case CHIP_ARUBA:	116	case CHIP_ARUBA:
97	case CHIP_OLAND:	117	case CHIP_OLAND:
98	fw_name = FIRMWARE_TAHITI;	118	fw_name = FIRMWARE_TAHITI;
99	break;	119	break;
100		120
101	case CHIP_BONAIRE:	121	case CHIP_BONAIRE:
102	case CHIP_KABINI:	122	case CHIP_KABINI:
103	case CHIP_KAVERI:	123	case CHIP_KAVERI:
104	case CHIP_HAWAII:	124	case CHIP_HAWAII:
105	case CHIP_MULLINS:	125	case CHIP_MULLINS:
106	fw_name = FIRMWARE_BONAIRE;	126	fw_name = FIRMWARE_BONAIRE;
107	break;	127	break;
108		128
109	default:	129	default:
110	return -EINVAL;	130	return -EINVAL;
111	}	131	}
112		132
113	r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);	133	r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
114	if (r) {	134	if (r) {
115	dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",	135	dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
116	fw_name);	136	fw_name);
117	return r;	137	return r;
118	}	138	}
119		139
120	bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +	140	bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
121	RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +	141	RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
122	RADEON_GPU_PAGE_SIZE;	142	RADEON_GPU_PAGE_SIZE;
123	r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,	143	r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
124	RADEON_GEM_DOMAIN_VRAM, 0, NULL,	144	RADEON_GEM_DOMAIN_VRAM, 0, NULL,
125	NULL, &rdev->uvd.vcpu_bo);	145	NULL, &rdev->uvd.vcpu_bo);
126	if (r) {	146	if (r) {
127	dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);	147	dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
128	return r;	148	return r;
129	}	149	}
130		150
131	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);	151	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
132	if (r) {	152	if (r) {
133	radeon_bo_unref(&rdev->uvd.vcpu_bo);	153	radeon_bo_unref(&rdev->uvd.vcpu_bo);
134	dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);	154	dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
135	return r;	155	return r;
136	}	156	}
137		157
138	r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,	158	r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
139	&rdev->uvd.gpu_addr);	159	&rdev->uvd.gpu_addr);
140	if (r) {	160	if (r) {
141	radeon_bo_unreserve(rdev->uvd.vcpu_bo);	161	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
142	radeon_bo_unref(&rdev->uvd.vcpu_bo);	162	radeon_bo_unref(&rdev->uvd.vcpu_bo);
143	dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);	163	dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
144	return r;	164	return r;
145	}	165	}
146		166
147	r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);	167	r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
148	if (r) {	168	if (r) {
149	dev_err(rdev->dev, "(%d) UVD map failed\n", r);	169	dev_err(rdev->dev, "(%d) UVD map failed\n", r);
150	return r;	170	return r;
151	}	171	}
152		172
153	radeon_bo_unreserve(rdev->uvd.vcpu_bo);	173	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
154		174
155	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {	175	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
156	atomic_set(&rdev->uvd.handles[i], 0);	176	atomic_set(&rdev->uvd.handles[i], 0);
157	rdev->uvd.filp[i] = NULL;	177	rdev->uvd.filp[i] = NULL;
158	rdev->uvd.img_size[i] = 0;	178	rdev->uvd.img_size[i] = 0;
159	}	179	}
160		180
161	return 0;	181	return 0;
162	}	182	}
163		183
164	void radeon_uvd_fini(struct radeon_device *rdev)	184	void radeon_uvd_fini(struct radeon_device *rdev)
165	{	185	{
166	int r;	186	int r;
167		187
168	if (rdev->uvd.vcpu_bo == NULL)	188	if (rdev->uvd.vcpu_bo == NULL)
169	return;	189	return;
170		190
171	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);	191	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
172	if (!r) {	192	if (!r) {
173	radeon_bo_kunmap(rdev->uvd.vcpu_bo);	193	radeon_bo_kunmap(rdev->uvd.vcpu_bo);
174	radeon_bo_unpin(rdev->uvd.vcpu_bo);	194	radeon_bo_unpin(rdev->uvd.vcpu_bo);
175	radeon_bo_unreserve(rdev->uvd.vcpu_bo);	195	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
176	}	196	}
177		197
178	radeon_bo_unref(&rdev->uvd.vcpu_bo);	198	radeon_bo_unref(&rdev->uvd.vcpu_bo);
179		199
180	radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);	200	radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
181		201
182	release_firmware(rdev->uvd_fw);	202	release_firmware(rdev->uvd_fw);
183	}	203	}
184		204
185	int radeon_uvd_suspend(struct radeon_device *rdev)	205	int radeon_uvd_suspend(struct radeon_device *rdev)
186	{	206	{
187	unsigned size;	-
188	void *ptr;	-
189	int i;	207	int i, r;
190		208
191	if (rdev->uvd.vcpu_bo == NULL)	209	if (rdev->uvd.vcpu_bo == NULL)
192	return 0;	210	return 0;
193		211
194	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)	212	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
195	if (atomic_read(&rdev->uvd.handles[i]))	213	uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
-		214	if (handle != 0) {
196	break;	215	struct radeon_fence *fence;
197		-
198	if (i == RADEON_MAX_UVD_HANDLES)	216
-		217	radeon_uvd_note_usage(rdev);
-		218
199	return 0;	219	r = radeon_uvd_get_destroy_msg(rdev,
-		220	R600_RING_TYPE_UVD_INDEX, handle, &fence);
-		221	if (r) {
200		222	DRM_ERROR("Error destroying UVD (%d)!\n", r);
201	size = radeon_bo_size(rdev->uvd.vcpu_bo);	223	continue;
202	size -= rdev->uvd_fw->size;	224	}
203		225
-		226	radeon_fence_wait(fence, false);
-		227	radeon_fence_unref(&fence);
204	ptr = rdev->uvd.cpu_addr;	228
205	ptr += rdev->uvd_fw->size;	229	rdev->uvd.filp[i] = NULL;
206		230	atomic_set(&rdev->uvd.handles[i], 0);
207	rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);	231	}
208	memcpy(rdev->uvd.saved_bo, ptr, size);	232	}
209		233
210	return 0;	234	return 0;
211	}	235	}
212		236
213	int radeon_uvd_resume(struct radeon_device *rdev)	237	int radeon_uvd_resume(struct radeon_device *rdev)
214	{	238	{
215	unsigned size;	239	unsigned size;
216	void *ptr;	240	void *ptr;
217		241
218	if (rdev->uvd.vcpu_bo == NULL)	242	if (rdev->uvd.vcpu_bo == NULL)
219	return -EINVAL;	243	return -EINVAL;
220		244
221	memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);	245	memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
222		246
223	size = radeon_bo_size(rdev->uvd.vcpu_bo);	247	size = radeon_bo_size(rdev->uvd.vcpu_bo);
224	size -= rdev->uvd_fw->size;	248	size -= rdev->uvd_fw->size;
225		249
226	ptr = rdev->uvd.cpu_addr;	250	ptr = rdev->uvd.cpu_addr;
227	ptr += rdev->uvd_fw->size;	251	ptr += rdev->uvd_fw->size;
228		-
229	if (rdev->uvd.saved_bo != NULL) {	-
230	memcpy(ptr, rdev->uvd.saved_bo, size);	-
231	kfree(rdev->uvd.saved_bo);	-
232	rdev->uvd.saved_bo = NULL;	-
233	} else	252
234	memset(ptr, 0, size);	253	memset(ptr, 0, size);
235		254
236	return 0;	255	return 0;
237	}	256	}
238		257
239	void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,	258	void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
240	uint32_t allowed_domains)	259	uint32_t allowed_domains)
241	{	260	{
242	int i;	261	int i;
243		262
244	for (i = 0; i < rbo->placement.num_placement; ++i) {	263	for (i = 0; i < rbo->placement.num_placement; ++i) {
245	rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;	264	rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
246	rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;	265	rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
247	}	266	}
248		267
249	/* If it must be in VRAM it must be in the first segment as well */	268	/* If it must be in VRAM it must be in the first segment as well */
250	if (allowed_domains == RADEON_GEM_DOMAIN_VRAM)	269	if (allowed_domains == RADEON_GEM_DOMAIN_VRAM)
251	return;	270	return;
252		271
253	/* abort if we already have more than one placement */	272	/* abort if we already have more than one placement */
254	if (rbo->placement.num_placement > 1)	273	if (rbo->placement.num_placement > 1)
255	return;	274	return;
256		275
257	/* add another 256MB segment */	276	/* add another 256MB segment */
258	rbo->placements[1] = rbo->placements[0];	277	rbo->placements[1] = rbo->placements[0];
259	rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;	278	rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
260	rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;	279	rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
261	rbo->placement.num_placement++;	280	rbo->placement.num_placement++;
262	rbo->placement.num_busy_placement++;	281	rbo->placement.num_busy_placement++;
263	}	282	}
264		283
265	void radeon_uvd_free_handles(struct radeon_device rdev, struct drm_file filp)	284	void radeon_uvd_free_handles(struct radeon_device rdev, struct drm_file filp)
266	{	285	{
267	int i, r;	286	int i, r;
268	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {	287	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
269	uint32_t handle = atomic_read(&rdev->uvd.handles[i]);	288	uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
270	if (handle != 0 && rdev->uvd.filp[i] == filp) {	289	if (handle != 0 && rdev->uvd.filp[i] == filp) {
271	struct radeon_fence *fence;	290	struct radeon_fence *fence;
272		291
273	radeon_uvd_note_usage(rdev);	292	radeon_uvd_note_usage(rdev);
274		293
275	r = radeon_uvd_get_destroy_msg(rdev,	294	r = radeon_uvd_get_destroy_msg(rdev,
276	R600_RING_TYPE_UVD_INDEX, handle, &fence);	295	R600_RING_TYPE_UVD_INDEX, handle, &fence);
277	if (r) {	296	if (r) {
278	DRM_ERROR("Error destroying UVD (%d)!\n", r);	297	DRM_ERROR("Error destroying UVD (%d)!\n", r);
279	continue;	298	continue;
280	}	299	}
281		300
282	radeon_fence_wait(fence, false);	301	radeon_fence_wait(fence, false);
283	radeon_fence_unref(&fence);	302	radeon_fence_unref(&fence);
284		303
285	rdev->uvd.filp[i] = NULL;	304	rdev->uvd.filp[i] = NULL;
286	atomic_set(&rdev->uvd.handles[i], 0);	305	atomic_set(&rdev->uvd.handles[i], 0);
287	}	306	}
288	}	307	}
289	}	308	}
290		309
291	static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])	310	static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
292	{	311	{
293	unsigned stream_type = msg[4];	312	unsigned stream_type = msg[4];
294	unsigned width = msg[6];	313	unsigned width = msg[6];
295	unsigned height = msg[7];	314	unsigned height = msg[7];
296	unsigned dpb_size = msg[9];	315	unsigned dpb_size = msg[9];
297	unsigned pitch = msg[28];	316	unsigned pitch = msg[28];
298		317
299	unsigned width_in_mb = width / 16;	318	unsigned width_in_mb = width / 16;
300	unsigned height_in_mb = ALIGN(height / 16, 2);	319	unsigned height_in_mb = ALIGN(height / 16, 2);
301		320
302	unsigned image_size, tmp, min_dpb_size;	321	unsigned image_size, tmp, min_dpb_size;
303		322
304	image_size = width * height;	323	image_size = width * height;
305	image_size += image_size / 2;	324	image_size += image_size / 2;
306	image_size = ALIGN(image_size, 1024);	325	image_size = ALIGN(image_size, 1024);
307		326
308	switch (stream_type) {	327	switch (stream_type) {
309	case 0: /* H264 */	328	case 0: /* H264 */
310		329
311	/* reference picture buffer */	330	/* reference picture buffer */
312	min_dpb_size = image_size * 17;	331	min_dpb_size = image_size * 17;
313		332
314	/* macroblock context buffer */	333	/* macroblock context buffer */
315	min_dpb_size += width_in_mb * height_in_mb * 17 * 192;	334	min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
316		335
317	/* IT surface buffer */	336	/* IT surface buffer */
318	min_dpb_size += width_in_mb * height_in_mb * 32;	337	min_dpb_size += width_in_mb * height_in_mb * 32;
319	break;	338	break;
320		339
321	case 1: /* VC1 */	340	case 1: /* VC1 */
322		341
323	/* reference picture buffer */	342	/* reference picture buffer */
324	min_dpb_size = image_size * 3;	343	min_dpb_size = image_size * 3;
325		344
326	/* CONTEXT_BUFFER */	345	/* CONTEXT_BUFFER */
327	min_dpb_size += width_in_mb * height_in_mb * 128;	346	min_dpb_size += width_in_mb * height_in_mb * 128;
328		347
329	/* IT surface buffer */	348	/* IT surface buffer */
330	min_dpb_size += width_in_mb * 64;	349	min_dpb_size += width_in_mb * 64;
331		350
332	/* DB surface buffer */	351	/* DB surface buffer */
333	min_dpb_size += width_in_mb * 128;	352	min_dpb_size += width_in_mb * 128;
334		353
335	/* BP */	354	/* BP */
336	tmp = max(width_in_mb, height_in_mb);	355	tmp = max(width_in_mb, height_in_mb);
337	min_dpb_size += ALIGN(tmp * 7 * 16, 64);	356	min_dpb_size += ALIGN(tmp * 7 * 16, 64);
338	break;	357	break;
339		358
340	case 3: /* MPEG2 */	359	case 3: /* MPEG2 */
341		360
342	/* reference picture buffer */	361	/* reference picture buffer */
343	min_dpb_size = image_size * 3;	362	min_dpb_size = image_size * 3;
344	break;	363	break;
345		364
346	case 4: /* MPEG4 */	365	case 4: /* MPEG4 */
347		366
348	/* reference picture buffer */	367	/* reference picture buffer */
349	min_dpb_size = image_size * 3;	368	min_dpb_size = image_size * 3;
350		369
351	/* CM */	370	/* CM */
352	min_dpb_size += width_in_mb * height_in_mb * 64;	371	min_dpb_size += width_in_mb * height_in_mb * 64;
353		372
354	/* IT surface buffer */	373	/* IT surface buffer */
355	min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);	374	min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
356	break;	375	break;
357		376
358	default:	377	default:
359	DRM_ERROR("UVD codec not handled %d!\n", stream_type);	378	DRM_ERROR("UVD codec not handled %d!\n", stream_type);
360	return -EINVAL;	379	return -EINVAL;
361	}	380	}
362		381
363	if (width > pitch) {	382	if (width > pitch) {
364	DRM_ERROR("Invalid UVD decoding target pitch!\n");	383	DRM_ERROR("Invalid UVD decoding target pitch!\n");
365	return -EINVAL;	384	return -EINVAL;
366	}	385	}
367		386
368	if (dpb_size < min_dpb_size) {	387	if (dpb_size < min_dpb_size) {
369	DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",	388	DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
370	dpb_size, min_dpb_size);	389	dpb_size, min_dpb_size);
371	return -EINVAL;	390	return -EINVAL;
372	}	391	}
373		392
374	buf_sizes[0x1] = dpb_size;	393	buf_sizes[0x1] = dpb_size;
375	buf_sizes[0x2] = image_size;	394	buf_sizes[0x2] = image_size;
376	return 0;	395	return 0;
377	}	396	}
-		397
-		398	static int radeon_uvd_validate_codec(struct radeon_cs_parser *p,
-		399	unsigned stream_type)
-		400	{
-		401	switch (stream_type) {
-		402	case 0: /* H264 */
-		403	case 1: /* VC1 */
-		404	/* always supported */
-		405	return 0;
-		406
-		407	case 3: /* MPEG2 */
-		408	case 4: /* MPEG4 */
-		409	/* only since UVD 3 */
-		410	if (p->rdev->family >= CHIP_PALM)
-		411	return 0;
-		412
-		413	/* fall through */
-		414	default:
-		415	DRM_ERROR("UVD codec not supported by hardware %d!\n",
-		416	stream_type);
-		417	return -EINVAL;
-		418	}
-		419	}
378		420
379	static int radeon_uvd_cs_msg(struct radeon_cs_parser p, struct radeon_bo bo,	421	static int radeon_uvd_cs_msg(struct radeon_cs_parser p, struct radeon_bo bo,
380	unsigned offset, unsigned buf_sizes[])	422	unsigned offset, unsigned buf_sizes[])
381	{	423	{
382	int32_t *msg, msg_type, handle;	424	int32_t *msg, msg_type, handle;
383	unsigned img_size = 0;	425	unsigned img_size = 0;
384	struct fence *f;	426	struct fence *f;
385	void *ptr;	427	void *ptr;
386		428
387	int i, r;	429	int i, r;
388		430
389	if (offset & 0x3F) {	431	if (offset & 0x3F) {
390	DRM_ERROR("UVD messages must be 64 byte aligned!\n");	432	DRM_ERROR("UVD messages must be 64 byte aligned!\n");
391	return -EINVAL;	433	return -EINVAL;
392	}	434	}
393		435
394	f = reservation_object_get_excl(bo->tbo.resv);	436	f = reservation_object_get_excl(bo->tbo.resv);
395	if (f) {	437	if (f) {
396	r = radeon_fence_wait((struct radeon_fence *)f, false);	438	r = radeon_fence_wait((struct radeon_fence *)f, false);
397	if (r) {	439	if (r) {
398	DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);	440	DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
399	return r;	441	return r;
400	}	442	}
401	}	443	}
402		444
403	r = radeon_bo_kmap(bo, &ptr);	445	r = radeon_bo_kmap(bo, &ptr);
404	if (r) {	446	if (r) {
405	DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);	447	DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
406	return r;	448	return r;
407	}	449	}
408		450
409	msg = ptr + offset;	451	msg = ptr + offset;
410		452
411	msg_type = msg[1];	453	msg_type = msg[1];
412	handle = msg[2];	454	handle = msg[2];
413		455
414	if (handle == 0) {	456	if (handle == 0) {
415	DRM_ERROR("Invalid UVD handle!\n");	457	DRM_ERROR("Invalid UVD handle!\n");
416	return -EINVAL;	458	return -EINVAL;
417	}	459	}
418		460
419	if (msg_type == 1) {	-
420	/* it's a decode msg, calc buffer sizes */	-
421	r = radeon_uvd_cs_msg_decode(msg, buf_sizes);	-
422	/* calc image size (width * height) */	-
423	img_size = msg[6] * msg[7];	-
424	radeon_bo_kunmap(bo);	-
425	if (r)	-
426	return r;	-
427		-
428	} else if (msg_type == 2) {	-
429	/* it's a destroy msg, free the handle */	-
430	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)	-
431	atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);	-
432	radeon_bo_kunmap(bo);	-
433	return 0;	461	switch (msg_type) {
434	} else {	462	case 0:
435	/* it's a create msg, calc image size (width * height) */	463	/* it's a create msg, calc image size (width * height) */
-		464	img_size = msg[7] * msg[8];
-		465
436	img_size = msg[7] * msg[8];	466	r = radeon_uvd_validate_codec(p, msg[4]);
-		467	radeon_bo_kunmap(bo);
-		468	if (r)
437	radeon_bo_kunmap(bo);	469	return r;
-		470
-		471	/* try to alloc a new handle */
438		472	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
439	if (msg_type != 0) {	473	if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
440	DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);	474	DRM_ERROR("Handle 0x%x already in use!\n", handle);
441	return -EINVAL;	475	return -EINVAL;
442	}	476	}
443		477
-		478	if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {

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(root)/drivers/video/drm/radeon/radeon_uvd.c – Rev 5271 → 6104