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Rev 3192 Rev 3764
Line 107... Line 107...
107 
	radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
 107 
	radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
108 
	radeon_fence_unref(&ib->fence);
 108 
	radeon_fence_unref(&ib->fence);
109 
}
 109 
}
Line 110... Line 110...
110 
 
 110 
 
- 
 
 111 
/**
- 
 
 112 
 * radeon_ib_sync_to - sync to fence before executing the IB
- 
 
 113 
 *
- 
 
 114 
 * @ib: IB object to add fence to
- 
 
 115 
 * @fence: fence to sync to
- 
 
 116 
 *
- 
 
 117 
 * Sync to the fence before executing the IB
- 
 
 118 
 */
- 
 
 119 
void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence)
- 
 
 120 
{
- 
 
 121 
	struct radeon_fence *other;
- 
 
 122 
 
- 
 
 123 
	if (!fence)
- 
 
 124 
		return;
- 
 
 125 
 
- 
 
 126 
	other = ib->sync_to[fence->ring];
- 
 
 127 
	ib->sync_to[fence->ring] = radeon_fence_later(fence, other);
- 
 
 128 
}
- 
 
 129 
 
111 
/**
 130 
/**
112 
 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
 131 
 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
113 
 *
 132 
 *
114 
 * @rdev: radeon_device pointer
 133 
 * @rdev: radeon_device pointer
115 
 * @ib: IB object to schedule
 134 
 * @ib: IB object to schedule
Line 159... Line 178...
159 
	/* immediately free semaphore when we don't need to sync */
 178 
	/* immediately free semaphore when we don't need to sync */
160 
	if (!need_sync) {
 179 
	if (!need_sync) {
161 
		radeon_semaphore_free(rdev, &ib->semaphore, NULL);
 180 
		radeon_semaphore_free(rdev, &ib->semaphore, NULL);
162 
	}
 181 
	}
163 
	/* if we can't remember our last VM flush then flush now! */
 182 
	/* if we can't remember our last VM flush then flush now! */
- 
 
 183 
	/* XXX figure out why we have to flush for every IB */
164 
	if (ib->vm && !ib->vm->last_flush) {
 184 
	if (ib->vm /*&& !ib->vm->last_flush*/) {
165 
		radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
 185 
		radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
166 
	}
 186 
	}
167 
	if (const_ib) {
 187 
	if (const_ib) {
168 
		radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
 188 
		radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
169 
		radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
 189 
		radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
Line 347... Line 367...
347 
 */
 367 
 */
348 
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
 368 
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
349 
{
 369 
{
350 
	u32 rptr;
 370 
	u32 rptr;
Line 351... Line 371...
351 
 
 371 
 
352 
	if (rdev->wb.enabled)
 372 
	if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX])
353 
		rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
 373 
		rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
354 
	else
 374 
	else
355 
		rptr = RREG32(ring->rptr_reg);
 375 
		rptr = RREG32(ring->rptr_reg);
356 
	ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
 376 
	ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
Line 375... Line 395...
375 
 */
 395 
 */
376 
int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
 396 
int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
377 
{
 397 
{
378 
	int r;
 398 
	int r;
Line -... Line 399...
- 
 
 399 
 
- 
 
 400 
	/* make sure we aren't trying to allocate more space than there is on the ring */
- 
 
 401 
	if (ndw > (ring->ring_size / 4))
379 
 
 402 
		return -ENOMEM;
380 
	/* Align requested size with padding so unlock_commit can
 403 
	/* Align requested size with padding so unlock_commit can
- 
 
 404 
	 * pad safely */
- 
 
 405 
	radeon_ring_free_size(rdev, ring);
- 
 
 406 
	if (ring->ring_free_dw == (ring->ring_size / 4)) {
- 
 
 407 
		/* This is an empty ring update lockup info to avoid
- 
 
 408 
		 * false positive.
- 
 
 409 
		 */
- 
 
 410 
		radeon_ring_lockup_update(ring);
381 
	 * pad safely */
 411 
	}
382 
	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
 412 
	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
383 
	while (ndw > (ring->ring_free_dw - 1)) {
 413 
	while (ndw > (ring->ring_free_dw - 1)) {
384 
		radeon_ring_free_size(rdev, ring);
 414 
		radeon_ring_free_size(rdev, ring);
385 
		if (ndw < ring->ring_free_dw) {
 415 
		if (ndw < ring->ring_free_dw) {
Line 797... Line 827...
797 
		i = (i + 1) & ring->ptr_mask;
 827 
		i = (i + 1) & ring->ptr_mask;
798 
	}
 828 
	}
799 
	return 0;
 829 
	return 0;
800 
}
 830 
}
Line 801... Line 831...
801 
 
 831 
 
802 
static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
 832 
static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
803 
static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
 833 
static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
804 
static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
 834 
static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
805 
static int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX;
 835 
static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
- 
 
 836 
static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
Line 806... Line 837...
806 
static int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
 837 
static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
807 
 
 838 
 
808 
static struct drm_info_list radeon_debugfs_ring_info_list[] = {
 839 
static struct drm_info_list radeon_debugfs_ring_info_list[] = {
809 
	{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
 840 
	{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
810 
	{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
 841 
	{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
811 
	{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
 842 
	{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
- 
 
 843 
	{"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
812 
	{"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index},
 844 
	{"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
Line 813... Line 845...
813 
	{"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index},
 845 
	{"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
814 
};
 846 
};
815 
 
 847