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Rev 2004 Rev 2005
Line 69... Line 69...
69 
		radeon_fence_unref(&fence);
 69 
		radeon_fence_unref(&fence);
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		return -EBUSY;
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		return -EBUSY;
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	}
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	}
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	rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
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	rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
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	nib->free = false;
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	nib->free = false;
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//   if (nib->fence) {
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	if (nib->fence) {
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//       mutex_unlock(&rdev->ib_pool.mutex);
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		mutex_unlock(&rdev->ib_pool.mutex);
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//   r = radeon_fence_wait(nib->fence, false);
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		r = radeon_fence_wait(nib->fence, false);
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//   if (r) {
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		if (r) {
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//           dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
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			dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
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//               nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
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				nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
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//           mutex_lock(&rdev->ib_pool.mutex);
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			mutex_lock(&rdev->ib_pool.mutex);
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//           nib->free = true;
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			nib->free = true;
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//           mutex_unlock(&rdev->ib_pool.mutex);
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			mutex_unlock(&rdev->ib_pool.mutex);
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//           radeon_fence_unref(&fence);
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            radeon_fence_unref(&fence);
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//           return r;
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			return r;
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//       }
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		}
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//       mutex_lock(&rdev->ib_pool.mutex);
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		mutex_lock(&rdev->ib_pool.mutex);
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//   }
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	}
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	radeon_fence_unref(&nib->fence);
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    radeon_fence_unref(&nib->fence);
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	nib->fence = fence;
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	nib->fence = fence;
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	nib->length_dw = 0;
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	nib->length_dw = 0;
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	mutex_unlock(&rdev->ib_pool.mutex);
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	mutex_unlock(&rdev->ib_pool.mutex);
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	*ib = nib;
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	*ib = nib;