WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_ring.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include 
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"
 
int radeon_debugfs_ib_init(struct radeon_device *rdev);
 
/*
 * IB.
 */
 
#if 0
 
int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
{
	struct radeon_fence *fence;
	struct radeon_ib *nib;
 
	int r = 0, i, c;
 
	*ib = NULL;
	r = radeon_fence_create(rdev, &fence);
	if (r) {
		dev_err(rdev->dev, "failed to create fence for new IB\n");
		return r;
	}
    mutex_lock(&rdev->ib_pool.mutex);
	for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
		i &= (RADEON_IB_POOL_SIZE - 1);
 
		if (rdev->ib_pool.ibs[i].free) {
			nib = &rdev->ib_pool.ibs[i];
 
			break;
	}
	}
	if (nib == NULL) {
		/* This should never happen, it means we allocated all
		 * IB and haven't scheduled one yet, return EBUSY to
		 * userspace hoping that on ioctl recall we get better
 
		 * luck
		 */
 
		dev_err(rdev->dev, "no free indirect buffer !\n");
 
 
 
		mutex_unlock(&rdev->ib_pool.mutex);
		radeon_fence_unref(&fence);
		return -EBUSY;
 
	}
	rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
	nib->free = false;
	if (nib->fence) {
		mutex_unlock(&rdev->ib_pool.mutex);
 
	r = radeon_fence_wait(nib->fence, false);
	if (r) {
			dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
				nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
			mutex_lock(&rdev->ib_pool.mutex);
			nib->free = true;
			mutex_unlock(&rdev->ib_pool.mutex);
			radeon_fence_unref(&fence);
			return r;
	}
		mutex_lock(&rdev->ib_pool.mutex);
	}
	radeon_fence_unref(&nib->fence);
 
	nib->fence = fence;
	nib->length_dw = 0;
 
 
 
 
 
	mutex_unlock(&rdev->ib_pool.mutex);
 
	*ib = nib;
 
 
 
 
 
 
	return 0;
}
 
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
{
	struct radeon_ib *tmp = *ib;
 
	*ib = NULL;
	if (tmp == NULL) {
		return;
	}
 
 
 
 
 
 
 
 
	if (!tmp->fence->emited)
		radeon_fence_unref(&tmp->fence);
 
	mutex_lock(&rdev->ib_pool.mutex);
	tmp->free = true;
	mutex_unlock(&rdev->ib_pool.mutex);
}
 
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
{
	int r = 0;
 
	if (!ib->length_dw || !rdev->cp.ready) {
		/* TODO: Nothings in the ib we should report. */
		DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
		return -EINVAL;
	}
 
	/* 64 dwords should be enough for fence too */
	r = radeon_ring_lock(rdev, 64);
	if (r) {
		DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
		return r;
	}
	radeon_ring_ib_execute(rdev, ib);
	radeon_fence_emit(rdev, ib->fence);
	mutex_lock(&rdev->ib_pool.mutex);
	/* once scheduled IB is considered free and protected by the fence */
	ib->free = true;
	mutex_unlock(&rdev->ib_pool.mutex);
	radeon_ring_unlock_commit(rdev);
	return 0;
}
#endif
 
int radeon_ib_pool_init(struct radeon_device *rdev)
{
	void *ptr;
	uint64_t gpu_addr;
	int i;
	int r = 0;
 
	if (rdev->ib_pool.robj)
		return 0;
	/* Allocate 1M object buffer */
 
	r = radeon_bo_create(rdev, NULL,  RADEON_IB_POOL_SIZE*64*1024,
				 true, RADEON_GEM_DOMAIN_GTT,
				&rdev->ib_pool.robj);
	if (r) {
		DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
		return r;
	}
	r = radeon_bo_reserve(rdev->ib_pool.robj, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->ib_pool.robj);
		DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
		return r;
	}
	r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
	radeon_bo_unreserve(rdev->ib_pool.robj);
	if (r) {
		DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
		return r;
	}
	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
		unsigned offset;
 
		offset = i * 64 * 1024;
		rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
		rdev->ib_pool.ibs[i].ptr = ptr + offset;
		rdev->ib_pool.ibs[i].idx = i;
		rdev->ib_pool.ibs[i].length_dw = 0;
		rdev->ib_pool.ibs[i].free = true;
	}
	rdev->ib_pool.head_id = 0;
	rdev->ib_pool.ready = true;
	DRM_INFO("radeon: ib pool ready.\n");
	if (radeon_debugfs_ib_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for IB !\n");
	}
	return r;
}
 
void radeon_ib_pool_fini(struct radeon_device *rdev)
{
	int r;
 
	if (!rdev->ib_pool.ready) {
		return;
	}
	mutex_lock(&rdev->ib_pool.mutex);
 
	if (rdev->ib_pool.robj) {
		r = radeon_bo_reserve(rdev->ib_pool.robj, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(rdev->ib_pool.robj);
			radeon_bo_unpin(rdev->ib_pool.robj);
			radeon_bo_unreserve(rdev->ib_pool.robj);
		}
		radeon_bo_unref(&rdev->ib_pool.robj);
		rdev->ib_pool.robj = NULL;
	}
	mutex_unlock(&rdev->ib_pool.mutex);
}
 
 
/*
 * Ring.
 */
void radeon_ring_free_size(struct radeon_device *rdev)
{
	if (rdev->family >= CHIP_R600)
		rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
	else
	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
	/* This works because ring_size is a power of 2 */
	rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
	rdev->cp.ring_free_dw -= rdev->cp.wptr;
	rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
	if (!rdev->cp.ring_free_dw) {
		rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
	}
}
 
int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
{
	int r;
 
	/* Align requested size with padding so unlock_commit can
	 * pad safely */
	ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
	mutex_lock(&rdev->cp.mutex);
	while (ndw > (rdev->cp.ring_free_dw - 1)) {
		radeon_ring_free_size(rdev);
		if (ndw < rdev->cp.ring_free_dw) {
			break;
		}
//        r = radeon_fence_wait_next(rdev);
//       if (r) {
//           mutex_unlock(&rdev->cp.mutex);
//           return r;
//       }
	}
	rdev->cp.count_dw = ndw;
	rdev->cp.wptr_old = rdev->cp.wptr;
	return 0;
}
 
void radeon_ring_unlock_commit(struct radeon_device *rdev)
{
	unsigned count_dw_pad;
	unsigned i;
 
	/* We pad to match fetch size */
	count_dw_pad = (rdev->cp.align_mask + 1) -
		       (rdev->cp.wptr & rdev->cp.align_mask);
	for (i = 0; i < count_dw_pad; i++) {
		radeon_ring_write(rdev, 2 << 30);
	}
	DRM_MEMORYBARRIER();
	radeon_cp_commit(rdev);
	mutex_unlock(&rdev->cp.mutex);
}
 
void radeon_ring_unlock_undo(struct radeon_device *rdev)
{
	rdev->cp.wptr = rdev->cp.wptr_old;
	mutex_unlock(&rdev->cp.mutex);
}
 
int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
{
	int r;
 
    ENTER();
 
	rdev->cp.ring_size = ring_size;
    /* Allocate ring buffer */
	if (rdev->cp.ring_obj == NULL) {
		r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,
					 RADEON_GEM_DOMAIN_GTT,
					 &rdev->cp.ring_obj);
		if (r) {
			dev_err(rdev->dev, "(%d) ring create failed\n", r);
			return r;
		}
		r = radeon_bo_reserve(rdev->cp.ring_obj, false);
		if (unlikely(r != 0))
			return r;
		r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
				      &rdev->cp.gpu_addr);
		if (r) {
			radeon_bo_unreserve(rdev->cp.ring_obj);
			dev_err(rdev->dev, "(%d) ring pin failed\n", r);
			return r;
		}
		r = radeon_bo_kmap(rdev->cp.ring_obj,
				       (void **)&rdev->cp.ring);
		radeon_bo_unreserve(rdev->cp.ring_obj);
		if (r) {
			dev_err(rdev->dev, "(%d) ring map failed\n", r);
			return r;
		}
	}
	rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
	rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
 
    LEAVE();
 
	return 0;
}
 
void radeon_ring_fini(struct radeon_device *rdev)
{
	int r;
 
	mutex_lock(&rdev->cp.mutex);
   if (rdev->cp.ring_obj) {
		r = radeon_bo_reserve(rdev->cp.ring_obj, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(rdev->cp.ring_obj);
			radeon_bo_unpin(rdev->cp.ring_obj);
			radeon_bo_unreserve(rdev->cp.ring_obj);
		}
		radeon_bo_unref(&rdev->cp.ring_obj);
       rdev->cp.ring = NULL;
		rdev->cp.ring_obj = NULL;
	}
	mutex_unlock(&rdev->cp.mutex);
}
 
 
/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)
static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct radeon_ib *ib = node->info_ent->data;
	unsigned i;
 
	if (ib == NULL) {
		return 0;
	}
	seq_printf(m, "IB %04u\n", ib->idx);
	seq_printf(m, "IB fence %p\n", ib->fence);
	seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
	for (i = 0; i < ib->length_dw; i++) {
		seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
	}
	return 0;
}
 
static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
#endif
 
int radeon_debugfs_ib_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	unsigned i;
 
	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
		sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
		radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
		radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
		radeon_debugfs_ib_list[i].driver_features = 0;
		radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
	}
	return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
					RADEON_IB_POOL_SIZE);
#else
	return 0;
#endif
}

Rev 1404	Rev 1428
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#include	28	#include
29	#include "drmP.h"	29	#include "drmP.h"
30	#include "radeon_drm.h"	30	#include "radeon_drm.h"
31	#include "radeon_reg.h"	31	#include "radeon_reg.h"
32	#include "radeon.h"	32	#include "radeon.h"
33	#include "atom.h"	33	#include "atom.h"
34		34
35	int radeon_debugfs_ib_init(struct radeon_device *rdev);	35	int radeon_debugfs_ib_init(struct radeon_device *rdev);
36		36
37	/*	37	/*
38	* IB.	38	* IB.
39	*/	39	*/
40		40
41	#if 0	41	#if 0
42		42
43	int radeon_ib_get(struct radeon_device rdev, struct radeon_ib *ib)	43	int radeon_ib_get(struct radeon_device rdev, struct radeon_ib *ib)
44	{	44	{
45	struct radeon_fence *fence;	45	struct radeon_fence *fence;
46	struct radeon_ib *nib;	46	struct radeon_ib *nib;
47	unsigned long i;	-
48	int r = 0;	47	int r = 0, i, c;
49		48
50	*ib = NULL;	49	*ib = NULL;
51	r = radeon_fence_create(rdev, &fence);	50	r = radeon_fence_create(rdev, &fence);
52	if (r) {	51	if (r) {
53	DRM_ERROR("failed to create fence for new IB\n");	52	dev_err(rdev->dev, "failed to create fence for new IB\n");
54	return r;	53	return r;
55	}	54	}
56	mutex_lock(&rdev->ib_pool.mutex);	55	mutex_lock(&rdev->ib_pool.mutex);
57	i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);	56	for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
58	if (i < RADEON_IB_POOL_SIZE) {	57	i &= (RADEON_IB_POOL_SIZE - 1);
59	set_bit(i, rdev->ib_pool.alloc_bm);	-
60	rdev->ib_pool.ibs[i].length_dw = 0;	58	if (rdev->ib_pool.ibs[i].free) {
61	*ib = &rdev->ib_pool.ibs[i];	59	nib = &rdev->ib_pool.ibs[i];
62	mutex_unlock(&rdev->ib_pool.mutex);	-
63	goto out;	60	break;
64	}	61	}
-		62	}
65	if (list_empty(&rdev->ib_pool.scheduled_ibs)) {	63	if (nib == NULL) {
66	/* we go do nothings here */	64	/* This should never happen, it means we allocated all
67	mutex_unlock(&rdev->ib_pool.mutex);	65	* IB and haven't scheduled one yet, return EBUSY to
68	DRM_ERROR("all IB allocated none scheduled.\n");	66	* userspace hoping that on ioctl recall we get better
69	r = -EINVAL;	-
70	goto out;	67	* luck
71	}	68	*/
72	/* get the first ib on the scheduled list */	-
73	nib = list_entry(rdev->ib_pool.scheduled_ibs.next,	69	dev_err(rdev->dev, "no free indirect buffer !\n");
74	struct radeon_ib, list);	-
75	if (nib->fence == NULL) {	-
76	/* we go do nothings here */	-
77	mutex_unlock(&rdev->ib_pool.mutex);	70	mutex_unlock(&rdev->ib_pool.mutex);
78	DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx);	71	radeon_fence_unref(&fence);
79	r = -EINVAL;	72	return -EBUSY;
80	goto out;	-
81	}	73	}
-		74	rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
-		75	nib->free = false;
-		76	if (nib->fence) {
82	mutex_unlock(&rdev->ib_pool.mutex);	77	mutex_unlock(&rdev->ib_pool.mutex);
83		-
84	r = radeon_fence_wait(nib->fence, false);	78	r = radeon_fence_wait(nib->fence, false);
85	if (r) {	79	if (r) {
86	DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx,	80	dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
87	(unsigned long)nib->gpu_addr, nib->length_dw);	81	nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
-		82	mutex_lock(&rdev->ib_pool.mutex);
-		83	nib->free = true;
88	DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n");	84	mutex_unlock(&rdev->ib_pool.mutex);
-		85	radeon_fence_unref(&fence);
89	goto out;	86	return r;
-		87	}
-		88	mutex_lock(&rdev->ib_pool.mutex);
90	}	89	}
91	radeon_fence_unref(&nib->fence);	90	radeon_fence_unref(&nib->fence);
92		-
-		91	nib->fence = fence;
93	nib->length_dw = 0;	92	nib->length_dw = 0;
94		-
95	/* scheduled list is accessed here */	-
96	mutex_lock(&rdev->ib_pool.mutex);	-
97	list_del(&nib->list);	-
98	INIT_LIST_HEAD(&nib->list);	-
99	mutex_unlock(&rdev->ib_pool.mutex);	93	mutex_unlock(&rdev->ib_pool.mutex);
100		-
101	*ib = nib;	94	*ib = nib;
102	out:	-
103	if (r) {	-
104	radeon_fence_unref(&fence);	-
105	} else {	-
106	(*ib)->fence = fence;	-
107	}	-
108	return r;	95	return 0;
109	}	96	}
110		97
111	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib *ib)	98	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib *ib)
112	{	99	{
113	struct radeon_ib tmp = ib;	100	struct radeon_ib tmp = ib;
114		101
115	*ib = NULL;	102	*ib = NULL;
116	if (tmp == NULL) {	103	if (tmp == NULL) {
117	return;	104	return;
118	}	105	}
119	mutex_lock(&rdev->ib_pool.mutex);	-
120	if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) {	-
121	/* IB is scheduled & not signaled don't do anythings */	-
122	mutex_unlock(&rdev->ib_pool.mutex);	-
123	return;	-
124	}	-
125	list_del(&tmp->list);	-
126	INIT_LIST_HEAD(&tmp->list);	-
127	if (tmp->fence)	106	if (!tmp->fence->emited)
128	radeon_fence_unref(&tmp->fence);	107	radeon_fence_unref(&tmp->fence);
129		-
130	tmp->length_dw = 0;	108	mutex_lock(&rdev->ib_pool.mutex);
131	clear_bit(tmp->idx, rdev->ib_pool.alloc_bm);	109	tmp->free = true;
132	mutex_unlock(&rdev->ib_pool.mutex);	110	mutex_unlock(&rdev->ib_pool.mutex);
133	}	111	}
134		112
135	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib)	113	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib)
136	{	114	{
137	int r = 0;	115	int r = 0;
138		116
139	if (!ib->length_dw \|\| !rdev->cp.ready) {	117	if (!ib->length_dw \|\| !rdev->cp.ready) {
140	/* TODO: Nothings in the ib we should report. */	118	/* TODO: Nothings in the ib we should report. */
141	DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx);	119	DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
142	return -EINVAL;	120	return -EINVAL;
143	}	121	}
144		122
145	/* 64 dwords should be enough for fence too */	123	/* 64 dwords should be enough for fence too */
146	r = radeon_ring_lock(rdev, 64);	124	r = radeon_ring_lock(rdev, 64);
147	if (r) {	125	if (r) {
148	DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);	126	DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
149	return r;	127	return r;
150	}	128	}
151	radeon_ring_ib_execute(rdev, ib);	129	radeon_ring_ib_execute(rdev, ib);
152	radeon_fence_emit(rdev, ib->fence);	130	radeon_fence_emit(rdev, ib->fence);
153	mutex_lock(&rdev->ib_pool.mutex);	131	mutex_lock(&rdev->ib_pool.mutex);
154	list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);	132	/* once scheduled IB is considered free and protected by the fence */
-		133	ib->free = true;
155	mutex_unlock(&rdev->ib_pool.mutex);	134	mutex_unlock(&rdev->ib_pool.mutex);
156	radeon_ring_unlock_commit(rdev);	135	radeon_ring_unlock_commit(rdev);
157	return 0;	136	return 0;
158	}	137	}
159	#endif	138	#endif
160		139
161	int radeon_ib_pool_init(struct radeon_device *rdev)	140	int radeon_ib_pool_init(struct radeon_device *rdev)
162	{	141	{
163	void *ptr;	142	void *ptr;
164	uint64_t gpu_addr;	143	uint64_t gpu_addr;
165	int i;	144	int i;
166	int r = 0;	145	int r = 0;
167		146
168	if (rdev->ib_pool.robj)	147	if (rdev->ib_pool.robj)
169	return 0;	148	return 0;
170	/* Allocate 1M object buffer */	149	/* Allocate 1M object buffer */
171	INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs);	-
172	r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE641024,	150	r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE641024,
173	true, RADEON_GEM_DOMAIN_GTT,	151	true, RADEON_GEM_DOMAIN_GTT,
174	&rdev->ib_pool.robj);	152	&rdev->ib_pool.robj);
175	if (r) {	153	if (r) {
176	DRM_ERROR("radeon: failed to ib pool (%d).\n", r);	154	DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
177	return r;	155	return r;
178	}	156	}
179	r = radeon_bo_reserve(rdev->ib_pool.robj, false);	157	r = radeon_bo_reserve(rdev->ib_pool.robj, false);
180	if (unlikely(r != 0))	158	if (unlikely(r != 0))
181	return r;	159	return r;
182	r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);	160	r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
183	if (r) {	161	if (r) {
184	radeon_bo_unreserve(rdev->ib_pool.robj);	162	radeon_bo_unreserve(rdev->ib_pool.robj);
185	DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);	163	DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
186	return r;	164	return r;
187	}	165	}
188	r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);	166	r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
189	radeon_bo_unreserve(rdev->ib_pool.robj);	167	radeon_bo_unreserve(rdev->ib_pool.robj);
190	if (r) {	168	if (r) {
191	DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);	169	DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
192	return r;	170	return r;
193	}	171	}
194	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {	172	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
195	unsigned offset;	173	unsigned offset;
196		174
197	offset = i * 64 * 1024;	175	offset = i * 64 * 1024;
198	rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;	176	rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
199	rdev->ib_pool.ibs[i].ptr = ptr + offset;	177	rdev->ib_pool.ibs[i].ptr = ptr + offset;
200	rdev->ib_pool.ibs[i].idx = i;	178	rdev->ib_pool.ibs[i].idx = i;
201	rdev->ib_pool.ibs[i].length_dw = 0;	179	rdev->ib_pool.ibs[i].length_dw = 0;
202	INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list);	180	rdev->ib_pool.ibs[i].free = true;
203	}	181	}
204	bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);	182	rdev->ib_pool.head_id = 0;
205	rdev->ib_pool.ready = true;	183	rdev->ib_pool.ready = true;
206	DRM_INFO("radeon: ib pool ready.\n");	184	DRM_INFO("radeon: ib pool ready.\n");
207	if (radeon_debugfs_ib_init(rdev)) {	185	if (radeon_debugfs_ib_init(rdev)) {
208	DRM_ERROR("Failed to register debugfs file for IB !\n");	186	DRM_ERROR("Failed to register debugfs file for IB !\n");
209	}	187	}
210	return r;	188	return r;
211	}	189	}
212		190
213	void radeon_ib_pool_fini(struct radeon_device *rdev)	191	void radeon_ib_pool_fini(struct radeon_device *rdev)
214	{	192	{
215	int r;	193	int r;
216		194
217	if (!rdev->ib_pool.ready) {	195	if (!rdev->ib_pool.ready) {
218	return;	196	return;
219	}	197	}
220	mutex_lock(&rdev->ib_pool.mutex);	198	mutex_lock(&rdev->ib_pool.mutex);
221	bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);	-
222	if (rdev->ib_pool.robj) {	199	if (rdev->ib_pool.robj) {
223	r = radeon_bo_reserve(rdev->ib_pool.robj, false);	200	r = radeon_bo_reserve(rdev->ib_pool.robj, false);
224	if (likely(r == 0)) {	201	if (likely(r == 0)) {
225	radeon_bo_kunmap(rdev->ib_pool.robj);	202	radeon_bo_kunmap(rdev->ib_pool.robj);
226	radeon_bo_unpin(rdev->ib_pool.robj);	203	radeon_bo_unpin(rdev->ib_pool.robj);
227	radeon_bo_unreserve(rdev->ib_pool.robj);	204	radeon_bo_unreserve(rdev->ib_pool.robj);
228	}	205	}
229	radeon_bo_unref(&rdev->ib_pool.robj);	206	radeon_bo_unref(&rdev->ib_pool.robj);
230	rdev->ib_pool.robj = NULL;	207	rdev->ib_pool.robj = NULL;
231	}	208	}
232	mutex_unlock(&rdev->ib_pool.mutex);	209	mutex_unlock(&rdev->ib_pool.mutex);
233	}	210	}
234		211
235		212
236	/*	213	/*
237	* Ring.	214	* Ring.
238	*/	215	*/
239	void radeon_ring_free_size(struct radeon_device *rdev)	216	void radeon_ring_free_size(struct radeon_device *rdev)
240	{	217	{
241	if (rdev->family >= CHIP_R600)	218	if (rdev->family >= CHIP_R600)
242	rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);	219	rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
243	else	220	else
244	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);	221	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
245	/* This works because ring_size is a power of 2 */	222	/* This works because ring_size is a power of 2 */
246	rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));	223	rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
247	rdev->cp.ring_free_dw -= rdev->cp.wptr;	224	rdev->cp.ring_free_dw -= rdev->cp.wptr;
248	rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;	225	rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
249	if (!rdev->cp.ring_free_dw) {	226	if (!rdev->cp.ring_free_dw) {
250	rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;	227	rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
251	}	228	}
252	}	229	}
253		230
254	int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)	231	int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
255	{	232	{
256	int r;	233	int r;
257		234
258	/* Align requested size with padding so unlock_commit can	235	/* Align requested size with padding so unlock_commit can
259	* pad safely */	236	* pad safely */
260	ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;	237	ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
261	mutex_lock(&rdev->cp.mutex);	238	mutex_lock(&rdev->cp.mutex);
262	while (ndw > (rdev->cp.ring_free_dw - 1)) {	239	while (ndw > (rdev->cp.ring_free_dw - 1)) {
263	radeon_ring_free_size(rdev);	240	radeon_ring_free_size(rdev);
264	if (ndw < rdev->cp.ring_free_dw) {	241	if (ndw < rdev->cp.ring_free_dw) {
265	break;	242	break;
266	}	243	}
267	// r = radeon_fence_wait_next(rdev);	244	// r = radeon_fence_wait_next(rdev);
268	// if (r) {	245	// if (r) {
269	// mutex_unlock(&rdev->cp.mutex);	246	// mutex_unlock(&rdev->cp.mutex);
270	// return r;	247	// return r;
271	// }	248	// }
272	}	249	}
273	rdev->cp.count_dw = ndw;	250	rdev->cp.count_dw = ndw;
274	rdev->cp.wptr_old = rdev->cp.wptr;	251	rdev->cp.wptr_old = rdev->cp.wptr;
275	return 0;	252	return 0;
276	}	253	}
277		254
278	void radeon_ring_unlock_commit(struct radeon_device *rdev)	255	void radeon_ring_unlock_commit(struct radeon_device *rdev)
279	{	256	{
280	unsigned count_dw_pad;	257	unsigned count_dw_pad;
281	unsigned i;	258	unsigned i;
282		259
283	/* We pad to match fetch size */	260	/* We pad to match fetch size */
284	count_dw_pad = (rdev->cp.align_mask + 1) -	261	count_dw_pad = (rdev->cp.align_mask + 1) -
285	(rdev->cp.wptr & rdev->cp.align_mask);	262	(rdev->cp.wptr & rdev->cp.align_mask);
286	for (i = 0; i < count_dw_pad; i++) {	263	for (i = 0; i < count_dw_pad; i++) {
287	radeon_ring_write(rdev, 2 << 30);	264	radeon_ring_write(rdev, 2 << 30);
288	}	265	}
289	DRM_MEMORYBARRIER();	266	DRM_MEMORYBARRIER();
290	radeon_cp_commit(rdev);	267	radeon_cp_commit(rdev);
291	mutex_unlock(&rdev->cp.mutex);	268	mutex_unlock(&rdev->cp.mutex);
292	}	269	}
293		270
294	void radeon_ring_unlock_undo(struct radeon_device *rdev)	271	void radeon_ring_unlock_undo(struct radeon_device *rdev)
295	{	272	{
296	rdev->cp.wptr = rdev->cp.wptr_old;	273	rdev->cp.wptr = rdev->cp.wptr_old;
297	mutex_unlock(&rdev->cp.mutex);	274	mutex_unlock(&rdev->cp.mutex);
298	}	275	}
299		276
300	int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)	277	int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
301	{	278	{
302	int r;	279	int r;
303		280
304	ENTER();	281	ENTER();
305		282
306	rdev->cp.ring_size = ring_size;	283	rdev->cp.ring_size = ring_size;
307	/* Allocate ring buffer */	284	/* Allocate ring buffer */
308	if (rdev->cp.ring_obj == NULL) {	285	if (rdev->cp.ring_obj == NULL) {
309	r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,	286	r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,
310	RADEON_GEM_DOMAIN_GTT,	287	RADEON_GEM_DOMAIN_GTT,
311	&rdev->cp.ring_obj);	288	&rdev->cp.ring_obj);
312	if (r) {	289	if (r) {
313	dev_err(rdev->dev, "(%d) ring create failed\n", r);	290	dev_err(rdev->dev, "(%d) ring create failed\n", r);
314	return r;	291	return r;
315	}	292	}
316	r = radeon_bo_reserve(rdev->cp.ring_obj, false);	293	r = radeon_bo_reserve(rdev->cp.ring_obj, false);
317	if (unlikely(r != 0))	294	if (unlikely(r != 0))
318	return r;	295	return r;
319	r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,	296	r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
320	&rdev->cp.gpu_addr);	297	&rdev->cp.gpu_addr);
321	if (r) {	298	if (r) {
322	radeon_bo_unreserve(rdev->cp.ring_obj);	299	radeon_bo_unreserve(rdev->cp.ring_obj);
323	dev_err(rdev->dev, "(%d) ring pin failed\n", r);	300	dev_err(rdev->dev, "(%d) ring pin failed\n", r);
324	return r;	301	return r;
325	}	302	}
326	r = radeon_bo_kmap(rdev->cp.ring_obj,	303	r = radeon_bo_kmap(rdev->cp.ring_obj,
327	(void **)&rdev->cp.ring);	304	(void **)&rdev->cp.ring);
328	radeon_bo_unreserve(rdev->cp.ring_obj);	305	radeon_bo_unreserve(rdev->cp.ring_obj);
329	if (r) {	306	if (r) {
330	dev_err(rdev->dev, "(%d) ring map failed\n", r);	307	dev_err(rdev->dev, "(%d) ring map failed\n", r);
331	return r;	308	return r;
332	}	309	}
333	}	310	}
334	rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;	311	rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
335	rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;	312	rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
336		313
337	LEAVE();	314	LEAVE();
338		315
339	return 0;	316	return 0;
340	}	317	}
341		318
342	void radeon_ring_fini(struct radeon_device *rdev)	319	void radeon_ring_fini(struct radeon_device *rdev)
343	{	320	{
344	int r;	321	int r;
345		322
346	mutex_lock(&rdev->cp.mutex);	323	mutex_lock(&rdev->cp.mutex);
347	if (rdev->cp.ring_obj) {	324	if (rdev->cp.ring_obj) {
348	r = radeon_bo_reserve(rdev->cp.ring_obj, false);	325	r = radeon_bo_reserve(rdev->cp.ring_obj, false);
349	if (likely(r == 0)) {	326	if (likely(r == 0)) {
350	radeon_bo_kunmap(rdev->cp.ring_obj);	327	radeon_bo_kunmap(rdev->cp.ring_obj);
351	radeon_bo_unpin(rdev->cp.ring_obj);	328	radeon_bo_unpin(rdev->cp.ring_obj);
352	radeon_bo_unreserve(rdev->cp.ring_obj);	329	radeon_bo_unreserve(rdev->cp.ring_obj);
353	}	330	}
354	radeon_bo_unref(&rdev->cp.ring_obj);	331	radeon_bo_unref(&rdev->cp.ring_obj);
355	rdev->cp.ring = NULL;	332	rdev->cp.ring = NULL;
356	rdev->cp.ring_obj = NULL;	333	rdev->cp.ring_obj = NULL;
357	}	334	}
358	mutex_unlock(&rdev->cp.mutex);	335	mutex_unlock(&rdev->cp.mutex);
359	}	336	}
360		337
361		338
362	/*	339	/*
363	* Debugfs info	340	* Debugfs info
364	*/	341	*/
365	#if defined(CONFIG_DEBUG_FS)	342	#if defined(CONFIG_DEBUG_FS)
366	static int radeon_debugfs_ib_info(struct seq_file m, void data)	343	static int radeon_debugfs_ib_info(struct seq_file m, void data)
367	{	344	{
368	struct drm_info_node node = (struct drm_info_node ) m->private;	345	struct drm_info_node node = (struct drm_info_node ) m->private;
369	struct radeon_ib *ib = node->info_ent->data;	346	struct radeon_ib *ib = node->info_ent->data;
370	unsigned i;	347	unsigned i;
371		348
372	if (ib == NULL) {	349	if (ib == NULL) {
373	return 0;	350	return 0;
374	}	351	}
375	seq_printf(m, "IB %04lu\n", ib->idx);	352	seq_printf(m, "IB %04u\n", ib->idx);
376	seq_printf(m, "IB fence %p\n", ib->fence);	353	seq_printf(m, "IB fence %p\n", ib->fence);
377	seq_printf(m, "IB size %05u dwords\n", ib->length_dw);	354	seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
378	for (i = 0; i < ib->length_dw; i++) {	355	for (i = 0; i < ib->length_dw; i++) {
379	seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);	356	seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
380	}	357	}
381	return 0;	358	return 0;
382	}	359	}
383		360
384	static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];	361	static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
385	static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];	362	static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
386	#endif	363	#endif
387		364
388	int radeon_debugfs_ib_init(struct radeon_device *rdev)	365	int radeon_debugfs_ib_init(struct radeon_device *rdev)
389	{	366	{
390	#if defined(CONFIG_DEBUG_FS)	367	#if defined(CONFIG_DEBUG_FS)
391	unsigned i;	368	unsigned i;
392		369
393	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {	370	for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
394	sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);	371	sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
395	radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];	372	radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
396	radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;	373	radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
397	radeon_debugfs_ib_list[i].driver_features = 0;	374	radeon_debugfs_ib_list[i].driver_features = 0;
398	radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];	375	radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
399	}	376	}
400	return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,	377	return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
401	RADEON_IB_POOL_SIZE);	378	RADEON_IB_POOL_SIZE);
402	#else	379	#else
403	return 0;	380	return 0;
404	#endif	381	#endif
405	}	382	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_ring.c – Rev 1404 → 1428