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Rev 6104 Rev 6321
Line 895... Line 895...
895 
	if (ret)
 895 
	if (ret)
896 
		goto done;
 896 
		goto done;
Line 897... Line 897...
897 
 
 897 
 
898 
	/* update display watermarks based on new power state */
 898 
	/* update display watermarks based on new power state */
899 
	radeon_bandwidth_update(rdev);
 - 
 
900 
	/* update displays */
 - 
 
901 
	radeon_dpm_display_configuration_changed(rdev);
 - 
 
902 
 
 - 
 
903 
	rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 - 
 
904 
	rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 - 
 
Line 905... Line 899...
905 
	rdev->pm.dpm.single_display = single_display;
 899 
	radeon_bandwidth_update(rdev);
906 
 
 900 
 
907 
	/* wait for the rings to drain */
 901 
	/* wait for the rings to drain */
908 
	for (i = 0; i < RADEON_NUM_RINGS; i++) {
 902 
	for (i = 0; i < RADEON_NUM_RINGS; i++) {
Line 917... Line 911...
917 
	/* update current power state */
 911 
	/* update current power state */
918 
	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
 912 
	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
Line 919... Line 913...
919 
 
 913 
 
Line -... Line 914...
- 
 
 914 
	radeon_dpm_post_set_power_state(rdev);
- 
 
 915 
 
- 
 
 916 
	/* update displays */
- 
 
 917 
	radeon_dpm_display_configuration_changed(rdev);
- 
 
 918 
 
- 
 
 919 
	rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
- 
 
 920 
	rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
920 
	radeon_dpm_post_set_power_state(rdev);
 921 
	rdev->pm.dpm.single_display = single_display;
921 
 
 922 
 
922 
	if (rdev->asic->dpm.force_performance_level) {
 923 
	if (rdev->asic->dpm.force_performance_level) {
923 
		if (rdev->pm.dpm.thermal_active) {
 924 
		if (rdev->pm.dpm.thermal_active) {
924 
			enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 925 
			enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;