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Rev 2997 Rev 3764
Line 161... Line 161...
161 
		if (sclk > rdev->pm.default_sclk)
 161 
		if (sclk > rdev->pm.default_sclk)
162 
			sclk = rdev->pm.default_sclk;
 162 
			sclk = rdev->pm.default_sclk;
Line 163... Line 163...
163 
 
 163 
 
164 
		/* starting with BTC, there is one state that is used for both
 164 
		/* starting with BTC, there is one state that is used for both
165 
		 * MH and SH.  Difference is that we always use the high clock index for
 165 
		 * MH and SH.  Difference is that we always use the high clock index for
166 
		 * mclk.
 166 
		 * mclk and vddci.
167 
		 */
 167 
		 */
168 
		if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 168 
		if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
169 
		    (rdev->family >= CHIP_BARTS) &&
 169 
		    (rdev->family >= CHIP_BARTS) &&
170 
		    rdev->pm.active_crtc_count &&
 170 
		    rdev->pm.active_crtc_count &&
Line 226... Line 226...
226 
		DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 226 
		DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
227 
}
 227 
}
Line 228... Line 228...
228 
 
 228 
 
229 
static void radeon_pm_set_clocks(struct radeon_device *rdev)
 229 
static void radeon_pm_set_clocks(struct radeon_device *rdev)
230 
{
 230 
{
Line 231... Line 231...
231 
	int i;
 231 
	int i, r;
232 
 
 232 
 
233 
	/* no need to take locks, etc. if nothing's going to change */
 233 
	/* no need to take locks, etc. if nothing's going to change */
234 
	if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 234 
	if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
Line 240... Line 240...
240 
	mutex_lock(&rdev->ring_lock);
 240 
	mutex_lock(&rdev->ring_lock);
Line 241... Line 241...
241 
 
 241 
 
242 
	/* wait for the rings to drain */
 242 
	/* wait for the rings to drain */
243 
	for (i = 0; i < RADEON_NUM_RINGS; i++) {
 243 
	for (i = 0; i < RADEON_NUM_RINGS; i++) {
244 
		struct radeon_ring *ring = &rdev->ring[i];
 244 
		struct radeon_ring *ring = &rdev->ring[i];
- 
 
 245 
		if (!ring->ready) {
- 
 
 246 
			continue;
245 
		if (ring->ready)
 247 
		}
- 
 
 248 
		r = radeon_fence_wait_empty_locked(rdev, i);
- 
 
 249 
		if (r) {
- 
 
 250 
			/* needs a GPU reset dont reset here */
- 
 
 251 
			mutex_unlock(&rdev->ring_lock);
- 
 
 252 
//			up_write(&rdev->pm.mclk_lock);
- 
 
 253 
			mutex_unlock(&rdev->ddev->struct_mutex);
- 
 
 254 
			return;
246 
			radeon_fence_wait_empty_locked(rdev, i);
 255 
		}
Line 247... Line 256...
247 
	}
 256 
	}
Line 248... Line 257...
248 
 
 257 
 
Line 483... Line 492...
483 
	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 492 
	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
484 
	rdev->pm.current_clock_mode_index = 0;
 493 
	rdev->pm.current_clock_mode_index = 0;
485 
	rdev->pm.current_sclk = rdev->pm.default_sclk;
 494 
	rdev->pm.current_sclk = rdev->pm.default_sclk;
486 
	rdev->pm.current_mclk = rdev->pm.default_mclk;
 495 
	rdev->pm.current_mclk = rdev->pm.default_mclk;
487 
	rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 496 
	rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
- 
 
 497 
	rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
488 
	if (rdev->pm.pm_method == PM_METHOD_DYNPM
 498 
	if (rdev->pm.pm_method == PM_METHOD_DYNPM
489 
	    && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 499 
	    && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
490 
		rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 500 
		rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
491 
//		schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 501 
//		schedule_delayed_work(&rdev->pm.dynpm_idle_work,
492 
//					msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 502 
//					msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
Line 670... Line 680...
670 
	struct drm_info_node *node = (struct drm_info_node *) m->private;
 680 
	struct drm_info_node *node = (struct drm_info_node *) m->private;
671 
	struct drm_device *dev = node->minor->dev;
 681 
	struct drm_device *dev = node->minor->dev;
672 
	struct radeon_device *rdev = dev->dev_private;
 682 
	struct radeon_device *rdev = dev->dev_private;
Line 673... Line 683...
673 
 
 683 
 
- 
 
 684 
	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
- 
 
 685 
	/* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
- 
 
 686 
	if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
- 
 
 687 
		seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
674 
	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
 688 
	else
675 
	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 689 
	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
676 
	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
 690 
	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
677 
	if (rdev->asic->get_memory_clock)
 691 
	if (rdev->asic->pm.get_memory_clock)
678 
		seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 692 
		seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
679 
	if (rdev->pm.current_vddc)
 693 
	if (rdev->pm.current_vddc)
680 
		seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
 694 
		seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
681 
	if (rdev->asic->get_pcie_lanes)
 695 
	if (rdev->asic->pm.get_pcie_lanes)
Line 682... Line 696...
682 
		seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 696 
		seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
683 
 
 697