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Rev 1430 | Rev 1963 | ||
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Line 22... | Line 22... | ||
22 | */ |
22 | */ |
23 | #include "drmP.h" |
23 | #include "drmP.h" |
24 | #include "radeon.h" |
24 | #include "radeon.h" |
25 | #include "avivod.h" |
25 | #include "avivod.h" |
Line -... | Line 26... | ||
- | 26 | ||
- | 27 | #define DRM_DEBUG_DRIVER(fmt, args...) |
|
26 | 28 | ||
27 | #define RADEON_IDLE_LOOP_MS 100 |
29 | #define RADEON_IDLE_LOOP_MS 100 |
28 | #define RADEON_RECLOCK_DELAY_MS 200 |
30 | #define RADEON_RECLOCK_DELAY_MS 200 |
- | 31 | #define RADEON_WAIT_VBLANK_TIMEOUT 200 |
|
Line 29... | Line -... | ||
29 | #define RADEON_WAIT_VBLANK_TIMEOUT 200 |
- | |
30 | - | ||
31 | static void radeon_pm_set_clocks_locked(struct radeon_device *rdev); |
- | |
32 | static void radeon_pm_set_clocks(struct radeon_device *rdev); |
- | |
33 | static void radeon_pm_idle_work_handler(struct work_struct *work); |
- | |
34 | static int radeon_debugfs_pm_init(struct radeon_device *rdev); |
- | |
35 | - | ||
36 | static const char *pm_state_names[4] = { |
- | |
37 | "PM_STATE_DISABLED", |
- | |
38 | "PM_STATE_MINIMUM", |
- | |
39 | "PM_STATE_PAUSED", |
- | |
40 | "PM_STATE_ACTIVE" |
- | |
41 | }; |
32 | #define RADEON_WAIT_IDLE_TIMEOUT 200 |
42 | 33 | ||
43 | static const char *pm_state_types[5] = { |
34 | static const char *radeon_pm_state_type_name[5] = { |
44 | "Default", |
35 | "Default", |
45 | "Powersave", |
36 | "Powersave", |
46 | "Battery", |
37 | "Battery", |
47 | "Balanced", |
38 | "Balanced", |
Line -... | Line 39... | ||
- | 39 | "Performance", |
|
- | 40 | }; |
|
- | 41 | ||
- | 42 | static void radeon_dynpm_idle_work_handler(struct work_struct *work); |
|
48 | "Performance", |
43 | static int radeon_debugfs_pm_init(struct radeon_device *rdev); |
- | 44 | static bool radeon_pm_in_vbl(struct radeon_device *rdev); |
|
- | 45 | static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); |
|
- | 46 | static void radeon_pm_update_profile(struct radeon_device *rdev); |
|
- | 47 | static void radeon_pm_set_clocks(struct radeon_device *rdev); |
|
- | 48 | ||
- | 49 | static inline int power_supply_is_system_supplied(void) { return -ENOSYS; } |
|
- | 50 | ||
- | 51 | #define ACPI_AC_CLASS "ac_adapter" |
|
- | 52 | ||
- | 53 | #ifdef CONFIG_ACPI |
|
49 | }; |
54 | static int radeon_acpi_event(struct notifier_block *nb, |
50 | 55 | unsigned long val, |
|
51 | static void radeon_print_power_mode_info(struct radeon_device *rdev) |
56 | void *data) |
Line 52... | Line -... | ||
52 | { |
- | |
53 | int i, j; |
57 | { |
54 | bool is_default; |
- | |
55 | - | ||
56 | DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states); |
- | |
57 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
- | |
58 | if (rdev->pm.default_power_state == &rdev->pm.power_state[i]) |
- | |
59 | is_default = true; |
- | |
60 | else |
58 | struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb); |
61 | is_default = false; |
- | |
62 | DRM_INFO("State %d %s %s\n", i, |
- | |
63 | pm_state_types[rdev->pm.power_state[i].type], |
- | |
64 | is_default ? "(default)" : ""); |
- | |
65 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) |
- | |
66 | DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes); |
59 | struct acpi_bus_event *entry = (struct acpi_bus_event *)data; |
67 | DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes); |
- | |
68 | for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) { |
- | |
69 | if (rdev->flags & RADEON_IS_IGP) |
60 | |
70 | DRM_INFO("\t\t%d engine: %d\n", |
61 | if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) { |
71 | j, |
62 | if (power_supply_is_system_supplied() > 0) |
72 | rdev->pm.power_state[i].clock_info[j].sclk * 10); |
63 | DRM_DEBUG_DRIVER("pm: AC\n"); |
73 | else |
64 | else |
- | 65 | DRM_DEBUG_DRIVER("pm: DC\n"); |
|
- | 66 | ||
- | 67 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
|
- | 68 | if (rdev->pm.profile == PM_PROFILE_AUTO) { |
|
74 | DRM_INFO("\t\t%d engine/memory: %d/%d\n", |
69 | mutex_lock(&rdev->pm.mutex); |
75 | j, |
70 | radeon_pm_update_profile(rdev); |
76 | rdev->pm.power_state[i].clock_info[j].sclk * 10, |
71 | radeon_pm_set_clocks(rdev); |
Line 77... | Line -... | ||
77 | rdev->pm.power_state[i].clock_info[j].mclk * 10); |
- | |
78 | } |
72 | mutex_unlock(&rdev->pm.mutex); |
79 | } |
73 | } |
80 | } |
74 | } |
81 | - | ||
82 | static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev, |
- | |
Line -... | Line 75... | ||
- | 75 | } |
|
- | 76 | ||
83 | enum radeon_pm_state_type type) |
77 | return NOTIFY_OK; |
84 | { |
78 | } |
- | 79 | #endif |
|
85 | int i, j; |
80 | |
86 | enum radeon_pm_state_type wanted_types[2]; |
- | |
87 | int wanted_count; |
81 | static void radeon_pm_update_profile(struct radeon_device *rdev) |
88 | 82 | { |
|
89 | switch (type) { |
83 | switch (rdev->pm.profile) { |
90 | case POWER_STATE_TYPE_DEFAULT: |
84 | case PM_PROFILE_DEFAULT: |
91 | default: |
85 | rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; |
- | 86 | break; |
|
92 | return rdev->pm.default_power_state; |
87 | case PM_PROFILE_AUTO: |
- | 88 | if (power_supply_is_system_supplied() > 0) { |
|
93 | case POWER_STATE_TYPE_POWERSAVE: |
89 | if (rdev->pm.active_crtc_count > 1) |
94 | if (rdev->flags & RADEON_IS_MOBILITY) { |
90 | rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; |
- | 91 | else |
|
95 | wanted_types[0] = POWER_STATE_TYPE_POWERSAVE; |
92 | rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; |
96 | wanted_types[1] = POWER_STATE_TYPE_BATTERY; |
93 | } else { |
97 | wanted_count = 2; |
94 | if (rdev->pm.active_crtc_count > 1) |
98 | } else { |
95 | rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; |
99 | wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE; |
96 | else |
- | 97 | rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; |
|
100 | wanted_count = 1; |
98 | } |
101 | } |
- | |
102 | break; |
99 | break; |
103 | case POWER_STATE_TYPE_BATTERY: |
100 | case PM_PROFILE_LOW: |
104 | if (rdev->flags & RADEON_IS_MOBILITY) { |
101 | if (rdev->pm.active_crtc_count > 1) |
- | 102 | rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; |
|
105 | wanted_types[0] = POWER_STATE_TYPE_BATTERY; |
103 | else |
- | 104 | rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; |
|
106 | wanted_types[1] = POWER_STATE_TYPE_POWERSAVE; |
105 | break; |
107 | wanted_count = 2; |
106 | case PM_PROFILE_MID: |
108 | } else { |
107 | if (rdev->pm.active_crtc_count > 1) |
109 | wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE; |
108 | rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; |
110 | wanted_count = 1; |
109 | else |
- | 110 | rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; |
|
111 | } |
111 | break; |
112 | break; |
112 | case PM_PROFILE_HIGH: |
Line 113... | Line 113... | ||
113 | case POWER_STATE_TYPE_BALANCED: |
113 | if (rdev->pm.active_crtc_count > 1) |
114 | case POWER_STATE_TYPE_PERFORMANCE: |
114 | rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; |
115 | wanted_types[0] = type; |
115 | else |
- | 116 | rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; |
|
- | 117 | break; |
|
- | 118 | } |
|
116 | wanted_count = 1; |
119 | |
- | 120 | if (rdev->pm.active_crtc_count == 0) { |
|
- | 121 | rdev->pm.requested_power_state_index = |
|
- | 122 | rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; |
|
117 | break; |
123 | rdev->pm.requested_clock_mode_index = |
118 | } |
124 | rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; |
Line -... | Line 125... | ||
- | 125 | } else { |
|
- | 126 | rdev->pm.requested_power_state_index = |
|
- | 127 | rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; |
|
- | 128 | rdev->pm.requested_clock_mode_index = |
|
119 | 129 | rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; |
|
- | 130 | } |
|
- | 131 | } |
|
120 | for (i = 0; i < wanted_count; i++) { |
132 | |
Line -... | Line 133... | ||
- | 133 | static void radeon_unmap_vram_bos(struct radeon_device *rdev) |
|
121 | for (j = 0; j < rdev->pm.num_power_states; j++) { |
134 | { |
122 | if (rdev->pm.power_state[j].type == wanted_types[i]) |
- | |
123 | return &rdev->pm.power_state[j]; |
- | |
124 | } |
135 | struct radeon_bo *bo, *n; |
- | 136 | ||
- | 137 | if (list_empty(&rdev->gem.objects)) |
|
- | 138 | return; |
|
- | 139 | ||
- | 140 | } |
|
- | 141 | ||
- | 142 | ||
- | 143 | static void radeon_set_power_state(struct radeon_device *rdev) |
|
- | 144 | { |
|
- | 145 | u32 sclk, mclk; |
|
- | 146 | bool misc_after = false; |
|
- | 147 | ||
- | 148 | if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && |
|
- | 149 | (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) |
|
- | 150 | return; |
|
- | 151 | ||
- | 152 | if (radeon_gui_idle(rdev)) { |
|
- | 153 | sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
|
- | 154 | clock_info[rdev->pm.requested_clock_mode_index].sclk; |
|
- | 155 | if (sclk > rdev->pm.default_sclk) |
|
125 | } |
156 | sclk = rdev->pm.default_sclk; |
- | 157 | ||
- | 158 | mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
|
- | 159 | clock_info[rdev->pm.requested_clock_mode_index].mclk; |
|
- | 160 | if (mclk > rdev->pm.default_mclk) |
|
126 | 161 | mclk = rdev->pm.default_mclk; |
|
- | 162 | ||
- | 163 | /* upvolt before raising clocks, downvolt after lowering clocks */ |
|
- | 164 | if (sclk < rdev->pm.current_sclk) |
|
- | 165 | misc_after = true; |
|
- | 166 | ||
- | 167 | // radeon_sync_with_vblank(rdev); |
|
- | 168 | ||
- | 169 | if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
|
- | 170 | if (!radeon_pm_in_vbl(rdev)) |
|
- | 171 | return; |
|
- | 172 | } |
|
- | 173 | ||
- | 174 | radeon_pm_prepare(rdev); |
|
- | 175 | ||
- | 176 | if (!misc_after) |
|
- | 177 | /* voltage, pcie lanes, etc.*/ |
|
- | 178 | radeon_pm_misc(rdev); |
|
- | 179 | ||
- | 180 | /* set engine clock */ |
|
- | 181 | if (sclk != rdev->pm.current_sclk) { |
|
- | 182 | radeon_pm_debug_check_in_vbl(rdev, false); |
|
- | 183 | radeon_set_engine_clock(rdev, sclk); |
|
- | 184 | radeon_pm_debug_check_in_vbl(rdev, true); |
|
- | 185 | rdev->pm.current_sclk = sclk; |
|
- | 186 | DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); |
|
- | 187 | } |
|
- | 188 | ||
- | 189 | /* set memory clock */ |
|
- | 190 | if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) { |
|
- | 191 | radeon_pm_debug_check_in_vbl(rdev, false); |
|
- | 192 | radeon_set_memory_clock(rdev, mclk); |
|
- | 193 | radeon_pm_debug_check_in_vbl(rdev, true); |
|
- | 194 | rdev->pm.current_mclk = mclk; |
|
- | 195 | DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); |
|
- | 196 | } |
|
- | 197 | ||
- | 198 | if (misc_after) |
|
- | 199 | /* voltage, pcie lanes, etc.*/ |
|
- | 200 | radeon_pm_misc(rdev); |
|
- | 201 | ||
- | 202 | radeon_pm_finish(rdev); |
|
- | 203 | ||
- | 204 | rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; |
|
- | 205 | rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; |
|
- | 206 | } else |
|
- | 207 | DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); |
|
127 | return rdev->pm.default_power_state; |
208 | } |
- | 209 | ||
128 | } |
210 | static void radeon_pm_set_clocks(struct radeon_device *rdev) |
- | 211 | { |
|
- | 212 | int i; |
|
- | 213 | ||
- | 214 | /* no need to take locks, etc. if nothing's going to change */ |
|
- | 215 | if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && |
|
- | 216 | (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) |
|
- | 217 | return; |
|
- | 218 | ||
- | 219 | mutex_lock(&rdev->ddev->struct_mutex); |
|
- | 220 | mutex_lock(&rdev->vram_mutex); |
|
- | 221 | mutex_lock(&rdev->cp.mutex); |
|
- | 222 | ||
- | 223 | /* gui idle int has issues on older chips it seems */ |
|
- | 224 | if (rdev->family >= CHIP_R600) { |
|
- | 225 | if (rdev->irq.installed) { |
|
- | 226 | /* wait for GPU idle */ |
|
- | 227 | rdev->pm.gui_idle = false; |
|
- | 228 | rdev->irq.gui_idle = true; |
|
- | 229 | } |
|
- | 230 | } else { |
|
- | 231 | if (rdev->cp.ready) { |
|
129 | 232 | // struct radeon_fence *fence; |
|
- | 233 | // radeon_ring_alloc(rdev, 64); |
|
- | 234 | // radeon_fence_create(rdev, &fence); |
|
- | 235 | // radeon_fence_emit(rdev, fence); |
|
- | 236 | // radeon_ring_commit(rdev); |
|
- | 237 | // radeon_fence_wait(fence, false); |
|
- | 238 | // radeon_fence_unref(&fence); |
|
- | 239 | } |
|
- | 240 | } |
|
- | 241 | radeon_unmap_vram_bos(rdev); |
|
- | 242 | ||
- | 243 | if (rdev->irq.installed) { |
|
- | 244 | for (i = 0; i < rdev->num_crtc; i++) { |
|
- | 245 | if (rdev->pm.active_crtcs & (1 << i)) { |
|
- | 246 | rdev->pm.req_vblank |= (1 << i); |
|
- | 247 | // drm_vblank_get(rdev->ddev, i); |
|
- | 248 | } |
|
- | 249 | } |
|
- | 250 | } |
|
- | 251 | ||
- | 252 | radeon_set_power_state(rdev); |
|
- | 253 | ||
- | 254 | if (rdev->irq.installed) { |
|
- | 255 | for (i = 0; i < rdev->num_crtc; i++) { |
|
- | 256 | if (rdev->pm.req_vblank & (1 << i)) { |
|
- | 257 | rdev->pm.req_vblank &= ~(1 << i); |
|
- | 258 | // drm_vblank_put(rdev->ddev, i); |
|
- | 259 | } |
|
- | 260 | } |
|
- | 261 | } |
|
- | 262 | ||
- | 263 | /* update display watermarks based on new power state */ |
|
- | 264 | radeon_update_bandwidth_info(rdev); |
|
- | 265 | if (rdev->pm.active_crtc_count) |
|
- | 266 | radeon_bandwidth_update(rdev); |
|
- | 267 | ||
- | 268 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
|
130 | static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev, |
269 | |
- | 270 | mutex_unlock(&rdev->cp.mutex); |
|
- | 271 | mutex_unlock(&rdev->vram_mutex); |
|
- | 272 | mutex_unlock(&rdev->ddev->struct_mutex); |
|
- | 273 | } |
|
- | 274 | ||
- | 275 | static void radeon_pm_print_states(struct radeon_device *rdev) |
|
- | 276 | { |
|
- | 277 | int i, j; |
|
131 | struct radeon_power_state *power_state, |
278 | struct radeon_power_state *power_state; |
- | 279 | struct radeon_pm_clock_info *clock_info; |
|
- | 280 | ||
- | 281 | DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); |
|
- | 282 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
|
- | 283 | power_state = &rdev->pm.power_state[i]; |
|
132 | enum radeon_pm_clock_mode_type type) |
284 | DRM_DEBUG_DRIVER("State %d: %s\n", i, |
133 | { |
285 | radeon_pm_state_type_name[power_state->type]); |
- | 286 | if (i == rdev->pm.default_power_state_index) |
|
- | 287 | DRM_DEBUG_DRIVER("\tDefault"); |
|
- | 288 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) |
|
- | 289 | DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); |
|
- | 290 | if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
|
134 | switch (type) { |
291 | DRM_DEBUG_DRIVER("\tSingle display only\n"); |
- | 292 | DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); |
|
- | 293 | for (j = 0; j < power_state->num_clock_modes; j++) { |
|
- | 294 | clock_info = &(power_state->clock_info[j]); |
|
135 | case POWER_MODE_TYPE_DEFAULT: |
295 | if (rdev->flags & RADEON_IS_IGP) |
- | 296 | DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n", |
|
- | 297 | j, |
|
136 | default: |
298 | clock_info->sclk * 10, |
- | 299 | clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : ""); |
|
- | 300 | else |
|
- | 301 | DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n", |
|
- | 302 | j, |
|
- | 303 | clock_info->sclk * 10, |
|
- | 304 | clock_info->mclk * 10, |
|
- | 305 | clock_info->voltage.voltage, |
|
- | 306 | clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : ""); |
|
- | 307 | } |
|
- | 308 | } |
|
- | 309 | } |
|
- | 310 | ||
- | 311 | static ssize_t radeon_get_pm_profile(struct device *dev, |
|
137 | return power_state->default_clock_mode; |
312 | struct device_attribute *attr, |
- | 313 | char *buf) |
|
- | 314 | { |
|
138 | case POWER_MODE_TYPE_LOW: |
315 | |
- | 316 | return snprintf(buf, PAGE_SIZE, "%s\n", "default"); |
|
- | 317 | } |
|
- | 318 | ||
- | 319 | static ssize_t radeon_set_pm_profile(struct device *dev, |
|
- | 320 | struct device_attribute *attr, |
|
- | 321 | const char *buf, |
|
- | 322 | size_t count) |
|
- | 323 | { |
|
- | 324 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); |
|
- | 325 | struct radeon_device *rdev = ddev->dev_private; |
|
- | 326 | ||
- | 327 | mutex_lock(&rdev->pm.mutex); |
|
139 | return &power_state->clock_info[0]; |
328 | |
Line -... | Line 329... | ||
- | 329 | rdev->pm.profile = PM_PROFILE_DEFAULT; |
|
- | 330 | ||
- | 331 | radeon_pm_update_profile(rdev); |
|
- | 332 | radeon_pm_set_clocks(rdev); |
|
- | 333 | fail: |
|
- | 334 | mutex_unlock(&rdev->pm.mutex); |
|
- | 335 | ||
- | 336 | return count; |
|
- | 337 | } |
|
- | 338 | ||
- | 339 | static ssize_t radeon_get_pm_method(struct device *dev, |
|
- | 340 | struct device_attribute *attr, |
|
- | 341 | char *buf) |
|
- | 342 | { |
|
- | 343 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); |
|
- | 344 | struct radeon_device *rdev = ddev->dev_private; |
|
- | 345 | int pm = rdev->pm.pm_method; |
|
- | 346 | ||
- | 347 | return snprintf(buf, PAGE_SIZE, "%s\n", |
|
- | 348 | (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile"); |
|
- | 349 | } |
|
- | 350 | ||
- | 351 | static ssize_t radeon_set_pm_method(struct device *dev, |
|
- | 352 | struct device_attribute *attr, |
|
- | 353 | const char *buf, |
|
- | 354 | size_t count) |
|
- | 355 | { |
|
- | 356 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); |
|
- | 357 | struct radeon_device *rdev = ddev->dev_private; |
|
- | 358 | ||
- | 359 | ||
- | 360 | if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { |
|
- | 361 | mutex_lock(&rdev->pm.mutex); |
|
- | 362 | rdev->pm.pm_method = PM_METHOD_DYNPM; |
|
- | 363 | rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; |
|
- | 364 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; |
|
- | 365 | mutex_unlock(&rdev->pm.mutex); |
|
- | 366 | } else if (strncmp("profile", buf, strlen("profile")) == 0) { |
|
- | 367 | mutex_lock(&rdev->pm.mutex); |
|
- | 368 | /* disable dynpm */ |
|
- | 369 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; |
|
- | 370 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
|
140 | case POWER_MODE_TYPE_MID: |
371 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
Line 141... | Line 372... | ||
141 | if (power_state->num_clock_modes > 2) |
372 | mutex_unlock(&rdev->pm.mutex); |
142 | return &power_state->clock_info[1]; |
373 | // cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); |
- | 374 | } else { |
|
143 | else |
375 | DRM_ERROR("invalid power method!\n"); |
- | 376 | goto fail; |
|
- | 377 | } |
|
- | 378 | radeon_pm_compute_clocks(rdev); |
|
- | 379 | fail: |
|
144 | return &power_state->clock_info[0]; |
380 | return count; |
145 | break; |
381 | } |
146 | case POWER_MODE_TYPE_HIGH: |
- | |
147 | return &power_state->clock_info[power_state->num_clock_modes - 1]; |
382 | |
148 | } |
- | |
149 | 383 | static ssize_t radeon_hwmon_show_temp(struct device *dev, |
|
150 | } |
384 | struct device_attribute *attr, |
151 | - | ||
152 | static void radeon_get_power_state(struct radeon_device *rdev, |
385 | char *buf) |
153 | enum radeon_pm_action action) |
- | |
154 | { |
386 | { |
155 | switch (action) { |
387 | struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); |
156 | case PM_ACTION_MINIMUM: |
388 | struct radeon_device *rdev = ddev->dev_private; |
157 | rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY); |
389 | u32 temp; |
158 | rdev->pm.requested_clock_mode = |
- | |
159 | radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW); |
390 | |
160 | break; |
- | |
161 | case PM_ACTION_DOWNCLOCK: |
391 | switch (rdev->pm.int_thermal_type) { |
162 | rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE); |
392 | case THERMAL_TYPE_RV6XX: |
163 | rdev->pm.requested_clock_mode = |
393 | temp = rv6xx_get_temp(rdev); |
164 | radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID); |
394 | break; |
- | 395 | case THERMAL_TYPE_RV770: |
|
165 | break; |
396 | temp = rv770_get_temp(rdev); |
166 | case PM_ACTION_UPCLOCK: |
- | |
167 | rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT); |
- | |
168 | rdev->pm.requested_clock_mode = |
- | |
169 | radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH); |
397 | break; |
Line 170... | Line 398... | ||
170 | break; |
398 | case THERMAL_TYPE_EVERGREEN: |
- | 399 | case THERMAL_TYPE_NI: |
|
- | 400 | temp = evergreen_get_temp(rdev); |
|
171 | case PM_ACTION_NONE: |
401 | break; |
172 | default: |
402 | default: |
173 | DRM_ERROR("Requested mode for not defined action\n"); |
- | |
174 | return; |
403 | temp = 0; |
Line 175... | Line -... | ||
175 | } |
- | |
176 | DRM_INFO("Requested: e: %d m: %d p: %d\n", |
- | |
177 | rdev->pm.requested_clock_mode->sclk, |
- | |
178 | rdev->pm.requested_clock_mode->mclk, |
404 | break; |
- | 405 | } |
|
179 | rdev->pm.requested_power_state->non_clock_info.pcie_lanes); |
406 | |
- | 407 | return snprintf(buf, PAGE_SIZE, "%d\n", temp); |
|
180 | } |
408 | } |
- | 409 | ||
181 | 410 | static ssize_t radeon_hwmon_show_name(struct device *dev, |
|
- | 411 | struct device_attribute *attr, |
|
- | 412 | char *buf) |
|
182 | static void radeon_set_power_state(struct radeon_device *rdev) |
413 | { |
183 | { |
- | |
- | 414 | return sprintf(buf, "radeon\n"); |
|
- | 415 | } |
|
Line -... | Line 416... | ||
- | 416 | ||
- | 417 | static int radeon_hwmon_init(struct radeon_device *rdev) |
|
- | 418 | { |
|
- | 419 | int err = 0; |
|
- | 420 | ||
- | 421 | rdev->pm.int_hwmon_dev = NULL; |
|
- | 422 | ||
- | 423 | return err; |
|
- | 424 | } |
|
- | 425 | ||
- | 426 | static void radeon_hwmon_fini(struct radeon_device *rdev) |
|
- | 427 | { |
|
- | 428 | } |
|
- | 429 | ||
- | 430 | void radeon_pm_suspend(struct radeon_device *rdev) |
|
- | 431 | { |
|
184 | /* if *_clock_mode are the same, *_power_state are as well */ |
432 | mutex_lock(&rdev->pm.mutex); |
- | 433 | if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
|
- | 434 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) |
|
185 | if (rdev->pm.requested_clock_mode == rdev->pm.current_clock_mode) |
435 | rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; |
- | 436 | } |
|
- | 437 | mutex_unlock(&rdev->pm.mutex); |
|
- | 438 | ||
- | 439 | // cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); |
|
- | 440 | } |
|
- | 441 | ||
- | 442 | void radeon_pm_resume(struct radeon_device *rdev) |
|
- | 443 | { |
|
- | 444 | /* asic init will reset the default power state */ |
|
186 | return; |
445 | mutex_lock(&rdev->pm.mutex); |
Line 187... | Line 446... | ||
187 | 446 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
|
188 | DRM_INFO("Setting: e: %d m: %d p: %d\n", |
447 | rdev->pm.current_clock_mode_index = 0; |
- | 448 | rdev->pm.current_sclk = rdev->pm.default_sclk; |
|
- | 449 | rdev->pm.current_mclk = rdev->pm.default_mclk; |
|
- | 450 | rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; |
|
- | 451 | if (rdev->pm.pm_method == PM_METHOD_DYNPM |
|
- | 452 | && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { |
|
189 | rdev->pm.requested_clock_mode->sclk, |
453 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; |
190 | rdev->pm.requested_clock_mode->mclk, |
454 | // schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
- | 455 | // msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); |
|
191 | rdev->pm.requested_power_state->non_clock_info.pcie_lanes); |
456 | } |
- | 457 | mutex_unlock(&rdev->pm.mutex); |
|
- | 458 | radeon_pm_compute_clocks(rdev); |
|
- | 459 | } |
|
- | 460 | ||
- | 461 | int radeon_pm_init(struct radeon_device *rdev) |
|
Line 192... | Line 462... | ||
192 | /* set pcie lanes */ |
462 | { |
193 | /* set voltage */ |
463 | int ret; |
194 | /* set engine clock */ |
464 | |
195 | radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk); |
465 | /* default to profile method */ |
196 | /* set memory clock */ |
466 | rdev->pm.pm_method = PM_METHOD_PROFILE; |
- | 467 | rdev->pm.profile = PM_PROFILE_DEFAULT; |
|
197 | 468 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; |
|
198 | rdev->pm.current_power_state = rdev->pm.requested_power_state; |
469 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
Line -... | Line 470... | ||
- | 470 | rdev->pm.dynpm_can_upclock = true; |
|
199 | rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode; |
471 | rdev->pm.dynpm_can_downclock = true; |
- | 472 | rdev->pm.default_sclk = rdev->clock.default_sclk; |
|
- | 473 | rdev->pm.default_mclk = rdev->clock.default_mclk; |
|
- | 474 | rdev->pm.current_sclk = rdev->clock.default_sclk; |
|
- | 475 | rdev->pm.current_mclk = rdev->clock.default_mclk; |
|
- | 476 | rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; |
|
200 | } |
477 | |
201 | 478 | if (rdev->bios) { |
|
Line 202... | Line 479... | ||
202 | int radeon_pm_init(struct radeon_device *rdev) |
479 | if (rdev->is_atom_bios) |
- | 480 | radeon_atombios_get_power_modes(rdev); |
|
Line 203... | Line 481... | ||
203 | { |
481 | else |
- | 482 | radeon_combios_get_power_modes(rdev); |
|
- | 483 | radeon_pm_print_states(rdev); |
|
- | 484 | radeon_pm_init_profile(rdev); |
|
- | 485 | } |
|
- | 486 | ||
- | 487 | /* set up the internal thermal sensor if applicable */ |
|
- | 488 | ret = radeon_hwmon_init(rdev); |
|
- | 489 | if (ret) |
|
- | 490 | return ret; |
|
204 | rdev->pm.state = PM_STATE_DISABLED; |
491 | |
205 | rdev->pm.planned_action = PM_ACTION_NONE; |
492 | if (rdev->pm.num_power_states > 1) { |
- | 493 | ||
206 | rdev->pm.downclocked = false; |
494 | DRM_INFO("radeon: power management initialized\n"); |
- | 495 | } |
|
Line 207... | Line 496... | ||
207 | 496 | ||
Line 208... | Line 497... | ||
208 | if (rdev->bios) { |
497 | return 0; |
- | 498 | } |
|
- | 499 | ||
209 | if (rdev->is_atom_bios) |
500 | void radeon_pm_fini(struct radeon_device *rdev) |
Line 210... | Line 501... | ||
210 | radeon_atombios_get_power_modes(rdev); |
501 | { |
211 | else |
502 | if (rdev->pm.num_power_states > 1) { |
212 | radeon_combios_get_power_modes(rdev); |
503 | mutex_lock(&rdev->pm.mutex); |
213 | radeon_print_power_mode_info(rdev); |
504 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
214 | } |
505 | rdev->pm.profile = PM_PROFILE_DEFAULT; |
215 | - | ||
Line 216... | Line 506... | ||
216 | if (radeon_debugfs_pm_init(rdev)) { |
506 | radeon_pm_update_profile(rdev); |
217 | DRM_ERROR("Failed to register debugfs file for PM!\n"); |
507 | radeon_pm_set_clocks(rdev); |
Line 218... | Line 508... | ||
218 | } |
508 | } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
Line 219... | Line 509... | ||
219 | 509 | /* reset default clocks */ |
|
- | 510 | rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; |
|
220 | // INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler); |
511 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; |
221 | 512 | radeon_pm_set_clocks(rdev); |
|
222 | if (radeon_dynpm != -1 && radeon_dynpm) { |
513 | } |
223 | rdev->pm.state = PM_STATE_PAUSED; |
- | |
224 | DRM_INFO("radeon: dynamic power management enabled\n"); |
514 | mutex_unlock(&rdev->pm.mutex); |
225 | } |
515 | |
226 | 516 | // cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); |
|
227 | DRM_INFO("radeon: power management initialized\n"); |
517 | |
228 | 518 | } |
|
Line -... | Line 519... | ||
- | 519 | ||
- | 520 | radeon_hwmon_fini(rdev); |
|
- | 521 | } |
|
- | 522 | ||
- | 523 | void radeon_pm_compute_clocks(struct radeon_device *rdev) |
|
229 | return 0; |
524 | { |
230 | } |
525 | struct drm_device *ddev = rdev->ddev; |
- | 526 | struct drm_crtc *crtc; |
|
231 | 527 | struct radeon_crtc *radeon_crtc; |
|
232 | void radeon_pm_compute_clocks(struct radeon_device *rdev) |
528 | |
233 | { |
529 | if (rdev->pm.num_power_states < 2) |
234 | struct drm_device *ddev = rdev->ddev; |
530 | return; |
235 | struct drm_connector *connector; |
531 | |
Line 236... | Line 532... | ||
236 | struct radeon_crtc *radeon_crtc; |
532 | mutex_lock(&rdev->pm.mutex); |
237 | int count = 0; |
533 | |
238 | 534 | rdev->pm.active_crtcs = 0; |
|
239 | if (rdev->pm.state == PM_STATE_DISABLED) |
535 | rdev->pm.active_crtc_count = 0; |
Line 240... | Line 536... | ||
240 | return; |
536 | list_for_each_entry(crtc, |
241 | 537 | &ddev->mode_config.crtc_list, head) { |
|
242 | mutex_lock(&rdev->pm.mutex); |
538 | radeon_crtc = to_radeon_crtc(crtc); |
- | 539 | if (radeon_crtc->enabled) { |
|
- | 540 | rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); |
|
- | 541 | rdev->pm.active_crtc_count++; |
|
- | 542 | } |
|
- | 543 | } |
|
- | 544 | ||
- | 545 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
|
- | 546 | radeon_pm_update_profile(rdev); |
|
- | 547 | radeon_pm_set_clocks(rdev); |
|
- | 548 | } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
|
- | 549 | if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { |
|
- | 550 | if (rdev->pm.active_crtc_count > 1) { |
|
- | 551 | if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { |
|
- | 552 | // cancel_delayed_work(&rdev->pm.dynpm_idle_work); |
|
- | 553 | ||
- | 554 | rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; |
|
- | 555 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; |
|
- | 556 | radeon_pm_get_dynpm_state(rdev); |
|
243 | 557 | radeon_pm_set_clocks(rdev); |
|
244 | rdev->pm.active_crtcs = 0; |
- | |
245 | list_for_each_entry(connector, |
- | |
246 | &ddev->mode_config.connector_list, head) { |
- | |
247 | if (connector->encoder && |
- | |
248 | connector->dpms != DRM_MODE_DPMS_OFF) { |
558 | |
249 | radeon_crtc = to_radeon_crtc(connector->encoder->crtc); |
559 | DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); |
250 | rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); |
- | |
251 | ++count; |
- | |
252 | } |
- | |
253 | } |
- | |
254 | - | ||
255 | if (count > 1) { |
560 | } |
256 | if (rdev->pm.state == PM_STATE_ACTIVE) { |
561 | } else if (rdev->pm.active_crtc_count == 1) { |
Line 257... | Line 562... | ||
257 | 562 | /* TODO: Increase clocks if needed for current mode */ |
|
258 | rdev->pm.state = PM_STATE_PAUSED; |
563 | |
Line 259... | Line 564... | ||
259 | rdev->pm.planned_action = PM_ACTION_UPCLOCK; |
564 | if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { |
260 | if (rdev->pm.downclocked) |
565 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; |
261 | radeon_pm_set_clocks(rdev); |
566 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; |
262 | 567 | radeon_pm_get_dynpm_state(rdev); |
|
Line 263... | Line -... | ||
263 | DRM_DEBUG("radeon: dynamic power management deactivated\n"); |
- | |
264 | } |
568 | radeon_pm_set_clocks(rdev); |
265 | } else if (count == 1) { |
- | |
266 | /* TODO: Increase clocks if needed for current mode */ |
- | |
267 | 569 | ||
268 | if (rdev->pm.state == PM_STATE_MINIMUM) { |
570 | // schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
- | 571 | // msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); |
|
269 | rdev->pm.state = PM_STATE_ACTIVE; |
572 | } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { |
- | 573 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; |
|
270 | rdev->pm.planned_action = PM_ACTION_UPCLOCK; |
574 | // schedule_delayed_work(&rdev->pm.dynpm_idle_work, |
271 | radeon_pm_set_clocks(rdev); |
575 | // msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); |
272 | } |
576 | DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); |
273 | else if (rdev->pm.state == PM_STATE_PAUSED) { |
577 | } |
274 | rdev->pm.state = PM_STATE_ACTIVE; |
578 | } else { /* count == 0 */ |
275 | DRM_DEBUG("radeon: dynamic power management activated\n"); |
- | |
276 | } |
- | |
277 | } |
- | |
278 | else { /* count == 0 */ |
- | |
279 | if (rdev->pm.state != PM_STATE_MINIMUM) { |
- | |
280 | rdev->pm.state = PM_STATE_MINIMUM; |
- | |
281 | rdev->pm.planned_action = PM_ACTION_MINIMUM; |
- | |
282 | radeon_pm_set_clocks(rdev); |
- | |
283 | } |
- | |
284 | } |
- | |
285 | - | ||
286 | mutex_unlock(&rdev->pm.mutex); |
- | |
287 | } |
- | |
288 | - | ||
289 | static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) |
- | |
290 | { |
- | |
291 | u32 stat_crtc1 = 0, stat_crtc2 = 0; |
- | |
292 | bool in_vbl = true; |
- | |
293 | - | ||
294 | if (ASIC_IS_AVIVO(rdev)) { |
- | |
295 | if (rdev->pm.active_crtcs & (1 << 0)) { |
- | |
Line 296... | Line 579... | ||
296 | stat_crtc1 = RREG32(D1CRTC_STATUS); |
579 | if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { |
297 | if (!(stat_crtc1 & 1)) |
- | |
298 | in_vbl = false; |
- | |
299 | } |
- | |
300 | if (rdev->pm.active_crtcs & (1 << 1)) { |
- | |
301 | stat_crtc2 = RREG32(D2CRTC_STATUS); |
- | |
302 | if (!(stat_crtc2 & 1)) |
- | |
303 | in_vbl = false; |
- | |
304 | } |
- | |
305 | } |
- | |
306 | if (in_vbl == false) |
- | |
307 | DRM_INFO("not in vbl for pm change %08x %08x at %s\n", stat_crtc1, |
- | |
308 | stat_crtc2, finish ? "exit" : "entry"); |
- | |
309 | return in_vbl; |
- | |
310 | } |
- | |
311 | static void radeon_pm_set_clocks_locked(struct radeon_device *rdev) |
- | |
312 | { |
- | |
313 | /*radeon_fence_wait_last(rdev);*/ |
- | |
314 | switch (rdev->pm.planned_action) { |
- | |
315 | case PM_ACTION_UPCLOCK: |
- | |
316 | rdev->pm.downclocked = false; |
- | |
317 | break; |
- | |
318 | case PM_ACTION_DOWNCLOCK: |
- | |
319 | rdev->pm.downclocked = true; |
- | |
320 | break; |
- | |
321 | case PM_ACTION_MINIMUM: |
- | |
322 | break; |
- | |
323 | case PM_ACTION_NONE: |
- | |
324 | DRM_ERROR("%s: PM_ACTION_NONE\n", __func__); |
- | |
325 | break; |
- | |
326 | } |
- | |
327 | - | ||
328 | /* check if we are in vblank */ |
- | |
329 | radeon_pm_debug_check_in_vbl(rdev, false); |
- | |
330 | radeon_set_power_state(rdev); |
- | |
331 | radeon_pm_debug_check_in_vbl(rdev, true); |
580 | // cancel_delayed_work(&rdev->pm.dynpm_idle_work); |
Line 332... | Line -... | ||
332 | rdev->pm.planned_action = PM_ACTION_NONE; |
- | |
333 | } |
581 | |
334 | 582 | rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; |
|
335 | static void radeon_pm_set_clocks(struct radeon_device *rdev) |
583 | rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; |
336 | { |
584 | radeon_pm_get_dynpm_state(rdev); |
337 | radeon_get_power_state(rdev, rdev->pm.planned_action); |
- | |
Line 338... | Line -... | ||
338 | mutex_lock(&rdev->cp.mutex); |
- | |
339 | - | ||
340 | if (rdev->pm.active_crtcs & (1 << 0)) { |
585 | radeon_pm_set_clocks(rdev); |
341 | rdev->pm.req_vblank |= (1 << 0); |
- | |
342 | // drm_vblank_get(rdev->ddev, 0); |
- | |
343 | } |
- | |
344 | if (rdev->pm.active_crtcs & (1 << 1)) { |
- | |
345 | rdev->pm.req_vblank |= (1 << 1); |
- | |
346 | // drm_vblank_get(rdev->ddev, 1); |
- | |
347 | } |
586 | } |
348 | if (rdev->pm.active_crtcs) |
587 | } |
349 | // wait_event_interruptible_timeout( |
588 | } |
350 | // rdev->irq.vblank_queue, 0, |
- | |
351 | // msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); |
- | |
352 | if (rdev->pm.req_vblank & (1 << 0)) { |
- | |
353 | rdev->pm.req_vblank &= ~(1 << 0); |
- | |
354 | // drm_vblank_put(rdev->ddev, 0); |
- | |
355 | } |
- | |
356 | if (rdev->pm.req_vblank & (1 << 1)) { |
- | |
357 | rdev->pm.req_vblank &= ~(1 << 1); |
- | |
358 | // drm_vblank_put(rdev->ddev, 1); |
- | |
359 | } |
- | |
360 | - | ||
361 | radeon_pm_set_clocks_locked(rdev); |
- | |
362 | mutex_unlock(&rdev->cp.mutex); |
- | |
363 | } |
- | |
364 | - | ||
365 | #if 0 |
- | |
366 | static void radeon_pm_idle_work_handler(struct work_struct *work) |
- | |
367 | { |
- | |
368 | struct radeon_device *rdev; |
- | |
369 | rdev = container_of(work, struct radeon_device, |
- | |
370 | pm.idle_work.work); |
- | |
371 | - | ||
372 | mutex_lock(&rdev->pm.mutex); |
- | |
373 | if (rdev->pm.state == PM_STATE_ACTIVE) { |
- | |
374 | unsigned long irq_flags; |
- | |
375 | int not_processed = 0; |
- | |
376 | - | ||
377 | read_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
- | |
378 | if (!list_empty(&rdev->fence_drv.emited)) { |
- | |
379 | struct list_head *ptr; |
- | |
380 | list_for_each(ptr, &rdev->fence_drv.emited) { |
589 | } |
381 | /* count up to 3, that's enought info */ |
- | |
Line 382... | Line -... | ||
382 | if (++not_processed >= 3) |
- | |
383 | break; |
- | |
384 | } |
- | |
385 | } |
- | |
Line 386... | Line 590... | ||
386 | read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
590 | |
387 | 591 | mutex_unlock(&rdev->pm.mutex); |
|
388 | if (not_processed >= 3) { /* should upclock */ |
592 | } |
389 | if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) { |
593 | |
Line 428... | Line 632... | ||
428 | { |
632 | { |
429 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
633 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
430 | struct drm_device *dev = node->minor->dev; |
634 | struct drm_device *dev = node->minor->dev; |
431 | struct radeon_device *rdev = dev->dev_private; |
635 | struct radeon_device *rdev = dev->dev_private; |
Line 432... | Line -... | ||
432 | - | ||
433 | seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]); |
636 | |
434 | seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk); |
637 | seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); |
435 | seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); |
638 | seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); |
436 | seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk); |
639 | seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); |
437 | if (rdev->asic->get_memory_clock) |
640 | if (rdev->asic->get_memory_clock) |
- | 641 | seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); |
|
- | 642 | if (rdev->pm.current_vddc) |
|
438 | seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); |
643 | seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); |
439 | if (rdev->asic->get_pcie_lanes) |
644 | if (rdev->asic->get_pcie_lanes) |
Line 440... | Line 645... | ||
440 | seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); |
645 | seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); |
441 | 646 |