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Rev 1404 Rev 1430
Line 177... Line 177...
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    bo->tbo.offset = bo->tbo.vm_node->start << PAGE_SHIFT;
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    bo->tbo.offset = bo->tbo.vm_node->start << PAGE_SHIFT;
Line 178... Line 178...
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    if(bo->domain & RADEON_GEM_DOMAIN_VRAM)
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    if(bo->domain & RADEON_GEM_DOMAIN_VRAM)
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    {
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    {
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        bo->tbo.offset += (u64)bo->rdev->mc.vram_location;
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        bo->tbo.offset += (u64)bo->rdev->mc.vram_start;
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    }
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    }
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    else if (bo->domain & RADEON_GEM_DOMAIN_GTT)
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    else if (bo->domain & RADEON_GEM_DOMAIN_GTT)
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    {
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    {
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        u32_t *pagelist;
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        u32_t *pagelist;
Line 189... Line 189...
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        pagelist =  &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12];
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        pagelist =  &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12];
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        dbgprintf("pagelist %x\n", pagelist);
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        dbgprintf("pagelist %x\n", pagelist);
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        radeon_gart_bind(bo->rdev, bo->tbo.offset,
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        radeon_gart_bind(bo->rdev, bo->tbo.offset,
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                         bo->tbo.vm_node->size,  pagelist);
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                         bo->tbo.vm_node->size,  pagelist);
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        bo->tbo.offset += (u64)bo->rdev->mc.gtt_location;
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        bo->tbo.offset += (u64)bo->rdev->mc.gtt_start;
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    }
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    }
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    else
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    else
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    {
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    {
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        DRM_ERROR("Unknown placement %x\n", bo->domain);
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        DRM_ERROR("Unknown placement %x\n", bo->domain);
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        bo->tbo.offset = -1;
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        bo->tbo.offset = -1;
Line 376... Line 376...
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    vm_node->mm = NULL;
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    vm_node->mm = NULL;
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Line 378... Line 378...
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    bo->tbo.vm_node = vm_node;
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    bo->tbo.vm_node = vm_node;
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    bo->tbo.offset  = bo->tbo.vm_node->start << PAGE_SHIFT;
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    bo->tbo.offset  = bo->tbo.vm_node->start << PAGE_SHIFT;
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    bo->tbo.offset += (u64)bo->rdev->mc.vram_location;
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    bo->tbo.offset += (u64)bo->rdev->mc.vram_start;
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    bo->kptr        = (void*)0xFE000000;
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    bo->kptr        = (void*)0xFE000000;
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    bo->pin_count   = 1;
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    bo->pin_count   = 1;
Line 383... Line 383...
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