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1 | /* |
1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
3 | * VA Linux Systems Inc., Fremont, California. |
3 | * VA Linux Systems Inc., Fremont, California. |
4 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2008 Red Hat Inc. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Original Authors: |
24 | * Original Authors: |
25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
26 | * |
26 | * |
27 | * Kernel port Author: Dave Airlie |
27 | * Kernel port Author: Dave Airlie |
28 | */ |
28 | */ |
29 | 29 | ||
30 | #ifndef RADEON_MODE_H |
30 | #ifndef RADEON_MODE_H |
31 | #define RADEON_MODE_H |
31 | #define RADEON_MODE_H |
32 | 32 | ||
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include |
36 | #include |
37 | #include |
37 | #include |
38 | #include |
38 | #include |
39 | #include |
39 | #include |
40 | 40 | ||
41 | struct radeon_bo; |
41 | struct radeon_bo; |
42 | struct radeon_device; |
42 | struct radeon_device; |
43 | 43 | ||
44 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
44 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
45 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
45 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
48 | 48 | ||
49 | #define RADEON_MAX_HPD_PINS 7 |
49 | #define RADEON_MAX_HPD_PINS 7 |
50 | #define RADEON_MAX_CRTCS 6 |
50 | #define RADEON_MAX_CRTCS 6 |
51 | #define RADEON_MAX_AFMT_BLOCKS 7 |
51 | #define RADEON_MAX_AFMT_BLOCKS 7 |
52 | 52 | ||
53 | enum radeon_rmx_type { |
53 | enum radeon_rmx_type { |
54 | RMX_OFF, |
54 | RMX_OFF, |
55 | RMX_FULL, |
55 | RMX_FULL, |
56 | RMX_CENTER, |
56 | RMX_CENTER, |
57 | RMX_ASPECT |
57 | RMX_ASPECT |
58 | }; |
58 | }; |
59 | 59 | ||
60 | enum radeon_tv_std { |
60 | enum radeon_tv_std { |
61 | TV_STD_NTSC, |
61 | TV_STD_NTSC, |
62 | TV_STD_PAL, |
62 | TV_STD_PAL, |
63 | TV_STD_PAL_M, |
63 | TV_STD_PAL_M, |
64 | TV_STD_PAL_60, |
64 | TV_STD_PAL_60, |
65 | TV_STD_NTSC_J, |
65 | TV_STD_NTSC_J, |
66 | TV_STD_SCART_PAL, |
66 | TV_STD_SCART_PAL, |
67 | TV_STD_SECAM, |
67 | TV_STD_SECAM, |
68 | TV_STD_PAL_CN, |
68 | TV_STD_PAL_CN, |
69 | TV_STD_PAL_N, |
69 | TV_STD_PAL_N, |
70 | }; |
70 | }; |
71 | 71 | ||
72 | enum radeon_underscan_type { |
72 | enum radeon_underscan_type { |
73 | UNDERSCAN_OFF, |
73 | UNDERSCAN_OFF, |
74 | UNDERSCAN_ON, |
74 | UNDERSCAN_ON, |
75 | UNDERSCAN_AUTO, |
75 | UNDERSCAN_AUTO, |
76 | }; |
76 | }; |
77 | 77 | ||
78 | enum radeon_hpd_id { |
78 | enum radeon_hpd_id { |
79 | RADEON_HPD_1 = 0, |
79 | RADEON_HPD_1 = 0, |
80 | RADEON_HPD_2, |
80 | RADEON_HPD_2, |
81 | RADEON_HPD_3, |
81 | RADEON_HPD_3, |
82 | RADEON_HPD_4, |
82 | RADEON_HPD_4, |
83 | RADEON_HPD_5, |
83 | RADEON_HPD_5, |
84 | RADEON_HPD_6, |
84 | RADEON_HPD_6, |
85 | RADEON_HPD_NONE = 0xff, |
85 | RADEON_HPD_NONE = 0xff, |
86 | }; |
86 | }; |
87 | 87 | ||
88 | #define RADEON_MAX_I2C_BUS 16 |
88 | #define RADEON_MAX_I2C_BUS 16 |
89 | 89 | ||
90 | /* radeon gpio-based i2c |
90 | /* radeon gpio-based i2c |
91 | * 1. "mask" reg and bits |
91 | * 1. "mask" reg and bits |
92 | * grabs the gpio pins for software use |
92 | * grabs the gpio pins for software use |
93 | * 0=not held 1=held |
93 | * 0=not held 1=held |
94 | * 2. "a" reg and bits |
94 | * 2. "a" reg and bits |
95 | * output pin value |
95 | * output pin value |
96 | * 0=low 1=high |
96 | * 0=low 1=high |
97 | * 3. "en" reg and bits |
97 | * 3. "en" reg and bits |
98 | * sets the pin direction |
98 | * sets the pin direction |
99 | * 0=input 1=output |
99 | * 0=input 1=output |
100 | * 4. "y" reg and bits |
100 | * 4. "y" reg and bits |
101 | * input pin value |
101 | * input pin value |
102 | * 0=low 1=high |
102 | * 0=low 1=high |
103 | */ |
103 | */ |
104 | struct radeon_i2c_bus_rec { |
104 | struct radeon_i2c_bus_rec { |
105 | bool valid; |
105 | bool valid; |
106 | /* id used by atom */ |
106 | /* id used by atom */ |
107 | uint8_t i2c_id; |
107 | uint8_t i2c_id; |
108 | /* id used by atom */ |
108 | /* id used by atom */ |
109 | enum radeon_hpd_id hpd; |
109 | enum radeon_hpd_id hpd; |
110 | /* can be used with hw i2c engine */ |
110 | /* can be used with hw i2c engine */ |
111 | bool hw_capable; |
111 | bool hw_capable; |
112 | /* uses multi-media i2c engine */ |
112 | /* uses multi-media i2c engine */ |
113 | bool mm_i2c; |
113 | bool mm_i2c; |
114 | /* regs and bits */ |
114 | /* regs and bits */ |
115 | uint32_t mask_clk_reg; |
115 | uint32_t mask_clk_reg; |
116 | uint32_t mask_data_reg; |
116 | uint32_t mask_data_reg; |
117 | uint32_t a_clk_reg; |
117 | uint32_t a_clk_reg; |
118 | uint32_t a_data_reg; |
118 | uint32_t a_data_reg; |
119 | uint32_t en_clk_reg; |
119 | uint32_t en_clk_reg; |
120 | uint32_t en_data_reg; |
120 | uint32_t en_data_reg; |
121 | uint32_t y_clk_reg; |
121 | uint32_t y_clk_reg; |
122 | uint32_t y_data_reg; |
122 | uint32_t y_data_reg; |
123 | uint32_t mask_clk_mask; |
123 | uint32_t mask_clk_mask; |
124 | uint32_t mask_data_mask; |
124 | uint32_t mask_data_mask; |
125 | uint32_t a_clk_mask; |
125 | uint32_t a_clk_mask; |
126 | uint32_t a_data_mask; |
126 | uint32_t a_data_mask; |
127 | uint32_t en_clk_mask; |
127 | uint32_t en_clk_mask; |
128 | uint32_t en_data_mask; |
128 | uint32_t en_data_mask; |
129 | uint32_t y_clk_mask; |
129 | uint32_t y_clk_mask; |
130 | uint32_t y_data_mask; |
130 | uint32_t y_data_mask; |
131 | }; |
131 | }; |
132 | 132 | ||
133 | struct radeon_tmds_pll { |
133 | struct radeon_tmds_pll { |
134 | uint32_t freq; |
134 | uint32_t freq; |
135 | uint32_t value; |
135 | uint32_t value; |
136 | }; |
136 | }; |
137 | 137 | ||
138 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
138 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
139 | 139 | ||
140 | /* pll flags */ |
140 | /* pll flags */ |
141 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
141 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
142 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
142 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
143 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
143 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
144 | #define RADEON_PLL_LEGACY (1 << 3) |
144 | #define RADEON_PLL_LEGACY (1 << 3) |
145 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
145 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
146 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
146 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
147 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
147 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
148 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
148 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
149 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
149 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
150 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
150 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
151 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
151 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
152 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
152 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
153 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
153 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
154 | #define RADEON_PLL_IS_LCD (1 << 13) |
154 | #define RADEON_PLL_IS_LCD (1 << 13) |
155 | #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
155 | #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
156 | 156 | ||
157 | struct radeon_pll { |
157 | struct radeon_pll { |
158 | /* reference frequency */ |
158 | /* reference frequency */ |
159 | uint32_t reference_freq; |
159 | uint32_t reference_freq; |
160 | 160 | ||
161 | /* fixed dividers */ |
161 | /* fixed dividers */ |
162 | uint32_t reference_div; |
162 | uint32_t reference_div; |
163 | uint32_t post_div; |
163 | uint32_t post_div; |
164 | 164 | ||
165 | /* pll in/out limits */ |
165 | /* pll in/out limits */ |
166 | uint32_t pll_in_min; |
166 | uint32_t pll_in_min; |
167 | uint32_t pll_in_max; |
167 | uint32_t pll_in_max; |
168 | uint32_t pll_out_min; |
168 | uint32_t pll_out_min; |
169 | uint32_t pll_out_max; |
169 | uint32_t pll_out_max; |
170 | uint32_t lcd_pll_out_min; |
170 | uint32_t lcd_pll_out_min; |
171 | uint32_t lcd_pll_out_max; |
171 | uint32_t lcd_pll_out_max; |
172 | uint32_t best_vco; |
172 | uint32_t best_vco; |
173 | 173 | ||
174 | /* divider limits */ |
174 | /* divider limits */ |
175 | uint32_t min_ref_div; |
175 | uint32_t min_ref_div; |
176 | uint32_t max_ref_div; |
176 | uint32_t max_ref_div; |
177 | uint32_t min_post_div; |
177 | uint32_t min_post_div; |
178 | uint32_t max_post_div; |
178 | uint32_t max_post_div; |
179 | uint32_t min_feedback_div; |
179 | uint32_t min_feedback_div; |
180 | uint32_t max_feedback_div; |
180 | uint32_t max_feedback_div; |
181 | uint32_t min_frac_feedback_div; |
181 | uint32_t min_frac_feedback_div; |
182 | uint32_t max_frac_feedback_div; |
182 | uint32_t max_frac_feedback_div; |
183 | 183 | ||
184 | /* flags for the current clock */ |
184 | /* flags for the current clock */ |
185 | uint32_t flags; |
185 | uint32_t flags; |
186 | 186 | ||
187 | /* pll id */ |
187 | /* pll id */ |
188 | uint32_t id; |
188 | uint32_t id; |
189 | }; |
189 | }; |
190 | 190 | ||
191 | struct radeon_i2c_chan { |
191 | struct radeon_i2c_chan { |
192 | struct i2c_adapter adapter; |
192 | struct i2c_adapter adapter; |
193 | struct drm_device *dev; |
193 | struct drm_device *dev; |
194 | struct i2c_algo_bit_data bit; |
194 | struct i2c_algo_bit_data bit; |
195 | struct radeon_i2c_bus_rec rec; |
195 | struct radeon_i2c_bus_rec rec; |
196 | struct drm_dp_aux aux; |
196 | struct drm_dp_aux aux; |
197 | bool has_aux; |
197 | bool has_aux; |
198 | struct mutex mutex; |
198 | struct mutex mutex; |
199 | }; |
199 | }; |
200 | 200 | ||
201 | /* mostly for macs, but really any system without connector tables */ |
201 | /* mostly for macs, but really any system without connector tables */ |
202 | enum radeon_connector_table { |
202 | enum radeon_connector_table { |
203 | CT_NONE = 0, |
203 | CT_NONE = 0, |
204 | CT_GENERIC, |
204 | CT_GENERIC, |
205 | CT_IBOOK, |
205 | CT_IBOOK, |
206 | CT_POWERBOOK_EXTERNAL, |
206 | CT_POWERBOOK_EXTERNAL, |
207 | CT_POWERBOOK_INTERNAL, |
207 | CT_POWERBOOK_INTERNAL, |
208 | CT_POWERBOOK_VGA, |
208 | CT_POWERBOOK_VGA, |
209 | CT_MINI_EXTERNAL, |
209 | CT_MINI_EXTERNAL, |
210 | CT_MINI_INTERNAL, |
210 | CT_MINI_INTERNAL, |
211 | CT_IMAC_G5_ISIGHT, |
211 | CT_IMAC_G5_ISIGHT, |
212 | CT_EMAC, |
212 | CT_EMAC, |
213 | CT_RN50_POWER, |
213 | CT_RN50_POWER, |
214 | CT_MAC_X800, |
214 | CT_MAC_X800, |
215 | CT_MAC_G5_9600, |
215 | CT_MAC_G5_9600, |
216 | CT_SAM440EP, |
216 | CT_SAM440EP, |
217 | CT_MAC_G4_SILVER |
217 | CT_MAC_G4_SILVER |
218 | }; |
218 | }; |
219 | 219 | ||
220 | enum radeon_dvo_chip { |
220 | enum radeon_dvo_chip { |
221 | DVO_SIL164, |
221 | DVO_SIL164, |
222 | DVO_SIL1178, |
222 | DVO_SIL1178, |
223 | }; |
223 | }; |
224 | 224 | ||
225 | struct radeon_fbdev; |
225 | struct radeon_fbdev; |
226 | 226 | ||
227 | struct radeon_afmt { |
227 | struct radeon_afmt { |
228 | bool enabled; |
228 | bool enabled; |
229 | int offset; |
229 | int offset; |
230 | bool last_buffer_filled_status; |
230 | bool last_buffer_filled_status; |
231 | int id; |
231 | int id; |
232 | struct r600_audio_pin *pin; |
232 | struct r600_audio_pin *pin; |
233 | }; |
233 | }; |
234 | 234 | ||
235 | struct radeon_mode_info { |
235 | struct radeon_mode_info { |
236 | struct atom_context *atom_context; |
236 | struct atom_context *atom_context; |
237 | struct card_info *atom_card_info; |
237 | struct card_info *atom_card_info; |
238 | enum radeon_connector_table connector_table; |
238 | enum radeon_connector_table connector_table; |
239 | bool mode_config_initialized; |
239 | bool mode_config_initialized; |
240 | struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; |
240 | struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; |
241 | struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; |
241 | struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; |
242 | /* DVI-I properties */ |
242 | /* DVI-I properties */ |
243 | struct drm_property *coherent_mode_property; |
243 | struct drm_property *coherent_mode_property; |
244 | /* DAC enable load detect */ |
244 | /* DAC enable load detect */ |
245 | struct drm_property *load_detect_property; |
245 | struct drm_property *load_detect_property; |
246 | /* TV standard */ |
246 | /* TV standard */ |
247 | struct drm_property *tv_std_property; |
247 | struct drm_property *tv_std_property; |
248 | /* legacy TMDS PLL detect */ |
248 | /* legacy TMDS PLL detect */ |
249 | struct drm_property *tmds_pll_property; |
249 | struct drm_property *tmds_pll_property; |
250 | /* underscan */ |
250 | /* underscan */ |
251 | struct drm_property *underscan_property; |
251 | struct drm_property *underscan_property; |
252 | struct drm_property *underscan_hborder_property; |
252 | struct drm_property *underscan_hborder_property; |
253 | struct drm_property *underscan_vborder_property; |
253 | struct drm_property *underscan_vborder_property; |
254 | /* audio */ |
254 | /* audio */ |
255 | struct drm_property *audio_property; |
255 | struct drm_property *audio_property; |
256 | /* FMT dithering */ |
256 | /* FMT dithering */ |
257 | struct drm_property *dither_property; |
257 | struct drm_property *dither_property; |
258 | /* hardcoded DFP edid from BIOS */ |
258 | /* hardcoded DFP edid from BIOS */ |
259 | struct edid *bios_hardcoded_edid; |
259 | struct edid *bios_hardcoded_edid; |
260 | int bios_hardcoded_edid_size; |
260 | int bios_hardcoded_edid_size; |
261 | 261 | ||
262 | /* pointer to fbdev info structure */ |
262 | /* pointer to fbdev info structure */ |
263 | struct radeon_fbdev *rfbdev; |
263 | struct radeon_fbdev *rfbdev; |
264 | /* firmware flags */ |
264 | /* firmware flags */ |
265 | u16 firmware_flags; |
265 | u16 firmware_flags; |
266 | /* pointer to backlight encoder */ |
266 | /* pointer to backlight encoder */ |
267 | struct radeon_encoder *bl_encoder; |
267 | struct radeon_encoder *bl_encoder; |
268 | }; |
268 | }; |
269 | 269 | ||
270 | #define RADEON_MAX_BL_LEVEL 0xFF |
270 | #define RADEON_MAX_BL_LEVEL 0xFF |
271 | 271 | ||
272 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
272 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
273 | 273 | ||
274 | struct radeon_backlight_privdata { |
274 | struct radeon_backlight_privdata { |
275 | struct radeon_encoder *encoder; |
275 | struct radeon_encoder *encoder; |
276 | uint8_t negative; |
276 | uint8_t negative; |
277 | }; |
277 | }; |
278 | 278 | ||
279 | #endif |
279 | #endif |
280 | 280 | ||
281 | #define MAX_H_CODE_TIMING_LEN 32 |
281 | #define MAX_H_CODE_TIMING_LEN 32 |
282 | #define MAX_V_CODE_TIMING_LEN 32 |
282 | #define MAX_V_CODE_TIMING_LEN 32 |
283 | 283 | ||
284 | /* need to store these as reading |
284 | /* need to store these as reading |
285 | back code tables is excessive */ |
285 | back code tables is excessive */ |
286 | struct radeon_tv_regs { |
286 | struct radeon_tv_regs { |
287 | uint32_t tv_uv_adr; |
287 | uint32_t tv_uv_adr; |
288 | uint32_t timing_cntl; |
288 | uint32_t timing_cntl; |
289 | uint32_t hrestart; |
289 | uint32_t hrestart; |
290 | uint32_t vrestart; |
290 | uint32_t vrestart; |
291 | uint32_t frestart; |
291 | uint32_t frestart; |
292 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
292 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
293 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
293 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
294 | }; |
294 | }; |
295 | 295 | ||
296 | struct radeon_atom_ss { |
296 | struct radeon_atom_ss { |
297 | uint16_t percentage; |
297 | uint16_t percentage; |
298 | uint16_t percentage_divider; |
298 | uint16_t percentage_divider; |
299 | uint8_t type; |
299 | uint8_t type; |
300 | uint16_t step; |
300 | uint16_t step; |
301 | uint8_t delay; |
301 | uint8_t delay; |
302 | uint8_t range; |
302 | uint8_t range; |
303 | uint8_t refdiv; |
303 | uint8_t refdiv; |
304 | /* asic_ss */ |
304 | /* asic_ss */ |
305 | uint16_t rate; |
305 | uint16_t rate; |
306 | uint16_t amount; |
306 | uint16_t amount; |
307 | }; |
307 | }; |
308 | 308 | ||
309 | enum radeon_flip_status { |
309 | enum radeon_flip_status { |
310 | RADEON_FLIP_NONE, |
310 | RADEON_FLIP_NONE, |
311 | RADEON_FLIP_PENDING, |
311 | RADEON_FLIP_PENDING, |
312 | RADEON_FLIP_SUBMITTED |
312 | RADEON_FLIP_SUBMITTED |
313 | }; |
313 | }; |
314 | 314 | ||
315 | struct radeon_crtc { |
315 | struct radeon_crtc { |
316 | struct drm_crtc base; |
316 | struct drm_crtc base; |
317 | int crtc_id; |
317 | int crtc_id; |
318 | u16 lut_r[256], lut_g[256], lut_b[256]; |
318 | u16 lut_r[256], lut_g[256], lut_b[256]; |
319 | bool enabled; |
319 | bool enabled; |
320 | bool can_tile; |
320 | bool can_tile; |
321 | uint32_t crtc_offset; |
321 | uint32_t crtc_offset; |
322 | struct drm_gem_object *cursor_bo; |
322 | struct drm_gem_object *cursor_bo; |
323 | uint64_t cursor_addr; |
323 | uint64_t cursor_addr; |
- | 324 | int cursor_x; |
|
- | 325 | int cursor_y; |
|
- | 326 | int cursor_hot_x; |
|
- | 327 | int cursor_hot_y; |
|
324 | int cursor_width; |
328 | int cursor_width; |
325 | int cursor_height; |
329 | int cursor_height; |
326 | int max_cursor_width; |
330 | int max_cursor_width; |
327 | int max_cursor_height; |
331 | int max_cursor_height; |
328 | uint32_t legacy_display_base_addr; |
332 | uint32_t legacy_display_base_addr; |
329 | uint32_t legacy_cursor_offset; |
333 | uint32_t legacy_cursor_offset; |
330 | enum radeon_rmx_type rmx_type; |
334 | enum radeon_rmx_type rmx_type; |
331 | u8 h_border; |
335 | u8 h_border; |
332 | u8 v_border; |
336 | u8 v_border; |
333 | fixed20_12 vsc; |
337 | fixed20_12 vsc; |
334 | fixed20_12 hsc; |
338 | fixed20_12 hsc; |
335 | struct drm_display_mode native_mode; |
339 | struct drm_display_mode native_mode; |
336 | int pll_id; |
340 | int pll_id; |
337 | /* page flipping */ |
341 | /* page flipping */ |
338 | struct workqueue_struct *flip_queue; |
342 | struct workqueue_struct *flip_queue; |
339 | struct radeon_flip_work *flip_work; |
343 | struct radeon_flip_work *flip_work; |
340 | enum radeon_flip_status flip_status; |
344 | enum radeon_flip_status flip_status; |
341 | /* pll sharing */ |
345 | /* pll sharing */ |
342 | struct radeon_atom_ss ss; |
346 | struct radeon_atom_ss ss; |
343 | bool ss_enabled; |
347 | bool ss_enabled; |
344 | u32 adjusted_clock; |
348 | u32 adjusted_clock; |
345 | int bpc; |
349 | int bpc; |
346 | u32 pll_reference_div; |
350 | u32 pll_reference_div; |
347 | u32 pll_post_div; |
351 | u32 pll_post_div; |
348 | u32 pll_flags; |
352 | u32 pll_flags; |
349 | struct drm_encoder *encoder; |
353 | struct drm_encoder *encoder; |
350 | struct drm_connector *connector; |
354 | struct drm_connector *connector; |
351 | /* for dpm */ |
355 | /* for dpm */ |
352 | u32 line_time; |
356 | u32 line_time; |
353 | u32 wm_low; |
357 | u32 wm_low; |
354 | u32 wm_high; |
358 | u32 wm_high; |
355 | struct drm_display_mode hw_mode; |
359 | struct drm_display_mode hw_mode; |
356 | }; |
360 | }; |
357 | 361 | ||
358 | struct radeon_encoder_primary_dac { |
362 | struct radeon_encoder_primary_dac { |
359 | /* legacy primary dac */ |
363 | /* legacy primary dac */ |
360 | uint32_t ps2_pdac_adj; |
364 | uint32_t ps2_pdac_adj; |
361 | }; |
365 | }; |
362 | 366 | ||
363 | struct radeon_encoder_lvds { |
367 | struct radeon_encoder_lvds { |
364 | /* legacy lvds */ |
368 | /* legacy lvds */ |
365 | uint16_t panel_vcc_delay; |
369 | uint16_t panel_vcc_delay; |
366 | uint8_t panel_pwr_delay; |
370 | uint8_t panel_pwr_delay; |
367 | uint8_t panel_digon_delay; |
371 | uint8_t panel_digon_delay; |
368 | uint8_t panel_blon_delay; |
372 | uint8_t panel_blon_delay; |
369 | uint16_t panel_ref_divider; |
373 | uint16_t panel_ref_divider; |
370 | uint8_t panel_post_divider; |
374 | uint8_t panel_post_divider; |
371 | uint16_t panel_fb_divider; |
375 | uint16_t panel_fb_divider; |
372 | bool use_bios_dividers; |
376 | bool use_bios_dividers; |
373 | uint32_t lvds_gen_cntl; |
377 | uint32_t lvds_gen_cntl; |
374 | /* panel mode */ |
378 | /* panel mode */ |
375 | struct drm_display_mode native_mode; |
379 | struct drm_display_mode native_mode; |
376 | struct backlight_device *bl_dev; |
380 | struct backlight_device *bl_dev; |
377 | int dpms_mode; |
381 | int dpms_mode; |
378 | uint8_t backlight_level; |
382 | uint8_t backlight_level; |
379 | }; |
383 | }; |
380 | 384 | ||
381 | struct radeon_encoder_tv_dac { |
385 | struct radeon_encoder_tv_dac { |
382 | /* legacy tv dac */ |
386 | /* legacy tv dac */ |
383 | uint32_t ps2_tvdac_adj; |
387 | uint32_t ps2_tvdac_adj; |
384 | uint32_t ntsc_tvdac_adj; |
388 | uint32_t ntsc_tvdac_adj; |
385 | uint32_t pal_tvdac_adj; |
389 | uint32_t pal_tvdac_adj; |
386 | 390 | ||
387 | int h_pos; |
391 | int h_pos; |
388 | int v_pos; |
392 | int v_pos; |
389 | int h_size; |
393 | int h_size; |
390 | int supported_tv_stds; |
394 | int supported_tv_stds; |
391 | bool tv_on; |
395 | bool tv_on; |
392 | enum radeon_tv_std tv_std; |
396 | enum radeon_tv_std tv_std; |
393 | struct radeon_tv_regs tv; |
397 | struct radeon_tv_regs tv; |
394 | }; |
398 | }; |
395 | 399 | ||
396 | struct radeon_encoder_int_tmds { |
400 | struct radeon_encoder_int_tmds { |
397 | /* legacy int tmds */ |
401 | /* legacy int tmds */ |
398 | struct radeon_tmds_pll tmds_pll[4]; |
402 | struct radeon_tmds_pll tmds_pll[4]; |
399 | }; |
403 | }; |
400 | 404 | ||
401 | struct radeon_encoder_ext_tmds { |
405 | struct radeon_encoder_ext_tmds { |
402 | /* tmds over dvo */ |
406 | /* tmds over dvo */ |
403 | struct radeon_i2c_chan *i2c_bus; |
407 | struct radeon_i2c_chan *i2c_bus; |
404 | uint8_t slave_addr; |
408 | uint8_t slave_addr; |
405 | enum radeon_dvo_chip dvo_chip; |
409 | enum radeon_dvo_chip dvo_chip; |
406 | }; |
410 | }; |
407 | 411 | ||
408 | /* spread spectrum */ |
412 | /* spread spectrum */ |
409 | struct radeon_encoder_atom_dig { |
413 | struct radeon_encoder_atom_dig { |
410 | bool linkb; |
414 | bool linkb; |
411 | /* atom dig */ |
415 | /* atom dig */ |
412 | bool coherent_mode; |
416 | bool coherent_mode; |
413 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
417 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
414 | /* atom lvds/edp */ |
418 | /* atom lvds/edp */ |
415 | uint32_t lcd_misc; |
419 | uint32_t lcd_misc; |
416 | uint16_t panel_pwr_delay; |
420 | uint16_t panel_pwr_delay; |
417 | uint32_t lcd_ss_id; |
421 | uint32_t lcd_ss_id; |
418 | /* panel mode */ |
422 | /* panel mode */ |
419 | struct drm_display_mode native_mode; |
423 | struct drm_display_mode native_mode; |
420 | struct backlight_device *bl_dev; |
424 | struct backlight_device *bl_dev; |
421 | int dpms_mode; |
425 | int dpms_mode; |
422 | uint8_t backlight_level; |
426 | uint8_t backlight_level; |
423 | int panel_mode; |
427 | int panel_mode; |
424 | struct radeon_afmt *afmt; |
428 | struct radeon_afmt *afmt; |
425 | }; |
429 | }; |
426 | 430 | ||
427 | struct radeon_encoder_atom_dac { |
431 | struct radeon_encoder_atom_dac { |
428 | enum radeon_tv_std tv_std; |
432 | enum radeon_tv_std tv_std; |
429 | }; |
433 | }; |
430 | 434 | ||
431 | struct radeon_encoder { |
435 | struct radeon_encoder { |
432 | struct drm_encoder base; |
436 | struct drm_encoder base; |
433 | uint32_t encoder_enum; |
437 | uint32_t encoder_enum; |
434 | uint32_t encoder_id; |
438 | uint32_t encoder_id; |
435 | uint32_t devices; |
439 | uint32_t devices; |
436 | uint32_t active_device; |
440 | uint32_t active_device; |
437 | uint32_t flags; |
441 | uint32_t flags; |
438 | uint32_t pixel_clock; |
442 | uint32_t pixel_clock; |
439 | enum radeon_rmx_type rmx_type; |
443 | enum radeon_rmx_type rmx_type; |
440 | enum radeon_underscan_type underscan_type; |
444 | enum radeon_underscan_type underscan_type; |
441 | uint32_t underscan_hborder; |
445 | uint32_t underscan_hborder; |
442 | uint32_t underscan_vborder; |
446 | uint32_t underscan_vborder; |
443 | struct drm_display_mode native_mode; |
447 | struct drm_display_mode native_mode; |
444 | void *enc_priv; |
448 | void *enc_priv; |
445 | int audio_polling_active; |
449 | int audio_polling_active; |
446 | bool is_ext_encoder; |
450 | bool is_ext_encoder; |
447 | u16 caps; |
451 | u16 caps; |
448 | }; |
452 | }; |
449 | 453 | ||
450 | struct radeon_connector_atom_dig { |
454 | struct radeon_connector_atom_dig { |
451 | uint32_t igp_lane_info; |
455 | uint32_t igp_lane_info; |
452 | /* displayport */ |
456 | /* displayport */ |
453 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
457 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
454 | u8 dp_sink_type; |
458 | u8 dp_sink_type; |
455 | int dp_clock; |
459 | int dp_clock; |
456 | int dp_lane_count; |
460 | int dp_lane_count; |
457 | bool edp_on; |
461 | bool edp_on; |
458 | }; |
462 | }; |
459 | 463 | ||
460 | struct radeon_gpio_rec { |
464 | struct radeon_gpio_rec { |
461 | bool valid; |
465 | bool valid; |
462 | u8 id; |
466 | u8 id; |
463 | u32 reg; |
467 | u32 reg; |
464 | u32 mask; |
468 | u32 mask; |
- | 469 | u32 shift; |
|
465 | }; |
470 | }; |
466 | 471 | ||
467 | struct radeon_hpd { |
472 | struct radeon_hpd { |
468 | enum radeon_hpd_id hpd; |
473 | enum radeon_hpd_id hpd; |
469 | u8 plugged_state; |
474 | u8 plugged_state; |
470 | struct radeon_gpio_rec gpio; |
475 | struct radeon_gpio_rec gpio; |
471 | }; |
476 | }; |
472 | 477 | ||
473 | struct radeon_router { |
478 | struct radeon_router { |
474 | u32 router_id; |
479 | u32 router_id; |
475 | struct radeon_i2c_bus_rec i2c_info; |
480 | struct radeon_i2c_bus_rec i2c_info; |
476 | u8 i2c_addr; |
481 | u8 i2c_addr; |
477 | /* i2c mux */ |
482 | /* i2c mux */ |
478 | bool ddc_valid; |
483 | bool ddc_valid; |
479 | u8 ddc_mux_type; |
484 | u8 ddc_mux_type; |
480 | u8 ddc_mux_control_pin; |
485 | u8 ddc_mux_control_pin; |
481 | u8 ddc_mux_state; |
486 | u8 ddc_mux_state; |
482 | /* clock/data mux */ |
487 | /* clock/data mux */ |
483 | bool cd_valid; |
488 | bool cd_valid; |
484 | u8 cd_mux_type; |
489 | u8 cd_mux_type; |
485 | u8 cd_mux_control_pin; |
490 | u8 cd_mux_control_pin; |
486 | u8 cd_mux_state; |
491 | u8 cd_mux_state; |
487 | }; |
492 | }; |
488 | 493 | ||
489 | enum radeon_connector_audio { |
494 | enum radeon_connector_audio { |
490 | RADEON_AUDIO_DISABLE = 0, |
495 | RADEON_AUDIO_DISABLE = 0, |
491 | RADEON_AUDIO_ENABLE = 1, |
496 | RADEON_AUDIO_ENABLE = 1, |
492 | RADEON_AUDIO_AUTO = 2 |
497 | RADEON_AUDIO_AUTO = 2 |
493 | }; |
498 | }; |
494 | 499 | ||
495 | enum radeon_connector_dither { |
500 | enum radeon_connector_dither { |
496 | RADEON_FMT_DITHER_DISABLE = 0, |
501 | RADEON_FMT_DITHER_DISABLE = 0, |
497 | RADEON_FMT_DITHER_ENABLE = 1, |
502 | RADEON_FMT_DITHER_ENABLE = 1, |
498 | }; |
503 | }; |
499 | 504 | ||
500 | struct radeon_connector { |
505 | struct radeon_connector { |
501 | struct drm_connector base; |
506 | struct drm_connector base; |
502 | uint32_t connector_id; |
507 | uint32_t connector_id; |
503 | uint32_t devices; |
508 | uint32_t devices; |
504 | struct radeon_i2c_chan *ddc_bus; |
509 | struct radeon_i2c_chan *ddc_bus; |
505 | /* some systems have an hdmi and vga port with a shared ddc line */ |
510 | /* some systems have an hdmi and vga port with a shared ddc line */ |
506 | bool shared_ddc; |
511 | bool shared_ddc; |
507 | bool use_digital; |
512 | bool use_digital; |
508 | /* we need to mind the EDID between detect |
513 | /* we need to mind the EDID between detect |
509 | and get modes due to analog/digital/tvencoder */ |
514 | and get modes due to analog/digital/tvencoder */ |
510 | struct edid *edid; |
515 | struct edid *edid; |
511 | void *con_priv; |
516 | void *con_priv; |
512 | bool dac_load_detect; |
517 | bool dac_load_detect; |
513 | bool detected_by_load; /* if the connection status was determined by load */ |
518 | bool detected_by_load; /* if the connection status was determined by load */ |
514 | uint16_t connector_object_id; |
519 | uint16_t connector_object_id; |
515 | struct radeon_hpd hpd; |
520 | struct radeon_hpd hpd; |
516 | struct radeon_router router; |
521 | struct radeon_router router; |
517 | struct radeon_i2c_chan *router_bus; |
522 | struct radeon_i2c_chan *router_bus; |
518 | enum radeon_connector_audio audio; |
523 | enum radeon_connector_audio audio; |
519 | enum radeon_connector_dither dither; |
524 | enum radeon_connector_dither dither; |
520 | int pixelclock_for_modeset; |
525 | int pixelclock_for_modeset; |
521 | }; |
526 | }; |
522 | 527 | ||
523 | struct radeon_framebuffer { |
528 | struct radeon_framebuffer { |
524 | struct drm_framebuffer base; |
529 | struct drm_framebuffer base; |
525 | struct drm_gem_object *obj; |
530 | struct drm_gem_object *obj; |
526 | }; |
531 | }; |
527 | 532 | ||
528 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
533 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
529 | ((em) == ATOM_ENCODER_MODE_DP_MST)) |
534 | ((em) == ATOM_ENCODER_MODE_DP_MST)) |
530 | 535 | ||
531 | struct atom_clock_dividers { |
536 | struct atom_clock_dividers { |
532 | u32 post_div; |
537 | u32 post_div; |
533 | union { |
538 | union { |
534 | struct { |
539 | struct { |
535 | #ifdef __BIG_ENDIAN |
540 | #ifdef __BIG_ENDIAN |
536 | u32 reserved : 6; |
541 | u32 reserved : 6; |
537 | u32 whole_fb_div : 12; |
542 | u32 whole_fb_div : 12; |
538 | u32 frac_fb_div : 14; |
543 | u32 frac_fb_div : 14; |
539 | #else |
544 | #else |
540 | u32 frac_fb_div : 14; |
545 | u32 frac_fb_div : 14; |
541 | u32 whole_fb_div : 12; |
546 | u32 whole_fb_div : 12; |
542 | u32 reserved : 6; |
547 | u32 reserved : 6; |
543 | #endif |
548 | #endif |
544 | }; |
549 | }; |
545 | u32 fb_div; |
550 | u32 fb_div; |
546 | }; |
551 | }; |
547 | u32 ref_div; |
552 | u32 ref_div; |
548 | bool enable_post_div; |
553 | bool enable_post_div; |
549 | bool enable_dithen; |
554 | bool enable_dithen; |
550 | u32 vco_mode; |
555 | u32 vco_mode; |
551 | u32 real_clock; |
556 | u32 real_clock; |
552 | /* added for CI */ |
557 | /* added for CI */ |
553 | u32 post_divider; |
558 | u32 post_divider; |
554 | u32 flags; |
559 | u32 flags; |
555 | }; |
560 | }; |
556 | 561 | ||
557 | struct atom_mpll_param { |
562 | struct atom_mpll_param { |
558 | union { |
563 | union { |
559 | struct { |
564 | struct { |
560 | #ifdef __BIG_ENDIAN |
565 | #ifdef __BIG_ENDIAN |
561 | u32 reserved : 8; |
566 | u32 reserved : 8; |
562 | u32 clkfrac : 12; |
567 | u32 clkfrac : 12; |
563 | u32 clkf : 12; |
568 | u32 clkf : 12; |
564 | #else |
569 | #else |
565 | u32 clkf : 12; |
570 | u32 clkf : 12; |
566 | u32 clkfrac : 12; |
571 | u32 clkfrac : 12; |
567 | u32 reserved : 8; |
572 | u32 reserved : 8; |
568 | #endif |
573 | #endif |
569 | }; |
574 | }; |
570 | u32 fb_div; |
575 | u32 fb_div; |
571 | }; |
576 | }; |
572 | u32 post_div; |
577 | u32 post_div; |
573 | u32 bwcntl; |
578 | u32 bwcntl; |
574 | u32 dll_speed; |
579 | u32 dll_speed; |
575 | u32 vco_mode; |
580 | u32 vco_mode; |
576 | u32 yclk_sel; |
581 | u32 yclk_sel; |
577 | u32 qdr; |
582 | u32 qdr; |
578 | u32 half_rate; |
583 | u32 half_rate; |
579 | }; |
584 | }; |
580 | 585 | ||
581 | #define MEM_TYPE_GDDR5 0x50 |
586 | #define MEM_TYPE_GDDR5 0x50 |
582 | #define MEM_TYPE_GDDR4 0x40 |
587 | #define MEM_TYPE_GDDR4 0x40 |
583 | #define MEM_TYPE_GDDR3 0x30 |
588 | #define MEM_TYPE_GDDR3 0x30 |
584 | #define MEM_TYPE_DDR2 0x20 |
589 | #define MEM_TYPE_DDR2 0x20 |
585 | #define MEM_TYPE_GDDR1 0x10 |
590 | #define MEM_TYPE_GDDR1 0x10 |
586 | #define MEM_TYPE_DDR3 0xb0 |
591 | #define MEM_TYPE_DDR3 0xb0 |
587 | #define MEM_TYPE_MASK 0xf0 |
592 | #define MEM_TYPE_MASK 0xf0 |
588 | 593 | ||
589 | struct atom_memory_info { |
594 | struct atom_memory_info { |
590 | u8 mem_vendor; |
595 | u8 mem_vendor; |
591 | u8 mem_type; |
596 | u8 mem_type; |
592 | }; |
597 | }; |
593 | 598 | ||
594 | #define MAX_AC_TIMING_ENTRIES 16 |
599 | #define MAX_AC_TIMING_ENTRIES 16 |
595 | 600 | ||
596 | struct atom_memory_clock_range_table |
601 | struct atom_memory_clock_range_table |
597 | { |
602 | { |
598 | u8 num_entries; |
603 | u8 num_entries; |
599 | u8 rsv[3]; |
604 | u8 rsv[3]; |
600 | u32 mclk[MAX_AC_TIMING_ENTRIES]; |
605 | u32 mclk[MAX_AC_TIMING_ENTRIES]; |
601 | }; |
606 | }; |
602 | 607 | ||
603 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 |
608 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 |
604 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 |
609 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 |
605 | 610 | ||
606 | struct atom_mc_reg_entry { |
611 | struct atom_mc_reg_entry { |
607 | u32 mclk_max; |
612 | u32 mclk_max; |
608 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
613 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
609 | }; |
614 | }; |
610 | 615 | ||
611 | struct atom_mc_register_address { |
616 | struct atom_mc_register_address { |
612 | u16 s1; |
617 | u16 s1; |
613 | u8 pre_reg_data; |
618 | u8 pre_reg_data; |
614 | }; |
619 | }; |
615 | 620 | ||
616 | struct atom_mc_reg_table { |
621 | struct atom_mc_reg_table { |
617 | u8 last; |
622 | u8 last; |
618 | u8 num_entries; |
623 | u8 num_entries; |
619 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; |
624 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; |
620 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
625 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
621 | }; |
626 | }; |
622 | 627 | ||
623 | #define MAX_VOLTAGE_ENTRIES 32 |
628 | #define MAX_VOLTAGE_ENTRIES 32 |
624 | 629 | ||
625 | struct atom_voltage_table_entry |
630 | struct atom_voltage_table_entry |
626 | { |
631 | { |
627 | u16 value; |
632 | u16 value; |
628 | u32 smio_low; |
633 | u32 smio_low; |
629 | }; |
634 | }; |
630 | 635 | ||
631 | struct atom_voltage_table |
636 | struct atom_voltage_table |
632 | { |
637 | { |
633 | u32 count; |
638 | u32 count; |
634 | u32 mask_low; |
639 | u32 mask_low; |
635 | u32 phase_delay; |
640 | u32 phase_delay; |
636 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; |
641 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; |
637 | }; |
642 | }; |
638 | 643 | ||
639 | 644 | ||
640 | extern void |
645 | extern void |
641 | radeon_add_atom_connector(struct drm_device *dev, |
646 | radeon_add_atom_connector(struct drm_device *dev, |
642 | uint32_t connector_id, |
647 | uint32_t connector_id, |
643 | uint32_t supported_device, |
648 | uint32_t supported_device, |
644 | int connector_type, |
649 | int connector_type, |
645 | struct radeon_i2c_bus_rec *i2c_bus, |
650 | struct radeon_i2c_bus_rec *i2c_bus, |
646 | uint32_t igp_lane_info, |
651 | uint32_t igp_lane_info, |
647 | uint16_t connector_object_id, |
652 | uint16_t connector_object_id, |
648 | struct radeon_hpd *hpd, |
653 | struct radeon_hpd *hpd, |
649 | struct radeon_router *router); |
654 | struct radeon_router *router); |
650 | extern void |
655 | extern void |
651 | radeon_add_legacy_connector(struct drm_device *dev, |
656 | radeon_add_legacy_connector(struct drm_device *dev, |
652 | uint32_t connector_id, |
657 | uint32_t connector_id, |
653 | uint32_t supported_device, |
658 | uint32_t supported_device, |
654 | int connector_type, |
659 | int connector_type, |
655 | struct radeon_i2c_bus_rec *i2c_bus, |
660 | struct radeon_i2c_bus_rec *i2c_bus, |
656 | uint16_t connector_object_id, |
661 | uint16_t connector_object_id, |
657 | struct radeon_hpd *hpd); |
662 | struct radeon_hpd *hpd); |
658 | extern uint32_t |
663 | extern uint32_t |
659 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
664 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
660 | uint8_t dac); |
665 | uint8_t dac); |
661 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
666 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
662 | 667 | ||
663 | extern enum radeon_tv_std |
668 | extern enum radeon_tv_std |
664 | radeon_combios_get_tv_info(struct radeon_device *rdev); |
669 | radeon_combios_get_tv_info(struct radeon_device *rdev); |
665 | extern enum radeon_tv_std |
670 | extern enum radeon_tv_std |
666 | radeon_atombios_get_tv_info(struct radeon_device *rdev); |
671 | radeon_atombios_get_tv_info(struct radeon_device *rdev); |
667 | extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
672 | extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
668 | u16 *vddc, u16 *vddci, u16 *mvdd); |
673 | u16 *vddc, u16 *vddci, u16 *mvdd); |
669 | 674 | ||
670 | extern void |
675 | extern void |
671 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, |
676 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, |
672 | struct drm_encoder *encoder, |
677 | struct drm_encoder *encoder, |
673 | bool connected); |
678 | bool connected); |
674 | extern void |
679 | extern void |
675 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
680 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
676 | struct drm_encoder *encoder, |
681 | struct drm_encoder *encoder, |
677 | bool connected); |
682 | bool connected); |
678 | 683 | ||
679 | extern struct drm_connector * |
684 | extern struct drm_connector * |
680 | radeon_get_connector_for_encoder(struct drm_encoder *encoder); |
685 | radeon_get_connector_for_encoder(struct drm_encoder *encoder); |
681 | extern struct drm_connector * |
686 | extern struct drm_connector * |
682 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); |
687 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); |
683 | extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, |
688 | extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, |
684 | u32 pixel_clock); |
689 | u32 pixel_clock); |
685 | 690 | ||
686 | extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
691 | extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
687 | extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); |
692 | extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); |
688 | extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); |
693 | extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); |
689 | extern int radeon_get_monitor_bpc(struct drm_connector *connector); |
694 | extern int radeon_get_monitor_bpc(struct drm_connector *connector); |
690 | 695 | ||
691 | extern struct edid *radeon_connector_edid(struct drm_connector *connector); |
696 | extern struct edid *radeon_connector_edid(struct drm_connector *connector); |
692 | 697 | ||
693 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
698 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
694 | extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
699 | extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
695 | struct drm_display_mode *mode); |
700 | struct drm_display_mode *mode); |
696 | extern void radeon_dp_set_link_config(struct drm_connector *connector, |
701 | extern void radeon_dp_set_link_config(struct drm_connector *connector, |
697 | const struct drm_display_mode *mode); |
702 | const struct drm_display_mode *mode); |
698 | extern void radeon_dp_link_train(struct drm_encoder *encoder, |
703 | extern void radeon_dp_link_train(struct drm_encoder *encoder, |
699 | struct drm_connector *connector); |
704 | struct drm_connector *connector); |
700 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
705 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
701 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
706 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
702 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
707 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
703 | extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
708 | extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
704 | struct drm_connector *connector); |
709 | struct drm_connector *connector); |
705 | extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
710 | extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
706 | u8 power_state); |
711 | u8 power_state); |
707 | extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); |
712 | extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); |
708 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); |
713 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); |
709 | extern void radeon_atom_encoder_init(struct radeon_device *rdev); |
714 | extern void radeon_atom_encoder_init(struct radeon_device *rdev); |
710 | extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); |
715 | extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); |
711 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
716 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
712 | int action, uint8_t lane_num, |
717 | int action, uint8_t lane_num, |
713 | uint8_t lane_set); |
718 | uint8_t lane_set); |
714 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); |
719 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); |
715 | extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); |
720 | extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); |
716 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); |
721 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); |
717 | 722 | ||
718 | extern void radeon_i2c_init(struct radeon_device *rdev); |
723 | extern void radeon_i2c_init(struct radeon_device *rdev); |
719 | extern void radeon_i2c_fini(struct radeon_device *rdev); |
724 | extern void radeon_i2c_fini(struct radeon_device *rdev); |
720 | extern void radeon_combios_i2c_init(struct radeon_device *rdev); |
725 | extern void radeon_combios_i2c_init(struct radeon_device *rdev); |
721 | extern void radeon_atombios_i2c_init(struct radeon_device *rdev); |
726 | extern void radeon_atombios_i2c_init(struct radeon_device *rdev); |
722 | extern void radeon_i2c_add(struct radeon_device *rdev, |
727 | extern void radeon_i2c_add(struct radeon_device *rdev, |
723 | struct radeon_i2c_bus_rec *rec, |
728 | struct radeon_i2c_bus_rec *rec, |
724 | const char *name); |
729 | const char *name); |
725 | extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, |
730 | extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, |
726 | struct radeon_i2c_bus_rec *i2c_bus); |
731 | struct radeon_i2c_bus_rec *i2c_bus); |
727 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
732 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
728 | struct radeon_i2c_bus_rec *rec, |
733 | struct radeon_i2c_bus_rec *rec, |
729 | const char *name); |
734 | const char *name); |
730 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
735 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
731 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
736 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
732 | u8 slave_addr, |
737 | u8 slave_addr, |
733 | u8 addr, |
738 | u8 addr, |
734 | u8 *val); |
739 | u8 *val); |
735 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, |
740 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, |
736 | u8 slave_addr, |
741 | u8 slave_addr, |
737 | u8 addr, |
742 | u8 addr, |
738 | u8 val); |
743 | u8 val); |
739 | extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
744 | extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
740 | extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); |
745 | extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); |
741 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
746 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
742 | 747 | ||
743 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |
748 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |
744 | 749 | ||
745 | extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
750 | extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
746 | struct radeon_atom_ss *ss, |
751 | struct radeon_atom_ss *ss, |
747 | int id); |
752 | int id); |
748 | extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, |
753 | extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, |
749 | struct radeon_atom_ss *ss, |
754 | struct radeon_atom_ss *ss, |
750 | int id, u32 clock); |
755 | int id, u32 clock); |
- | 756 | extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, |
|
- | 757 | u8 id); |
|
751 | 758 | ||
752 | extern void radeon_compute_pll_legacy(struct radeon_pll *pll, |
759 | extern void radeon_compute_pll_legacy(struct radeon_pll *pll, |
753 | uint64_t freq, |
760 | uint64_t freq, |
754 | uint32_t *dot_clock_p, |
761 | uint32_t *dot_clock_p, |
755 | uint32_t *fb_div_p, |
762 | uint32_t *fb_div_p, |
756 | uint32_t *frac_fb_div_p, |
763 | uint32_t *frac_fb_div_p, |
757 | uint32_t *ref_div_p, |
764 | uint32_t *ref_div_p, |
758 | uint32_t *post_div_p); |
765 | uint32_t *post_div_p); |
759 | 766 | ||
760 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
767 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
761 | u32 freq, |
768 | u32 freq, |
762 | u32 *dot_clock_p, |
769 | u32 *dot_clock_p, |
763 | u32 *fb_div_p, |
770 | u32 *fb_div_p, |
764 | u32 *frac_fb_div_p, |
771 | u32 *frac_fb_div_p, |
765 | u32 *ref_div_p, |
772 | u32 *ref_div_p, |
766 | u32 *post_div_p); |
773 | u32 *post_div_p); |
767 | 774 | ||
768 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
775 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
769 | 776 | ||
770 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
777 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
771 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
778 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
772 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
779 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
773 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
780 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
774 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
781 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
775 | extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); |
782 | extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); |
776 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
783 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
777 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
784 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
778 | extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); |
785 | extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); |
779 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
786 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
- | 787 | extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); |
|
780 | 788 | ||
781 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
789 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
782 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
790 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
783 | struct drm_framebuffer *old_fb); |
791 | struct drm_framebuffer *old_fb); |
784 | extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
792 | extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
785 | struct drm_framebuffer *fb, |
793 | struct drm_framebuffer *fb, |
786 | int x, int y, |
794 | int x, int y, |
787 | enum mode_set_atomic state); |
795 | enum mode_set_atomic state); |
788 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
796 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
789 | struct drm_display_mode *mode, |
797 | struct drm_display_mode *mode, |
790 | struct drm_display_mode *adjusted_mode, |
798 | struct drm_display_mode *adjusted_mode, |
791 | int x, int y, |
799 | int x, int y, |
792 | struct drm_framebuffer *old_fb); |
800 | struct drm_framebuffer *old_fb); |
793 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
801 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
794 | 802 | ||
795 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
803 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
796 | struct drm_framebuffer *old_fb); |
804 | struct drm_framebuffer *old_fb); |
797 | extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
805 | extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
798 | struct drm_framebuffer *fb, |
806 | struct drm_framebuffer *fb, |
799 | int x, int y, |
807 | int x, int y, |
800 | enum mode_set_atomic state); |
808 | enum mode_set_atomic state); |
801 | extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
809 | extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
802 | struct drm_framebuffer *fb, |
810 | struct drm_framebuffer *fb, |
803 | int x, int y, int atomic); |
811 | int x, int y, int atomic); |
804 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
812 | extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, |
805 | struct drm_file *file_priv, |
813 | struct drm_file *file_priv, |
806 | uint32_t handle, |
814 | uint32_t handle, |
807 | uint32_t width, |
815 | uint32_t width, |
808 | uint32_t height); |
816 | uint32_t height, |
- | 817 | int32_t hot_x, |
|
- | 818 | int32_t hot_y); |
|
809 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
819 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
810 | int x, int y); |
820 | int x, int y); |
- | 821 | extern void radeon_cursor_reset(struct drm_crtc *crtc); |
|
811 | 822 | ||
812 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, |
823 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, |
813 | unsigned int flags, |
824 | unsigned int flags, |
814 | int *vpos, int *hpos, void *stime, |
825 | int *vpos, int *hpos, void *stime, |
815 | void *etime); |
826 | void *etime); |
816 | 827 | ||
817 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
828 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
818 | extern struct edid * |
829 | extern struct edid * |
819 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); |
830 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); |
820 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
831 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
821 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
832 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
822 | extern struct radeon_encoder_atom_dig * |
833 | extern struct radeon_encoder_atom_dig * |
823 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
834 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
824 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
835 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
825 | struct radeon_encoder_int_tmds *tmds); |
836 | struct radeon_encoder_int_tmds *tmds); |
826 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
837 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
827 | struct radeon_encoder_int_tmds *tmds); |
838 | struct radeon_encoder_int_tmds *tmds); |
828 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
839 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
829 | struct radeon_encoder_int_tmds *tmds); |
840 | struct radeon_encoder_int_tmds *tmds); |
830 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
841 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
831 | struct radeon_encoder_ext_tmds *tmds); |
842 | struct radeon_encoder_ext_tmds *tmds); |
832 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
843 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
833 | struct radeon_encoder_ext_tmds *tmds); |
844 | struct radeon_encoder_ext_tmds *tmds); |
834 | extern struct radeon_encoder_primary_dac * |
845 | extern struct radeon_encoder_primary_dac * |
835 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
846 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
836 | extern struct radeon_encoder_tv_dac * |
847 | extern struct radeon_encoder_tv_dac * |
837 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
848 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
838 | extern struct radeon_encoder_lvds * |
849 | extern struct radeon_encoder_lvds * |
839 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
850 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
840 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
851 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
841 | extern struct radeon_encoder_tv_dac * |
852 | extern struct radeon_encoder_tv_dac * |
842 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
853 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
843 | extern struct radeon_encoder_primary_dac * |
854 | extern struct radeon_encoder_primary_dac * |
844 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
855 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
845 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
856 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
846 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); |
857 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); |
847 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
858 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
848 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
859 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
849 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
860 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
850 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
861 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
851 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
862 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
852 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
863 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
853 | extern void |
864 | extern void |
854 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
865 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
855 | extern void |
866 | extern void |
856 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
867 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
857 | extern void |
868 | extern void |
858 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
869 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
859 | extern void |
870 | extern void |
860 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
871 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
861 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
872 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
862 | u16 blue, int regno); |
873 | u16 blue, int regno); |
863 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
874 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
864 | u16 *blue, int regno); |
875 | u16 *blue, int regno); |
865 | int radeon_framebuffer_init(struct drm_device *dev, |
876 | int radeon_framebuffer_init(struct drm_device *dev, |
866 | struct radeon_framebuffer *rfb, |
877 | struct radeon_framebuffer *rfb, |
867 | struct drm_mode_fb_cmd2 *mode_cmd, |
878 | struct drm_mode_fb_cmd2 *mode_cmd, |
868 | struct drm_gem_object *obj); |
879 | struct drm_gem_object *obj); |
869 | 880 | ||
870 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
881 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
871 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
882 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
872 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
883 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
873 | void radeon_atombios_init_crtc(struct drm_device *dev, |
884 | void radeon_atombios_init_crtc(struct drm_device *dev, |
874 | struct radeon_crtc *radeon_crtc); |
885 | struct radeon_crtc *radeon_crtc); |
875 | void radeon_legacy_init_crtc(struct drm_device *dev, |
886 | void radeon_legacy_init_crtc(struct drm_device *dev, |
876 | struct radeon_crtc *radeon_crtc); |
887 | struct radeon_crtc *radeon_crtc); |
877 | 888 | ||
878 | void radeon_get_clock_info(struct drm_device *dev); |
889 | void radeon_get_clock_info(struct drm_device *dev); |
879 | 890 | ||
880 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
891 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
881 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
892 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
882 | 893 | ||
883 | void radeon_enc_destroy(struct drm_encoder *encoder); |
894 | void radeon_enc_destroy(struct drm_encoder *encoder); |
884 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
895 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
885 | void radeon_combios_asic_init(struct drm_device *dev); |
896 | void radeon_combios_asic_init(struct drm_device *dev); |
886 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
897 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
887 | const struct drm_display_mode *mode, |
898 | const struct drm_display_mode *mode, |
888 | struct drm_display_mode *adjusted_mode); |
899 | struct drm_display_mode *adjusted_mode); |
889 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
900 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
890 | struct drm_display_mode *adjusted_mode); |
901 | struct drm_display_mode *adjusted_mode); |
891 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
902 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
892 | 903 | ||
893 | /* legacy tv */ |
904 | /* legacy tv */ |
894 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
905 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
895 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
906 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
896 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
907 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
897 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
908 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
898 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
909 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
899 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
910 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
900 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
911 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
901 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
912 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
902 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
913 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
903 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
914 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
904 | struct drm_display_mode *mode, |
915 | struct drm_display_mode *mode, |
905 | struct drm_display_mode *adjusted_mode); |
916 | struct drm_display_mode *adjusted_mode); |
906 | 917 | ||
907 | /* fmt blocks */ |
918 | /* fmt blocks */ |
908 | void avivo_program_fmt(struct drm_encoder *encoder); |
919 | void avivo_program_fmt(struct drm_encoder *encoder); |
909 | void dce3_program_fmt(struct drm_encoder *encoder); |
920 | void dce3_program_fmt(struct drm_encoder *encoder); |
910 | void dce4_program_fmt(struct drm_encoder *encoder); |
921 | void dce4_program_fmt(struct drm_encoder *encoder); |
911 | void dce8_program_fmt(struct drm_encoder *encoder); |
922 | void dce8_program_fmt(struct drm_encoder *encoder); |
912 | 923 | ||
913 | /* fbdev layer */ |
924 | /* fbdev layer */ |
914 | int radeon_fbdev_init(struct radeon_device *rdev); |
925 | int radeon_fbdev_init(struct radeon_device *rdev); |
915 | void radeon_fbdev_fini(struct radeon_device *rdev); |
926 | void radeon_fbdev_fini(struct radeon_device *rdev); |
916 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); |
927 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); |
917 | int radeon_fbdev_total_size(struct radeon_device *rdev); |
928 | int radeon_fbdev_total_size(struct radeon_device *rdev); |
918 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); |
929 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); |
919 | 930 | ||
920 | void radeon_fb_output_poll_changed(struct radeon_device *rdev); |
931 | void radeon_fb_output_poll_changed(struct radeon_device *rdev); |
921 | 932 | ||
922 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); |
933 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); |
923 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); |
934 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); |
924 | 935 | ||
925 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); |
936 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); |
926 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
937 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |