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Rev 3192 Rev 3764
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	struct drm_crtc base;
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	struct drm_crtc base;
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	int crtc_id;
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	int crtc_id;
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	u16 lut_r[256], lut_g[256], lut_b[256];
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	u16 lut_r[256], lut_g[256], lut_b[256];
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	bool enabled;
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	bool enabled;
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	bool can_tile;
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	bool can_tile;
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	bool in_mode_set;
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	uint32_t crtc_offset;
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	uint32_t crtc_offset;
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	struct drm_gem_object *cursor_bo;
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	struct drm_gem_object *cursor_bo;
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	uint64_t cursor_addr;
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	uint64_t cursor_addr;
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	int cursor_width;
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	int cursor_width;
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	int cursor_height;
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	int cursor_height;
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};
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};
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#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
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#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
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				((em) == ATOM_ENCODER_MODE_DP_MST))
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struct atom_clock_dividers {
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	u32 post_div;
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	union {
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		struct {
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#ifdef __BIG_ENDIAN
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			u32 reserved : 6;
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			u32 whole_fb_div : 12;
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			u32 frac_fb_div : 14;
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#else
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			u32 frac_fb_div : 14;
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			u32 whole_fb_div : 12;
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			u32 reserved : 6;
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#endif
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		};
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		u32 fb_div;
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	};
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	u32 ref_div;
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	bool enable_post_div;
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	bool enable_dithen;
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	u32 vco_mode;
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	u32 real_clock;
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				((em) == ATOM_ENCODER_MODE_DP_MST))
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};
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extern enum radeon_tv_std
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extern enum radeon_tv_std
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radeon_combios_get_tv_info(struct radeon_device *rdev);
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radeon_combios_get_tv_info(struct radeon_device *rdev);