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Rev 3192 | Rev 3764 | ||
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Line 300... | Line 300... | ||
300 | struct drm_crtc base; |
300 | struct drm_crtc base; |
301 | int crtc_id; |
301 | int crtc_id; |
302 | u16 lut_r[256], lut_g[256], lut_b[256]; |
302 | u16 lut_r[256], lut_g[256], lut_b[256]; |
303 | bool enabled; |
303 | bool enabled; |
304 | bool can_tile; |
304 | bool can_tile; |
305 | bool in_mode_set; |
- | |
306 | uint32_t crtc_offset; |
305 | uint32_t crtc_offset; |
307 | struct drm_gem_object *cursor_bo; |
306 | struct drm_gem_object *cursor_bo; |
308 | uint64_t cursor_addr; |
307 | uint64_t cursor_addr; |
309 | int cursor_width; |
308 | int cursor_width; |
310 | int cursor_height; |
309 | int cursor_height; |
Line 488... | Line 487... | ||
488 | }; |
487 | }; |
Line 489... | Line 488... | ||
489 | 488 | ||
490 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
489 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
Line -... | Line 490... | ||
- | 490 | ((em) == ATOM_ENCODER_MODE_DP_MST)) |
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- | 491 | ||
- | 492 | struct atom_clock_dividers { |
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- | 493 | u32 post_div; |
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- | 494 | union { |
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- | 495 | struct { |
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- | 496 | #ifdef __BIG_ENDIAN |
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- | 497 | u32 reserved : 6; |
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- | 498 | u32 whole_fb_div : 12; |
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- | 499 | u32 frac_fb_div : 14; |
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- | 500 | #else |
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- | 501 | u32 frac_fb_div : 14; |
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- | 502 | u32 whole_fb_div : 12; |
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- | 503 | u32 reserved : 6; |
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- | 504 | #endif |
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- | 505 | }; |
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- | 506 | u32 fb_div; |
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- | 507 | }; |
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- | 508 | u32 ref_div; |
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- | 509 | bool enable_post_div; |
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- | 510 | bool enable_dithen; |
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- | 511 | u32 vco_mode; |
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- | 512 | u32 real_clock; |
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491 | ((em) == ATOM_ENCODER_MODE_DP_MST)) |
513 | }; |
492 | 514 | ||
493 | extern enum radeon_tv_std |
515 | extern enum radeon_tv_std |
494 | radeon_combios_get_tv_info(struct radeon_device *rdev); |
516 | radeon_combios_get_tv_info(struct radeon_device *rdev); |