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Rev 1404 Rev 1963
Line 55... Line 55...
55 
/* tv pll setting for 14 mhz ref clk */
 55 
/* tv pll setting for 14 mhz ref clk */
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#define NTSC_TV_PLL_M_14 33
 56 
#define NTSC_TV_PLL_M_14 33
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#define NTSC_TV_PLL_N_14 693
 57 
#define NTSC_TV_PLL_N_14 693
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#define NTSC_TV_PLL_P_14 7
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#define NTSC_TV_PLL_P_14 7
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 59 
 
- 
 
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#define PAL_TV_PLL_M_14 19
- 
 
 61 
#define PAL_TV_PLL_N_14 353
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#define PAL_TV_PLL_P_14 5
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 63 
 
60 
#define VERT_LEAD_IN_LINES 2
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#define VERT_LEAD_IN_LINES 2
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#define FRAC_BITS 0xe
 65 
#define FRAC_BITS 0xe
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#define FRAC_MASK 0x3fff
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#define FRAC_MASK 0x3fff
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		347,                /* crtcPLL_N */
 210 
		347,                /* crtcPLL_N */
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		14,                 /* crtcPLL_M */
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		14,                 /* crtcPLL_M */
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			8,                  /* crtcPLL_postDiv */
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			8,                  /* crtcPLL_postDiv */
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		1022,               /* pixToTV */
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		1022,               /* pixToTV */
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	},
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	},
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	{ /* PAL timing for 14 Mhz ref clk */
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		800,                /* horResolution */
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		600,                /* verResolution */
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		TV_STD_PAL,         /* standard */
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		1131,               /* horTotal */
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		742,                /* verTotal */
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		813,                /* horStart */
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		840,                /* horSyncStart */
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		633,                /* verSyncStart */
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		708369,             /* defRestart */
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		211,                /* crtcPLL_N */
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		9,                  /* crtcPLL_M */
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 227 
		8,                  /* crtcPLL_postDiv */
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		759,                /* pixToTV */
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 229 
	},
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};
 230 
};
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 231 
 
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#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
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#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
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			const_ptr = &available_tv_modes[2];
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			const_ptr = &available_tv_modes[2];
241 
	} else {
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	} else {
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		if (pll->reference_freq == 2700)
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		if (pll->reference_freq == 2700)
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			const_ptr = &available_tv_modes[1];
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			const_ptr = &available_tv_modes[1];
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		else
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		else
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			const_ptr = &available_tv_modes[1]; /* FIX ME */
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			const_ptr = &available_tv_modes[3];
246 
	}
 265 
	}
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	return const_ptr;
 266 
	return const_ptr;
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}
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}
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 268 
 
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	else
 494 
	else
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		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
 495 
		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
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477 
 
 496 
 
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	restart -= v_offset + h_offset;
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	restart -= v_offset + h_offset;
479 
 
 498 
 
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	DRM_DEBUG("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
 499 
	DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
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		  const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
 500 
		  const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
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 501 
 
483 
	tv_dac->tv.hrestart = restart % h_total;
 502 
	tv_dac->tv.hrestart = restart % h_total;
484 
	restart /= h_total;
 503 
	restart /= h_total;
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	tv_dac->tv.vrestart = restart % v_total;
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	tv_dac->tv.vrestart = restart % v_total;
486 
	restart /= v_total;
 505 
	restart /= v_total;
487 
	tv_dac->tv.frestart = restart % f_total;
 506 
	tv_dac->tv.frestart = restart % f_total;
488 
 
 507 
 
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	DRM_DEBUG("compute_restart: F/H/V=%u,%u,%u\n",
 508 
	DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n",
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			      (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
 521 
			      (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
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 522 
 
504 
	tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
 523 
	tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
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		((u32)h_inc << RADEON_H_INC_SHIFT);
 524 
		((u32)h_inc << RADEON_H_INC_SHIFT);
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506 
 
 525 
 
507 
	DRM_DEBUG("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
 526 
	DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
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 527 
 
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621 
	} else {
 640 
	} else {
622 
		tmp /= PAL_TV_LINES_PER_FRAME;
 641 
		tmp /= PAL_TV_LINES_PER_FRAME;
623 
	}
 642 
	}
624 
	flicker_removal = (tmp + 500) / 1000;
 643 
	flicker_removal = (tmp + 500) / 1000;
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 644 
 
626 
	if (flicker_removal < 2)
 645 
	if (flicker_removal < 3)
627 
		flicker_removal = 2;
 646 
		flicker_removal = 3;
628 
	for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
 647 
	for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
629 
		if (flicker_removal == SLOPE_limit[i])
 648 
		if (flicker_removal == SLOPE_limit[i])
630 
			break;
 649 
			break;
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		if (pll_ref_freq == 2700) {
 702 
		if (pll_ref_freq == 2700) {
684 
			m = PAL_TV_PLL_M_27;
 703 
			m = PAL_TV_PLL_M_27;
685 
			n = PAL_TV_PLL_N_27;
 704 
			n = PAL_TV_PLL_N_27;
686 
			p = PAL_TV_PLL_P_27;
 705 
			p = PAL_TV_PLL_P_27;
687 
		} else {
 706 
		} else {
688 
			m = PAL_TV_PLL_M_27;
 707 
			m = PAL_TV_PLL_M_14;
689 
			n = PAL_TV_PLL_N_27;
 708 
			n = PAL_TV_PLL_N_14;
690 
			p = PAL_TV_PLL_P_27;
 709 
			p = PAL_TV_PLL_P_14;
691 
		}
 710 
		}
692 
	}
 711 
	}
Line 693... Line 712...
693 
 
 712 
 
694 
	tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
 713 
	tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |