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Rev 1963 Rev 2997
Line 204... Line 204...
204 
	WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 204 
	WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
205 
	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 205 
	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
206 
	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 206 
	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
207 
}
 207 
}
Line 208... Line -...
208 
 
 - 
 
209 
void radeon_restore_common_regs(struct drm_device *dev)
 - 
 
210 
{
 - 
 
211 
	/* don't need this yet */
 - 
 
212 
}
 - 
 
213 
 
 208 
 
214 
static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 209 
static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
215 
{
 210 
{
216 
	struct radeon_device *rdev = dev->dev_private;
 211 
	struct radeon_device *rdev = dev->dev_private;
Line 293... Line 288...
293 
		 * [0..180) MHz : 1
 288 
		 * [0..180) MHz : 1
294 
		 */
 289 
		 */
295 
		return 1;
 290 
		return 1;
296 
}
 291 
}
Line 297... Line 292...
297 
 
 292 
 
298 
void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 293 
static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
299 
{
 294 
{
300 
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 295 
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301 
	struct drm_device *dev = crtc->dev;
 296 
	struct drm_device *dev = crtc->dev;
302 
	struct radeon_device *rdev = dev->dev_private;
 297 
	struct radeon_device *rdev = dev->dev_private;
Line 417... Line 412...
417 
	obj = radeon_fb->obj;
 412 
	obj = radeon_fb->obj;
418 
	rbo = gem_to_radeon_bo(obj);
 413 
	rbo = gem_to_radeon_bo(obj);
419 
	r = radeon_bo_reserve(rbo, false);
 414 
	r = radeon_bo_reserve(rbo, false);
420 
	if (unlikely(r != 0))
 415 
	if (unlikely(r != 0))
421 
		return r;
 416 
		return r;
- 
 
 417 
	/* Only 27 bit offset for legacy CRTC */
422 
	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 418 
	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
423 
	if (unlikely(r != 0)) {
 419 
	if (unlikely(r != 0)) {
424 
		radeon_bo_unreserve(rbo);
 420 
		radeon_bo_unreserve(rbo);
425 
		return -EINVAL;
 421 
		return -EINVAL;
426 
	}
 422 
	}
Line 435... Line 431...
435 
 
 431 
 
Line 436... Line 432...
436 
	base -= radeon_crtc->legacy_display_base_addr;
 432 
	base -= radeon_crtc->legacy_display_base_addr;
Line 437... Line 433...
437 
 
 433 
 
438 
	crtc_offset_cntl = 0;
 434 
	crtc_offset_cntl = 0;
439 
 
 435 
 
440 
	pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
 436 
	pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
441 
	crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
 437 
	crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
Line 986... Line 982...
986 
			WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 982 
			WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
987 
	}
 983 
	}
988 
}
 984 
}
Line 989... Line 985...
989 
 
 985 
 
990 
static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
 986 
static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
991 
				   struct drm_display_mode *mode,
 987 
				   const struct drm_display_mode *mode,
992 
				   struct drm_display_mode *adjusted_mode)
 988 
				   struct drm_display_mode *adjusted_mode)
993 
{
 - 
 
994 
	struct drm_device *dev = crtc->dev;
 - 
 
995 
	struct radeon_device *rdev = dev->dev_private;
 - 
 
996 
 
 - 
 
997 
	/* adjust pm to upcoming mode change */
 - 
 
998 
	radeon_pm_compute_clocks(rdev);
 - 
 
999 
 
 989 
{
1000 
	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
 990 
	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1001 
		return false;
 991 
		return false;
1002 
	return true;
 992 
	return true;
Line 1027... Line 1017...
1027 
	return 0;
 1017 
	return 0;
1028 
}
 1018 
}
Line 1029... Line 1019...
1029 
 
 1019 
 
1030 
static void radeon_crtc_prepare(struct drm_crtc *crtc)
 1020 
static void radeon_crtc_prepare(struct drm_crtc *crtc)
- 
 
 1021 
{
1031 
{
 1022 
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1032 
	struct drm_device *dev = crtc->dev;
 1023 
	struct drm_device *dev = crtc->dev;
Line -... Line 1024...
- 
 
 1024 
	struct drm_crtc *crtci;
1033 
	struct drm_crtc *crtci;
 1025 
 
1034 
 
 1026 
	radeon_crtc->in_mode_set = true;
1035 
	/*
 1027 
	/*
1036 
	* The hardware wedges sometimes if you reconfigure one CRTC
 1028 
	* The hardware wedges sometimes if you reconfigure one CRTC
1037 
	* whilst another is running (see fdo bug #24611).
 1029 
	* whilst another is running (see fdo bug #24611).
1038 
	*/
 1030 
	*/
1039 
	list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
 1031 
	list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
Line 1040... Line 1032...
1040 
		radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
 1032 
		radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1041 
}
 1033 
}
- 
 
 1034 
 
1042 
 
 1035 
static void radeon_crtc_commit(struct drm_crtc *crtc)
1043 
static void radeon_crtc_commit(struct drm_crtc *crtc)
 1036 
{
Line 1044... Line 1037...
1044 
{
 1037 
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1045 
	struct drm_device *dev = crtc->dev;
 1038 
	struct drm_device *dev = crtc->dev;
1046 
	struct drm_crtc *crtci;
 1039 
	struct drm_crtc *crtci;
1047 
 
 1040 
 
1048 
	/*
 1041 
	/*
1049 
	* Reenable the CRTCs that should be running.
 1042 
	* Reenable the CRTCs that should be running.
1050 
	*/
 1043 
	*/
- 
 
 1044 
	list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1051 
	list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
 1045 
		if (crtci->enabled)
Line 1052... Line 1046...
1052 
		if (crtci->enabled)
 1046 
			radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1053 
			radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
 1047 
	}
1054 
	}
 1048 
	radeon_crtc->in_mode_set = false;