WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_legacy_crtc.c


/*
 * Copyright 2007-8 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 */
#include 
#include 
#include 
#include 
#include "radeon.h"
#include "atom.h"
 
static void radeon_overscan_setup(struct drm_crtc *crtc,
				  struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
	WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
	WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
	WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
}
 
static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
				       struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	int xres = mode->hdisplay;
	int yres = mode->vdisplay;
	bool hscale = true, vscale = true;
	int hsync_wid;
	int vsync_wid;
	int hsync_start;
	int blank_width;
	u32 scale, inc, crtc_more_cntl;
	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
	struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
 
	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
		(RADEON_VERT_STRETCH_RESERVED |
		 RADEON_VERT_AUTO_RATIO_INC);
	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
		(RADEON_HORZ_FP_LOOP_STRETCH |
		 RADEON_HORZ_AUTO_RATIO_INC);
 
	crtc_more_cntl = 0;
	if ((rdev->family == CHIP_RS100) ||
	    (rdev->family == CHIP_RS200)) {
		/* This is to workaround the asic bug for RMX, some versions
		   of BIOS dosen't have this register initialized correctly. */
		crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
	}
 
 
	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
				| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 
	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
	if (!hsync_wid)
		hsync_wid = 1;
	hsync_start = mode->crtc_hsync_start - 8;
 
	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
			      | ((hsync_wid & 0x3f) << 16)
			      | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
				 ? RADEON_CRTC_H_SYNC_POL
				 : 0));
 
	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
				| ((mode->crtc_vdisplay - 1) << 16));
 
	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
	if (!vsync_wid)
		vsync_wid = 1;
 
	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
			      | ((vsync_wid & 0x1f) << 16)
			      | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
				 ? RADEON_CRTC_V_SYNC_POL
				 : 0));
 
	fp_horz_vert_active = 0;
 
	if (native_mode->hdisplay == 0 ||
	    native_mode->vdisplay == 0) {
		hscale = false;
		vscale = false;
	} else {
		if (xres > native_mode->hdisplay)
			xres = native_mode->hdisplay;
		if (yres > native_mode->vdisplay)
			yres = native_mode->vdisplay;
 
		if (xres == native_mode->hdisplay)
			hscale = false;
		if (yres == native_mode->vdisplay)
			vscale = false;
	}
 
	switch (radeon_crtc->rmx_type) {
	case RMX_FULL:
	case RMX_ASPECT:
		if (!hscale)
			fp_horz_stretch |= ((xres/8-1) << 16);
		else {
			inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
			scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
				/ native_mode->hdisplay + 1;
			fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
					RADEON_HORZ_STRETCH_BLEND |
					RADEON_HORZ_STRETCH_ENABLE |
					((native_mode->hdisplay/8-1) << 16));
		}
 
		if (!vscale)
			fp_vert_stretch |= ((yres-1) << 12);
		else {
			inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
			scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
				/ native_mode->vdisplay + 1;
			fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
					RADEON_VERT_STRETCH_ENABLE |
					RADEON_VERT_STRETCH_BLEND |
					((native_mode->vdisplay-1) << 12));
		}
		break;
	case RMX_CENTER:
		fp_horz_stretch |= ((xres/8-1) << 16);
		fp_vert_stretch |= ((yres-1) << 12);
 
		crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
				RADEON_CRTC_AUTO_VERT_CENTER_EN);
 
		blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
		if (blank_width > 110)
			blank_width = 110;
 
		fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
				| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 
		hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
		if (!hsync_wid)
			hsync_wid = 1;
 
		fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
				| ((hsync_wid & 0x3f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
					? RADEON_CRTC_H_SYNC_POL
					: 0));
 
		fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
				| ((mode->crtc_vdisplay - 1) << 16));
 
		vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
		if (!vsync_wid)
			vsync_wid = 1;
 
		fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
					| ((vsync_wid & 0x1f) << 16)
					| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
						? RADEON_CRTC_V_SYNC_POL
						: 0)));
 
		fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
				(((native_mode->hdisplay / 8) & 0x1ff) << 16));
		break;
	case RMX_OFF:
	default:
		fp_horz_stretch |= ((xres/8-1) << 16);
		fp_vert_stretch |= ((yres-1) << 12);
		break;
	}
 
	WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
	WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
	WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
	WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
	WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
	WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
}
 
void radeon_restore_common_regs(struct drm_device *dev)
{
	/* don't need this yet */
}
 
static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	int i = 0;
 
	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
	   the cause yet, but this workaround will mask the problem for now.
	   Other chips usually will pass at the very first test, so the
	   workaround shouldn't have any effect on them. */
	for (i = 0;
	     (i < 10000 &&
	      RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
	     i++);
}
 
static void radeon_pll_write_update(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
 
	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 
	WREG32_PLL_P(RADEON_PPLL_REF_DIV,
			   RADEON_PPLL_ATOMIC_UPDATE_W,
			   ~(RADEON_PPLL_ATOMIC_UPDATE_W));
}
 
static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	int i = 0;
 
 
	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
	   the cause yet, but this workaround will mask the problem for now.
	   Other chips usually will pass at the very first test, so the
	   workaround shouldn't have any effect on them. */
	for (i = 0;
	     (i < 10000 &&
	      RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
	     i++);
}
 
static void radeon_pll2_write_update(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
 
	while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 
	WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
			   RADEON_P2PLL_ATOMIC_UPDATE_W,
			   ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
}
 
static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
				       uint16_t fb_div)
{
	unsigned int vcoFreq;
 
	if (!ref_div)
		return 1;
 
	vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
 
	/*
	 * This is horribly crude: the VCO frequency range is divided into
	 * 3 parts, each part having a fixed PLL gain value.
	 */
	if (vcoFreq >= 30000)
		/*
		 * [300..max] MHz : 7
		 */
		return 7;
	else if (vcoFreq >= 18000)
		/*
		 * [180..300) MHz : 4
		 */
		return 4;
	else
		/*
		 * [0..180) MHz : 1
		 */
		return 1;
}
 
void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t mask;
 
	if (radeon_crtc->crtc_id)
		mask = (RADEON_CRTC2_DISP_DIS |
			RADEON_CRTC2_VSYNC_DIS |
			RADEON_CRTC2_HSYNC_DIS |
			RADEON_CRTC2_DISP_REQ_EN_B);
	else
		mask = (RADEON_CRTC_DISPLAY_DIS |
			RADEON_CRTC_VSYNC_DIS |
			RADEON_CRTC_HSYNC_DIS);
 
	switch (mode) {
	case DRM_MODE_DPMS_ON:
		radeon_crtc->enabled = true;
		/* adjust pm to dpms changes BEFORE enabling crtcs */
		radeon_pm_compute_clocks(rdev);
		if (radeon_crtc->crtc_id)
			WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
		else {
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
									 RADEON_CRTC_DISP_REQ_EN_B));
			WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
		}
		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
		radeon_crtc_load_lut(crtc);
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
		if (radeon_crtc->crtc_id)
			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
		else {
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
										    RADEON_CRTC_DISP_REQ_EN_B));
			WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
		}
		radeon_crtc->enabled = false;
		/* adjust pm to dpms changes AFTER disabling crtcs */
		radeon_pm_compute_clocks(rdev);
		break;
	}
}
 
int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
			 struct drm_framebuffer *old_fb)
{
	return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
}
 
int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
				struct drm_framebuffer *fb,
				int x, int y, enum mode_set_atomic state)
{
	return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
}
 
int radeon_crtc_do_set_base(struct drm_crtc *crtc,
			 struct drm_framebuffer *fb,
			 int x, int y, int atomic)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct radeon_framebuffer *radeon_fb;
	struct drm_framebuffer *target_fb;
	struct drm_gem_object *obj;
	struct radeon_bo *rbo;
	uint64_t base;
	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
	uint32_t crtc_pitch, pitch_pixels;
	uint32_t tiling_flags;
	int format;
	uint32_t gen_cntl_reg, gen_cntl_val;
	int r;
 
	DRM_DEBUG_KMS("\n");
	/* no fb bound */
	if (!atomic && !crtc->fb) {
		DRM_DEBUG_KMS("No FB bound\n");
		return 0;
	}
 
	if (atomic) {
		radeon_fb = to_radeon_framebuffer(fb);
		target_fb = fb;
	}
	else {
	radeon_fb = to_radeon_framebuffer(crtc->fb);
		target_fb = crtc->fb;
	}
 
	switch (target_fb->bits_per_pixel) {
	case 8:
		format = 2;
		break;
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return false;
	}
 
	/* Pin framebuffer & get tilling informations */
	obj = radeon_fb->obj;
	rbo = gem_to_radeon_bo(obj);
	r = radeon_bo_reserve(rbo, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
	if (unlikely(r != 0)) {
		radeon_bo_unreserve(rbo);
		return -EINVAL;
	}
	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
	radeon_bo_unreserve(rbo);
	if (tiling_flags & RADEON_TILING_MICRO)
		DRM_ERROR("trying to scanout microtiled buffer\n");
 
	/* if scanout was in GTT this really wouldn't work */
	/* crtc offset is from display base addr not FB location */
	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 
	base -= radeon_crtc->legacy_display_base_addr;
 
	crtc_offset_cntl = 0;
 
	pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
	crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
			((target_fb->bits_per_pixel * 8) - 1)) /
		       (target_fb->bits_per_pixel * 8));
 
	crtc_pitch |= crtc_pitch << 16;
 
	crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
	if (tiling_flags & RADEON_TILING_MACRO) {
		if (ASIC_IS_R300(rdev))
			crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
					     R300_CRTC_MICRO_TILE_BUFFER_DIS |
					     R300_CRTC_MACRO_TILE_EN);
		else
			crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
	} else {
		if (ASIC_IS_R300(rdev))
			crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
					      R300_CRTC_MICRO_TILE_BUFFER_DIS |
					      R300_CRTC_MACRO_TILE_EN);
		else
			crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
	}
 
	if (tiling_flags & RADEON_TILING_MACRO) {
		if (ASIC_IS_R300(rdev)) {
			crtc_tile_x0_y0 = x | (y << 16);
			base &= ~0x7ff;
		} else {
			int byteshift = target_fb->bits_per_pixel >> 4;
			int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
			base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
			crtc_offset_cntl |= (y % 16);
		}
	} else {
		int offset = y * pitch_pixels + x;
		switch (target_fb->bits_per_pixel) {
		case 8:
			offset *= 1;
			break;
		case 15:
		case 16:
			offset *= 2;
			break;
		case 24:
			offset *= 3;
			break;
		case 32:
			offset *= 4;
			break;
		default:
			return false;
		}
		base += offset;
	}
 
	base &= ~7;
 
	if (radeon_crtc->crtc_id == 1)
		gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
	else
		gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 
	gen_cntl_val = RREG32(gen_cntl_reg);
	gen_cntl_val &= ~(0xf << 8);
	gen_cntl_val |= (format << 8);
	gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
	WREG32(gen_cntl_reg, gen_cntl_val);
 
	crtc_offset = (u32)base;
 
	WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 
	if (ASIC_IS_R300(rdev)) {
		if (radeon_crtc->crtc_id)
			WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
		else
			WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
	}
	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 
	if (!atomic && fb && fb != crtc->fb) {
		radeon_fb = to_radeon_framebuffer(fb);
		rbo = gem_to_radeon_bo(radeon_fb->obj);
		r = radeon_bo_reserve(rbo, false);
		if (unlikely(r != 0))
			return r;
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
	}
 
	/* Bytes per pixel may have changed */
	radeon_bandwidth_update(rdev);
 
	return 0;
}
 
static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_encoder *encoder;
	int format;
	int hsync_start;
	int hsync_wid;
	int vsync_wid;
	uint32_t crtc_h_total_disp;
	uint32_t crtc_h_sync_strt_wid;
	uint32_t crtc_v_total_disp;
	uint32_t crtc_v_sync_strt_wid;
	bool is_tv = false;
 
	DRM_DEBUG_KMS("\n");
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
				is_tv = true;
				DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
				break;
			}
		}
	}
 
	switch (crtc->fb->bits_per_pixel) {
	case 8:
		format = 2;
		break;
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return false;
	}
 
	crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
			     | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 
	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
	if (!hsync_wid)
		hsync_wid = 1;
	hsync_start = mode->crtc_hsync_start - 8;
 
	crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
				| ((hsync_wid & 0x3f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
				   ? RADEON_CRTC_H_SYNC_POL
				   : 0));
 
	/* This works for double scan mode. */
	crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
			     | ((mode->crtc_vdisplay - 1) << 16));
 
	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
	if (!vsync_wid)
		vsync_wid = 1;
 
	crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
				| ((vsync_wid & 0x1f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
				   ? RADEON_CRTC_V_SYNC_POL
				   : 0));
 
	if (radeon_crtc->crtc_id) {
		uint32_t crtc2_gen_cntl;
		uint32_t disp2_merge_cntl;
 
		/* if TV DAC is enabled for another crtc and keep it enabled */
		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
		crtc2_gen_cntl |= ((format << 8)
				   | RADEON_CRTC2_VSYNC_DIS
				   | RADEON_CRTC2_HSYNC_DIS
				   | RADEON_CRTC2_DISP_DIS
				   | RADEON_CRTC2_DISP_REQ_EN_B
				   | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
				      ? RADEON_CRTC2_DBL_SCAN_EN
				      : 0)
				   | ((mode->flags & DRM_MODE_FLAG_CSYNC)
				      ? RADEON_CRTC2_CSYNC_EN
				      : 0)
				   | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
				      ? RADEON_CRTC2_INTERLACE_EN
				      : 0));
 
		/* rs4xx chips seem to like to have the crtc enabled when the timing is set */
		if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
			crtc2_gen_cntl |= RADEON_CRTC2_EN;
 
		disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
		disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 
		WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 
		WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
		WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
	} else {
		uint32_t crtc_gen_cntl;
		uint32_t crtc_ext_cntl;
		uint32_t disp_merge_cntl;
 
		crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
		crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
				 | (format << 8)
				 | RADEON_CRTC_DISP_REQ_EN_B
				 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
				    ? RADEON_CRTC_DBL_SCAN_EN
				    : 0)
				 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
				    ? RADEON_CRTC_CSYNC_EN
				    : 0)
				 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
				    ? RADEON_CRTC_INTERLACE_EN
				    : 0));
 
		/* rs4xx chips seem to like to have the crtc enabled when the timing is set */
		if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
			crtc_gen_cntl |= RADEON_CRTC_EN;
 
		crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
				  RADEON_CRTC_VSYNC_DIS |
				  RADEON_CRTC_HSYNC_DIS |
				  RADEON_CRTC_DISPLAY_DIS);
 
		disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 
		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
		WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
		WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
	}
 
	if (is_tv)
		radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
						 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
						 &crtc_v_sync_strt_wid);
 
	WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
	WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
	WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
	WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 
	return true;
}
 
static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_encoder *encoder;
	uint32_t feedback_div = 0;
	uint32_t frac_fb_div = 0;
	uint32_t reference_div = 0;
	uint32_t post_divider = 0;
	uint32_t freq = 0;
	uint8_t pll_gain;
	bool use_bios_divs = false;
	/* PLL registers */
	uint32_t pll_ref_div = 0;
	uint32_t pll_fb_post_div = 0;
	uint32_t htotal_cntl = 0;
	bool is_tv = false;
	struct radeon_pll *pll;
 
	struct {
		int divider;
		int bitvalue;
	} *post_div, post_divs[]   = {
		/* From RAGE 128 VR/RAGE 128 GL Register
		 * Reference Manual (Technical Reference
		 * Manual P/N RRG-G04100-C Rev. 0.04), page
		 * 3-17 (PLL_DIV_[3:0]).
		 */
		{  1, 0 },              /* VCLK_SRC                 */
		{  2, 1 },              /* VCLK_SRC/2               */
		{  4, 2 },              /* VCLK_SRC/4               */
		{  8, 3 },              /* VCLK_SRC/8               */
		{  3, 4 },              /* VCLK_SRC/3               */
		{ 16, 5 },              /* VCLK_SRC/16              */
		{  6, 6 },              /* VCLK_SRC/6               */
		{ 12, 7 },              /* VCLK_SRC/12              */
		{  0, 0 }
	};
 
	if (radeon_crtc->crtc_id)
		pll = &rdev->clock.p2pll;
	else
		pll = &rdev->clock.p1pll;
 
	pll->flags = RADEON_PLL_LEGACY;
 
 
 
 
 
	if (mode->clock > 200000) /* range limits??? */
		pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
	else
		pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 
			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
				is_tv = true;
				break;
			}
 
			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
				pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
			if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
				if (!rdev->is_atom_bios) {
				struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
				struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
				if (lvds) {
					if (lvds->use_bios_dividers) {
						pll_ref_div = lvds->panel_ref_divider;
						pll_fb_post_div   = (lvds->panel_fb_divider |
								     (lvds->panel_post_divider << 16));
						htotal_cntl  = 0;
						use_bios_divs = true;
					}
				}
				}
				pll->flags |= RADEON_PLL_USE_REF_DIV;
			}
		}
	}
 
	DRM_DEBUG_KMS("\n");
 
	if (!use_bios_divs) {
		radeon_compute_pll_legacy(pll, mode->clock,
				   &freq, &feedback_div, &frac_fb_div,
				   &reference_div, &post_divider);
 
		for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
			if (post_div->divider == post_divider)
				break;
		}
 
		if (!post_div->divider)
			post_div = &post_divs[0];
 
		DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
			  (unsigned)freq,
			  feedback_div,
			  reference_div,
			  post_divider);
 
		pll_ref_div   = reference_div;
#if defined(__powerpc__) && (0) /* TODO */
		/* apparently programming this otherwise causes a hang??? */
		if (info->MacModel == RADEON_MAC_IBOOK)
			pll_fb_post_div = 0x000600ad;
		else
#endif
			pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 
		htotal_cntl    = mode->htotal & 0x7;
 
	}
 
	pll_gain = radeon_compute_pll_gain(pll->reference_freq,
					   pll_ref_div & 0x3ff,
					   pll_fb_post_div & 0x7ff);
 
	if (radeon_crtc->crtc_id) {
		uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
					  ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
					 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 
		if (is_tv) {
			radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
						     &pll_ref_div, &pll_fb_post_div,
						     &pixclks_cntl);
		}
 
		WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
			     RADEON_PIX2CLK_SRC_SEL_CPUCLK,
			     ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 
		WREG32_PLL_P(RADEON_P2PLL_CNTL,
			     RADEON_P2PLL_RESET
			     | RADEON_P2PLL_ATOMIC_UPDATE_EN
			     | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
			     ~(RADEON_P2PLL_RESET
			       | RADEON_P2PLL_ATOMIC_UPDATE_EN
			       | RADEON_P2PLL_PVG_MASK));
 
		WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
			     pll_ref_div,
			     ~RADEON_P2PLL_REF_DIV_MASK);
 
		WREG32_PLL_P(RADEON_P2PLL_DIV_0,
			     pll_fb_post_div,
			     ~RADEON_P2PLL_FB0_DIV_MASK);
 
		WREG32_PLL_P(RADEON_P2PLL_DIV_0,
			     pll_fb_post_div,
			     ~RADEON_P2PLL_POST0_DIV_MASK);
 
		radeon_pll2_write_update(dev);
		radeon_pll2_wait_for_read_update_complete(dev);
 
		WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 
		WREG32_PLL_P(RADEON_P2PLL_CNTL,
			     0,
			     ~(RADEON_P2PLL_RESET
			       | RADEON_P2PLL_SLEEP
			       | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 
		DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
			  (unsigned)pll_ref_div,
			  (unsigned)pll_fb_post_div,
			  (unsigned)htotal_cntl,
			  RREG32_PLL(RADEON_P2PLL_CNTL));
		DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
			  (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
			  (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
			  (unsigned)((pll_fb_post_div &
				      RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 
		mdelay(50); /* Let the clock to lock */
 
		WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
			     RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
			     ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 
		WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
	} else {
		uint32_t pixclks_cntl;
 
 
		if (is_tv) {
			pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
			radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
						     &pll_fb_post_div, &pixclks_cntl);
		}
 
		if (rdev->flags & RADEON_IS_MOBILITY) {
			/* A temporal workaround for the occasional blanking on certain laptop panels.
			   This appears to related to the PLL divider registers (fail to lock?).
			   It occurs even when all dividers are the same with their old settings.
			   In this case we really don't need to fiddle with PLL registers.
			   By doing this we can avoid the blanking problem with some panels.
			*/
			if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
			    (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
						 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
				WREG32_P(RADEON_CLOCK_CNTL_INDEX,
					 RADEON_PLL_DIV_SEL,
					 ~(RADEON_PLL_DIV_SEL));
				r100_pll_errata_after_index(rdev);
				return;
			}
		}
 
		WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
			     RADEON_VCLK_SRC_SEL_CPUCLK,
			     ~(RADEON_VCLK_SRC_SEL_MASK));
		WREG32_PLL_P(RADEON_PPLL_CNTL,
			     RADEON_PPLL_RESET
			     | RADEON_PPLL_ATOMIC_UPDATE_EN
			     | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
			     | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
			     ~(RADEON_PPLL_RESET
			       | RADEON_PPLL_ATOMIC_UPDATE_EN
			       | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
			       | RADEON_PPLL_PVG_MASK));
 
		WREG32_P(RADEON_CLOCK_CNTL_INDEX,
			 RADEON_PLL_DIV_SEL,
			 ~(RADEON_PLL_DIV_SEL));
		r100_pll_errata_after_index(rdev);
 
		if (ASIC_IS_R300(rdev) ||
		    (rdev->family == CHIP_RS300) ||
		    (rdev->family == CHIP_RS400) ||
		    (rdev->family == CHIP_RS480)) {
			if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
				/* When restoring console mode, use saved PPLL_REF_DIV
				 * setting.
				 */
				WREG32_PLL_P(RADEON_PPLL_REF_DIV,
					     pll_ref_div,
					     0);
			} else {
				/* R300 uses ref_div_acc field as real ref divider */
				WREG32_PLL_P(RADEON_PPLL_REF_DIV,
					     (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
					     ~R300_PPLL_REF_DIV_ACC_MASK);
			}
		} else
			WREG32_PLL_P(RADEON_PPLL_REF_DIV,
				     pll_ref_div,
				     ~RADEON_PPLL_REF_DIV_MASK);
 
		WREG32_PLL_P(RADEON_PPLL_DIV_3,
			     pll_fb_post_div,
			     ~RADEON_PPLL_FB3_DIV_MASK);
 
		WREG32_PLL_P(RADEON_PPLL_DIV_3,
			     pll_fb_post_div,
			     ~RADEON_PPLL_POST3_DIV_MASK);
 
		radeon_pll_write_update(dev);
		radeon_pll_wait_for_read_update_complete(dev);
 
		WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 
		WREG32_PLL_P(RADEON_PPLL_CNTL,
			     0,
			     ~(RADEON_PPLL_RESET
			       | RADEON_PPLL_SLEEP
			       | RADEON_PPLL_ATOMIC_UPDATE_EN
			       | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 
		DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
			  pll_ref_div,
			  pll_fb_post_div,
			  (unsigned)htotal_cntl,
			  RREG32_PLL(RADEON_PPLL_CNTL));
		DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
			  pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
			  pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
			  (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 
		mdelay(50); /* Let the clock to lock */
 
		WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
			     RADEON_VCLK_SRC_SEL_PPLLCLK,
			     ~(RADEON_VCLK_SRC_SEL_MASK));
 
		if (is_tv)
			WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
	}
}
 
static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
				   struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
 
	/* adjust pm to upcoming mode change */
	radeon_pm_compute_clocks(rdev);
 
	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
		return false;
	return true;
}
 
static int radeon_crtc_mode_set(struct drm_crtc *crtc,
				 struct drm_display_mode *mode,
				 struct drm_display_mode *adjusted_mode,
				 int x, int y, struct drm_framebuffer *old_fb)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
	/* TODO TV */
	radeon_crtc_set_base(crtc, x, y, old_fb);
	radeon_set_crtc_timing(crtc, adjusted_mode);
	radeon_set_pll(crtc, adjusted_mode);
	radeon_overscan_setup(crtc, adjusted_mode);
	if (radeon_crtc->crtc_id == 0) {
		radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
	} else {
		if (radeon_crtc->rmx_type != RMX_OFF) {
			/* FIXME: only first crtc has rmx what should we
			 * do ?
			 */
			DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
		}
	}
	return 0;
}
 
static void radeon_crtc_prepare(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_crtc *crtci;
 
	/*
	* The hardware wedges sometimes if you reconfigure one CRTC
	* whilst another is running (see fdo bug #24611).
	*/
	list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
		radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
}
 
static void radeon_crtc_commit(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_crtc *crtci;
 
	/*
	* Reenable the CRTCs that should be running.
	*/
	list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
		if (crtci->enabled)
			radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
	}
}
 
static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
	.dpms = radeon_crtc_dpms,
	.mode_fixup = radeon_crtc_mode_fixup,
	.mode_set = radeon_crtc_mode_set,
	.mode_set_base = radeon_crtc_set_base,
	.mode_set_base_atomic = radeon_crtc_set_base_atomic,
	.prepare = radeon_crtc_prepare,
	.commit = radeon_crtc_commit,
	.load_lut = radeon_crtc_load_lut,
};
 
 
void radeon_legacy_init_crtc(struct drm_device *dev,
			       struct radeon_crtc *radeon_crtc)
{
	if (radeon_crtc->crtc_id == 1)
		radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
	drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
}

Rev 1430	Rev 1963
1	/*	1	/*
2	* Copyright 2007-8 Advanced Micro Devices, Inc.	2	* Copyright 2007-8 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the "Software"),	6	* copy of this software and associated documentation files (the "Software"),
7	* to deal in the Software without restriction, including without limitation	7	* to deal in the Software without restriction, including without limitation
8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9	* and/or sell copies of the Software, and to permit persons to whom the	9	* and/or sell copies of the Software, and to permit persons to whom the
10	* Software is furnished to do so, subject to the following conditions:	10	* Software is furnished to do so, subject to the following conditions:
11	*	11	*
12	* The above copyright notice and this permission notice shall be included in	12	* The above copyright notice and this permission notice shall be included in
13	* all copies or substantial portions of the Software.	13	* all copies or substantial portions of the Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21	* OTHER DEALINGS IN THE SOFTWARE.	21	* OTHER DEALINGS IN THE SOFTWARE.
22	*	22	*
23	* Authors: Dave Airlie	23	* Authors: Dave Airlie
24	* Alex Deucher	24	* Alex Deucher
25	*/	25	*/
26	#include	26	#include
27	#include	27	#include
28	#include	28	#include
29	#include "radeon_fixed.h"	29	#include
30	#include "radeon.h"	30	#include "radeon.h"
31	#include "atom.h"	31	#include "atom.h"
32		32
33	static void radeon_overscan_setup(struct drm_crtc *crtc,	33	static void radeon_overscan_setup(struct drm_crtc *crtc,
34	struct drm_display_mode *mode)	34	struct drm_display_mode *mode)
35	{	35	{
36	struct drm_device *dev = crtc->dev;	36	struct drm_device *dev = crtc->dev;
37	struct radeon_device *rdev = dev->dev_private;	37	struct radeon_device *rdev = dev->dev_private;
38	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	38	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39		39
40	WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);	40	WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
41	WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);	41	WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
42	WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);	42	WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
43	}	43	}
44		44
45	static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,	45	static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
46	struct drm_display_mode *mode)	46	struct drm_display_mode *mode)
47	{	47	{
48	struct drm_device *dev = crtc->dev;	48	struct drm_device *dev = crtc->dev;
49	struct radeon_device *rdev = dev->dev_private;	49	struct radeon_device *rdev = dev->dev_private;
50	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	50	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
51	int xres = mode->hdisplay;	51	int xres = mode->hdisplay;
52	int yres = mode->vdisplay;	52	int yres = mode->vdisplay;
53	bool hscale = true, vscale = true;	53	bool hscale = true, vscale = true;
54	int hsync_wid;	54	int hsync_wid;
55	int vsync_wid;	55	int vsync_wid;
56	int hsync_start;	56	int hsync_start;
57	int blank_width;	57	int blank_width;
58	u32 scale, inc, crtc_more_cntl;	58	u32 scale, inc, crtc_more_cntl;
59	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;	59	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
60	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;	60	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
61	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;	61	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
62	struct drm_display_mode *native_mode = &radeon_crtc->native_mode;	62	struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
63		63
64	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &	64	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
65	(RADEON_VERT_STRETCH_RESERVED \|	65	(RADEON_VERT_STRETCH_RESERVED \|
66	RADEON_VERT_AUTO_RATIO_INC);	66	RADEON_VERT_AUTO_RATIO_INC);
67	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &	67	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
68	(RADEON_HORZ_FP_LOOP_STRETCH \|	68	(RADEON_HORZ_FP_LOOP_STRETCH \|
69	RADEON_HORZ_AUTO_RATIO_INC);	69	RADEON_HORZ_AUTO_RATIO_INC);
70		70
71	crtc_more_cntl = 0;	71	crtc_more_cntl = 0;
72	if ((rdev->family == CHIP_RS100) \|\|	72	if ((rdev->family == CHIP_RS100) \|\|
73	(rdev->family == CHIP_RS200)) {	73	(rdev->family == CHIP_RS200)) {
74	/* This is to workaround the asic bug for RMX, some versions	74	/* This is to workaround the asic bug for RMX, some versions
75	of BIOS dosen't have this register initialized correctly. */	75	of BIOS dosen't have this register initialized correctly. */
76	crtc_more_cntl \|= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;	76	crtc_more_cntl \|= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
77	}	77	}
78		78
79		79
80	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)	80	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
81	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));	81	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
82		82
83	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;	83	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
84	if (!hsync_wid)	84	if (!hsync_wid)
85	hsync_wid = 1;	85	hsync_wid = 1;
86	hsync_start = mode->crtc_hsync_start - 8;	86	hsync_start = mode->crtc_hsync_start - 8;
87		87
88	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)	88	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
89	\| ((hsync_wid & 0x3f) << 16)	89	\| ((hsync_wid & 0x3f) << 16)
90	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)	90	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
91	? RADEON_CRTC_H_SYNC_POL	91	? RADEON_CRTC_H_SYNC_POL
92	: 0));	92	: 0));
93		93
94	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)	94	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
95	\| ((mode->crtc_vdisplay - 1) << 16));	95	\| ((mode->crtc_vdisplay - 1) << 16));
96		96
97	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;	97	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
98	if (!vsync_wid)	98	if (!vsync_wid)
99	vsync_wid = 1;	99	vsync_wid = 1;
100		100
101	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)	101	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
102	\| ((vsync_wid & 0x1f) << 16)	102	\| ((vsync_wid & 0x1f) << 16)
103	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)	103	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
104	? RADEON_CRTC_V_SYNC_POL	104	? RADEON_CRTC_V_SYNC_POL
105	: 0));	105	: 0));
106		106
107	fp_horz_vert_active = 0;	107	fp_horz_vert_active = 0;
108		108
109	if (native_mode->hdisplay == 0 \|\|	109	if (native_mode->hdisplay == 0 \|\|
110	native_mode->vdisplay == 0) {	110	native_mode->vdisplay == 0) {
111	hscale = false;	111	hscale = false;
112	vscale = false;	112	vscale = false;
113	} else {	113	} else {
114	if (xres > native_mode->hdisplay)	114	if (xres > native_mode->hdisplay)
115	xres = native_mode->hdisplay;	115	xres = native_mode->hdisplay;
116	if (yres > native_mode->vdisplay)	116	if (yres > native_mode->vdisplay)
117	yres = native_mode->vdisplay;	117	yres = native_mode->vdisplay;
118		118
119	if (xres == native_mode->hdisplay)	119	if (xres == native_mode->hdisplay)
120	hscale = false;	120	hscale = false;
121	if (yres == native_mode->vdisplay)	121	if (yres == native_mode->vdisplay)
122	vscale = false;	122	vscale = false;
123	}	123	}
124		124
125	switch (radeon_crtc->rmx_type) {	125	switch (radeon_crtc->rmx_type) {
126	case RMX_FULL:	126	case RMX_FULL:
127	case RMX_ASPECT:	127	case RMX_ASPECT:
128	if (!hscale)	128	if (!hscale)
129	fp_horz_stretch \|= ((xres/8-1) << 16);	129	fp_horz_stretch \|= ((xres/8-1) << 16);
130	else {	130	else {
131	inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;	131	inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
132	scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)	132	scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
133	/ native_mode->hdisplay + 1;	133	/ native_mode->hdisplay + 1;
134	fp_horz_stretch \|= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) \|	134	fp_horz_stretch \|= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) \|
135	RADEON_HORZ_STRETCH_BLEND \|	135	RADEON_HORZ_STRETCH_BLEND \|
136	RADEON_HORZ_STRETCH_ENABLE \|	136	RADEON_HORZ_STRETCH_ENABLE \|
137	((native_mode->hdisplay/8-1) << 16));	137	((native_mode->hdisplay/8-1) << 16));
138	}	138	}
139		139
140	if (!vscale)	140	if (!vscale)
141	fp_vert_stretch \|= ((yres-1) << 12);	141	fp_vert_stretch \|= ((yres-1) << 12);
142	else {	142	else {
143	inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;	143	inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
144	scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)	144	scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
145	/ native_mode->vdisplay + 1;	145	/ native_mode->vdisplay + 1;
146	fp_vert_stretch \|= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) \|	146	fp_vert_stretch \|= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) \|
147	RADEON_VERT_STRETCH_ENABLE \|	147	RADEON_VERT_STRETCH_ENABLE \|
148	RADEON_VERT_STRETCH_BLEND \|	148	RADEON_VERT_STRETCH_BLEND \|
149	((native_mode->vdisplay-1) << 12));	149	((native_mode->vdisplay-1) << 12));
150	}	150	}
151	break;	151	break;
152	case RMX_CENTER:	152	case RMX_CENTER:
153	fp_horz_stretch \|= ((xres/8-1) << 16);	153	fp_horz_stretch \|= ((xres/8-1) << 16);
154	fp_vert_stretch \|= ((yres-1) << 12);	154	fp_vert_stretch \|= ((yres-1) << 12);
155		155
156	crtc_more_cntl \|= (RADEON_CRTC_AUTO_HORZ_CENTER_EN \|	156	crtc_more_cntl \|= (RADEON_CRTC_AUTO_HORZ_CENTER_EN \|
157	RADEON_CRTC_AUTO_VERT_CENTER_EN);	157	RADEON_CRTC_AUTO_VERT_CENTER_EN);
158		158
159	blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;	159	blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
160	if (blank_width > 110)	160	if (blank_width > 110)
161	blank_width = 110;	161	blank_width = 110;
162		162
163	fp_crtc_h_total_disp = (((blank_width) & 0x3ff)	163	fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
164	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));	164	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
165		165
166	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;	166	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
167	if (!hsync_wid)	167	if (!hsync_wid)
168	hsync_wid = 1;	168	hsync_wid = 1;
169		169
170	fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)	170	fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
171	\| ((hsync_wid & 0x3f) << 16)	171	\| ((hsync_wid & 0x3f) << 16)
172	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)	172	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
173	? RADEON_CRTC_H_SYNC_POL	173	? RADEON_CRTC_H_SYNC_POL
174	: 0));	174	: 0));
175		175
176	fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)	176	fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
177	\| ((mode->crtc_vdisplay - 1) << 16));	177	\| ((mode->crtc_vdisplay - 1) << 16));
178		178
179	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;	179	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
180	if (!vsync_wid)	180	if (!vsync_wid)
181	vsync_wid = 1;	181	vsync_wid = 1;
182		182
183	fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)	183	fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
184	\| ((vsync_wid & 0x1f) << 16)	184	\| ((vsync_wid & 0x1f) << 16)
185	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)	185	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
186	? RADEON_CRTC_V_SYNC_POL	186	? RADEON_CRTC_V_SYNC_POL
187	: 0)));	187	: 0)));
188		188
189	fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) \|	189	fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) \|
190	(((native_mode->hdisplay / 8) & 0x1ff) << 16));	190	(((native_mode->hdisplay / 8) & 0x1ff) << 16));
191	break;	191	break;
192	case RMX_OFF:	192	case RMX_OFF:
193	default:	193	default:
194	fp_horz_stretch \|= ((xres/8-1) << 16);	194	fp_horz_stretch \|= ((xres/8-1) << 16);
195	fp_vert_stretch \|= ((yres-1) << 12);	195	fp_vert_stretch \|= ((yres-1) << 12);
196	break;	196	break;
197	}	197	}
198		198
199	WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);	199	WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
200	WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);	200	WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
201	WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);	201	WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
202	WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);	202	WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
203	WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);	203	WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
204	WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);	204	WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
205	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);	205	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
206	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);	206	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
207	}	207	}
208		208
209	void radeon_restore_common_regs(struct drm_device *dev)	209	void radeon_restore_common_regs(struct drm_device *dev)
210	{	210	{
211	/* don't need this yet */	211	/* don't need this yet */
212	}	212	}
213		213
214	static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)	214	static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
215	{	215	{
216	struct radeon_device *rdev = dev->dev_private;	216	struct radeon_device *rdev = dev->dev_private;
217	int i = 0;	217	int i = 0;
218		218
219	/* FIXME: Certain revisions of R300 can't recover here. Not sure of	219	/* FIXME: Certain revisions of R300 can't recover here. Not sure of
220	the cause yet, but this workaround will mask the problem for now.	220	the cause yet, but this workaround will mask the problem for now.
221	Other chips usually will pass at the very first test, so the	221	Other chips usually will pass at the very first test, so the
222	workaround shouldn't have any effect on them. */	222	workaround shouldn't have any effect on them. */
223	for (i = 0;	223	for (i = 0;
224	(i < 10000 &&	224	(i < 10000 &&
225	RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);	225	RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
226	i++);	226	i++);
227	}	227	}
228		228
229	static void radeon_pll_write_update(struct drm_device *dev)	229	static void radeon_pll_write_update(struct drm_device *dev)
230	{	230	{
231	struct radeon_device *rdev = dev->dev_private;	231	struct radeon_device *rdev = dev->dev_private;
232		232
233	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);	233	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
234		234
235	WREG32_PLL_P(RADEON_PPLL_REF_DIV,	235	WREG32_PLL_P(RADEON_PPLL_REF_DIV,
236	RADEON_PPLL_ATOMIC_UPDATE_W,	236	RADEON_PPLL_ATOMIC_UPDATE_W,
237	~(RADEON_PPLL_ATOMIC_UPDATE_W));	237	~(RADEON_PPLL_ATOMIC_UPDATE_W));
238	}	238	}
239		239
240	static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)	240	static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
241	{	241	{
242	struct radeon_device *rdev = dev->dev_private;	242	struct radeon_device *rdev = dev->dev_private;
243	int i = 0;	243	int i = 0;
244		244
245		245
246	/* FIXME: Certain revisions of R300 can't recover here. Not sure of	246	/* FIXME: Certain revisions of R300 can't recover here. Not sure of
247	the cause yet, but this workaround will mask the problem for now.	247	the cause yet, but this workaround will mask the problem for now.
248	Other chips usually will pass at the very first test, so the	248	Other chips usually will pass at the very first test, so the
249	workaround shouldn't have any effect on them. */	249	workaround shouldn't have any effect on them. */
250	for (i = 0;	250	for (i = 0;
251	(i < 10000 &&	251	(i < 10000 &&
252	RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);	252	RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
253	i++);	253	i++);
254	}	254	}
255		255
256	static void radeon_pll2_write_update(struct drm_device *dev)	256	static void radeon_pll2_write_update(struct drm_device *dev)
257	{	257	{
258	struct radeon_device *rdev = dev->dev_private;	258	struct radeon_device *rdev = dev->dev_private;
259		259
260	while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);	260	while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
261		261
262	WREG32_PLL_P(RADEON_P2PLL_REF_DIV,	262	WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
263	RADEON_P2PLL_ATOMIC_UPDATE_W,	263	RADEON_P2PLL_ATOMIC_UPDATE_W,
264	~(RADEON_P2PLL_ATOMIC_UPDATE_W));	264	~(RADEON_P2PLL_ATOMIC_UPDATE_W));
265	}	265	}
266		266
267	static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,	267	static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
268	uint16_t fb_div)	268	uint16_t fb_div)
269	{	269	{
270	unsigned int vcoFreq;	270	unsigned int vcoFreq;
271		271
272	if (!ref_div)	272	if (!ref_div)
273	return 1;	273	return 1;
274		274
275	vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;	275	vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
276		276
277	/*	277	/*
278	* This is horribly crude: the VCO frequency range is divided into	278	* This is horribly crude: the VCO frequency range is divided into
279	* 3 parts, each part having a fixed PLL gain value.	279	* 3 parts, each part having a fixed PLL gain value.
280	*/	280	*/
281	if (vcoFreq >= 30000)	281	if (vcoFreq >= 30000)
282	/*	282	/*
283	* [300..max] MHz : 7	283	* [300..max] MHz : 7
284	*/	284	*/
285	return 7;	285	return 7;
286	else if (vcoFreq >= 18000)	286	else if (vcoFreq >= 18000)
287	/*	287	/*
288	* [180..300) MHz : 4	288	* [180..300) MHz : 4
289	*/	289	*/
290	return 4;	290	return 4;
291	else	291	else
292	/*	292	/*
293	* [0..180) MHz : 1	293	* [0..180) MHz : 1
294	*/	294	*/
295	return 1;	295	return 1;
296	}	296	}
297		297
298	void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)	298	void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
299	{	299	{
300	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	300	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301	struct drm_device *dev = crtc->dev;	301	struct drm_device *dev = crtc->dev;
302	struct radeon_device *rdev = dev->dev_private;	302	struct radeon_device *rdev = dev->dev_private;
303	uint32_t mask;	303	uint32_t mask;
304		304
305	if (radeon_crtc->crtc_id)	305	if (radeon_crtc->crtc_id)
306	mask = (RADEON_CRTC2_DISP_DIS \|	306	mask = (RADEON_CRTC2_DISP_DIS \|
307	RADEON_CRTC2_VSYNC_DIS \|	307	RADEON_CRTC2_VSYNC_DIS \|
308	RADEON_CRTC2_HSYNC_DIS \|	308	RADEON_CRTC2_HSYNC_DIS \|
309	RADEON_CRTC2_DISP_REQ_EN_B);	309	RADEON_CRTC2_DISP_REQ_EN_B);
310	else	310	else
311	mask = (RADEON_CRTC_DISPLAY_DIS \|	311	mask = (RADEON_CRTC_DISPLAY_DIS \|
312	RADEON_CRTC_VSYNC_DIS \|	312	RADEON_CRTC_VSYNC_DIS \|
313	RADEON_CRTC_HSYNC_DIS);	313	RADEON_CRTC_HSYNC_DIS);
314		314
315	switch (mode) {	315	switch (mode) {
316	case DRM_MODE_DPMS_ON:	316	case DRM_MODE_DPMS_ON:
-		317	radeon_crtc->enabled = true;
-		318	/* adjust pm to dpms changes BEFORE enabling crtcs */
-		319	radeon_pm_compute_clocks(rdev);
317	if (radeon_crtc->crtc_id)	320	if (radeon_crtc->crtc_id)
318	WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN \| mask));	321	WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN \| mask));
319	else {	322	else {
320	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN \|	323	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN \|
321	RADEON_CRTC_DISP_REQ_EN_B));	324	RADEON_CRTC_DISP_REQ_EN_B));
322	WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);	325	WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
323	}	326	}
324	drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);	327	drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
325	radeon_crtc_load_lut(crtc);	328	radeon_crtc_load_lut(crtc);
326	break;	329	break;
327	case DRM_MODE_DPMS_STANDBY:	330	case DRM_MODE_DPMS_STANDBY:
328	case DRM_MODE_DPMS_SUSPEND:	331	case DRM_MODE_DPMS_SUSPEND:
329	case DRM_MODE_DPMS_OFF:	332	case DRM_MODE_DPMS_OFF:
330	drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);	333	drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
331	if (radeon_crtc->crtc_id)	334	if (radeon_crtc->crtc_id)
332	WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN \| mask));	335	WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN \| mask));
333	else {	336	else {
334	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN \|	337	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN \|
335	RADEON_CRTC_DISP_REQ_EN_B));	338	RADEON_CRTC_DISP_REQ_EN_B));
336	WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);	339	WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
337	}	340	}
-		341	radeon_crtc->enabled = false;
-		342	/* adjust pm to dpms changes AFTER disabling crtcs */
-		343	radeon_pm_compute_clocks(rdev);
338	break;	344	break;
339	}	345	}
340	}	346	}
341		347
342	int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,	348	int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
343	struct drm_framebuffer *old_fb)	349	struct drm_framebuffer *old_fb)
344	{	350	{
-		351	return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
-		352	}
-		353
-		354	int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
-		355	struct drm_framebuffer *fb,
-		356	int x, int y, enum mode_set_atomic state)
-		357	{
-		358	return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
-		359	}
-		360
-		361	int radeon_crtc_do_set_base(struct drm_crtc *crtc,
-		362	struct drm_framebuffer *fb,
-		363	int x, int y, int atomic)
-		364	{
345	struct drm_device *dev = crtc->dev;	365	struct drm_device *dev = crtc->dev;
346	struct radeon_device *rdev = dev->dev_private;	366	struct radeon_device *rdev = dev->dev_private;
347	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	367	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
348	struct radeon_framebuffer *radeon_fb;	368	struct radeon_framebuffer *radeon_fb;
-		369	struct drm_framebuffer *target_fb;
349	struct drm_gem_object *obj;	370	struct drm_gem_object *obj;
350	struct radeon_bo *rbo;	371	struct radeon_bo *rbo;
351	uint64_t base;	372	uint64_t base;
352	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;	373	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
353	uint32_t crtc_pitch, pitch_pixels;	374	uint32_t crtc_pitch, pitch_pixels;
354	uint32_t tiling_flags;	375	uint32_t tiling_flags;
355	int format;	376	int format;
356	uint32_t gen_cntl_reg, gen_cntl_val;	377	uint32_t gen_cntl_reg, gen_cntl_val;
357	int r;	378	int r;
358		379
359	DRM_DEBUG("\n");	380	DRM_DEBUG_KMS("\n");
360	/* no fb bound */	381	/* no fb bound */
361	if (!crtc->fb) {	382	if (!atomic && !crtc->fb) {
362	DRM_DEBUG("No FB bound\n");	383	DRM_DEBUG_KMS("No FB bound\n");
363	return 0;	384	return 0;
364	}	385	}
-		386
-		387	if (atomic) {
-		388	radeon_fb = to_radeon_framebuffer(fb);
-		389	target_fb = fb;
-		390	}
365		391	else {
-		392	radeon_fb = to_radeon_framebuffer(crtc->fb);
-		393	target_fb = crtc->fb;
366	radeon_fb = to_radeon_framebuffer(crtc->fb);	394	}
367		395
368	switch (crtc->fb->bits_per_pixel) {	396	switch (target_fb->bits_per_pixel) {
369	case 8:	397	case 8:
370	format = 2;	398	format = 2;
371	break;	399	break;
372	case 15: /* 555 */	400	case 15: /* 555 */
373	format = 3;	401	format = 3;
374	break;	402	break;
375	case 16: /* 565 */	403	case 16: /* 565 */
376	format = 4;	404	format = 4;
377	break;	405	break;
378	case 24: /* RGB */	406	case 24: /* RGB */
379	format = 5;	407	format = 5;
380	break;	408	break;
381	case 32: /* xRGB */	409	case 32: /* xRGB */
382	format = 6;	410	format = 6;
383	break;	411	break;
384	default:	412	default:
385	return false;	413	return false;
386	}	414	}
387		415
388	/* Pin framebuffer & get tilling informations */	416	/* Pin framebuffer & get tilling informations */
389	obj = radeon_fb->obj;	417	obj = radeon_fb->obj;
390	rbo = obj->driver_private;	418	rbo = gem_to_radeon_bo(obj);
391	r = radeon_bo_reserve(rbo, false);	419	r = radeon_bo_reserve(rbo, false);
392	if (unlikely(r != 0))	420	if (unlikely(r != 0))
393	return r;	421	return r;
394	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);	422	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
395	if (unlikely(r != 0)) {	423	if (unlikely(r != 0)) {
396	radeon_bo_unreserve(rbo);	424	radeon_bo_unreserve(rbo);
397	return -EINVAL;	425	return -EINVAL;
398	}	426	}
399	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);	427	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
400	radeon_bo_unreserve(rbo);	428	radeon_bo_unreserve(rbo);
401	if (tiling_flags & RADEON_TILING_MICRO)	429	if (tiling_flags & RADEON_TILING_MICRO)
402	DRM_ERROR("trying to scanout microtiled buffer\n");	430	DRM_ERROR("trying to scanout microtiled buffer\n");
403		431
404	/* if scanout was in GTT this really wouldn't work */	432	/* if scanout was in GTT this really wouldn't work */
405	/* crtc offset is from display base addr not FB location */	433	/* crtc offset is from display base addr not FB location */
406	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;	434	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
407		435
408	base -= radeon_crtc->legacy_display_base_addr;	436	base -= radeon_crtc->legacy_display_base_addr;
409		437
410	crtc_offset_cntl = 0;	438	crtc_offset_cntl = 0;
411		439
412	pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);	440	pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
413	crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +	441	crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) +
414	((crtc->fb->bits_per_pixel * 8) - 1)) /	442	((target_fb->bits_per_pixel * 8) - 1)) /
415	(crtc->fb->bits_per_pixel * 8));	443	(target_fb->bits_per_pixel * 8));
416	crtc_pitch \|= crtc_pitch << 16;	-
-		444	crtc_pitch \|= crtc_pitch << 16;
417		445
418		446	crtc_offset_cntl \|= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
419	if (tiling_flags & RADEON_TILING_MACRO) {	447	if (tiling_flags & RADEON_TILING_MACRO) {
420	if (ASIC_IS_R300(rdev))	448	if (ASIC_IS_R300(rdev))
421	crtc_offset_cntl \|= (R300_CRTC_X_Y_MODE_EN \|	449	crtc_offset_cntl \|= (R300_CRTC_X_Y_MODE_EN \|
422	R300_CRTC_MICRO_TILE_BUFFER_DIS \|	450	R300_CRTC_MICRO_TILE_BUFFER_DIS \|
423	R300_CRTC_MACRO_TILE_EN);	451	R300_CRTC_MACRO_TILE_EN);
424	else	452	else
425	crtc_offset_cntl \|= RADEON_CRTC_TILE_EN;	453	crtc_offset_cntl \|= RADEON_CRTC_TILE_EN;
426	} else {	454	} else {
427	if (ASIC_IS_R300(rdev))	455	if (ASIC_IS_R300(rdev))
428	crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN \|	456	crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN \|
429	R300_CRTC_MICRO_TILE_BUFFER_DIS \|	457	R300_CRTC_MICRO_TILE_BUFFER_DIS \|
430	R300_CRTC_MACRO_TILE_EN);	458	R300_CRTC_MACRO_TILE_EN);
431	else	459	else
432	crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;	460	crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
433	}	461	}
434		462
435	if (tiling_flags & RADEON_TILING_MACRO) {	463	if (tiling_flags & RADEON_TILING_MACRO) {
436	if (ASIC_IS_R300(rdev)) {	464	if (ASIC_IS_R300(rdev)) {
437	crtc_tile_x0_y0 = x \| (y << 16);	465	crtc_tile_x0_y0 = x \| (y << 16);
438	base &= ~0x7ff;	466	base &= ~0x7ff;
439	} else {	467	} else {
440	int byteshift = crtc->fb->bits_per_pixel >> 4;	468	int byteshift = target_fb->bits_per_pixel >> 4;
441	int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;	469	int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
442	base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);	470	base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
443	crtc_offset_cntl \|= (y % 16);	471	crtc_offset_cntl \|= (y % 16);
444	}	472	}
445	} else {	473	} else {
446	int offset = y * pitch_pixels + x;	474	int offset = y * pitch_pixels + x;
447	switch (crtc->fb->bits_per_pixel) {	475	switch (target_fb->bits_per_pixel) {
448	case 8:	476	case 8:
449	offset *= 1;	477	offset *= 1;
450	break;	478	break;
451	case 15:	479	case 15:
452	case 16:	480	case 16:
453	offset *= 2;	481	offset *= 2;
454	break;	482	break;
455	case 24:	483	case 24:
456	offset *= 3;	484	offset *= 3;
457	break;	485	break;
458	case 32:	486	case 32:
459	offset *= 4;	487	offset *= 4;
460	break;	488	break;
461	default:	489	default:
462	return false;	490	return false;
463	}	491	}
464	base += offset;	492	base += offset;
465	}	493	}
466		494
467	base &= ~7;	495	base &= ~7;
468		496
469	if (radeon_crtc->crtc_id == 1)	497	if (radeon_crtc->crtc_id == 1)
470	gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;	498	gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
471	else	499	else

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_legacy_crtc.c – Rev 1430 → 1963