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Rev 1430 Rev 1963
Line 24... Line 24...
24
 *          Alex Deucher
24
 *          Alex Deucher
25
 */
25
 */
26
#include 
26
#include 
27
#include 
27
#include 
28
#include 
28
#include 
29
#include "radeon_fixed.h"
29
#include 
30
#include "radeon.h"
30
#include "radeon.h"
31
#include "atom.h"
31
#include "atom.h"
Line 32... Line 32...
32
 
32
 
33
static void radeon_overscan_setup(struct drm_crtc *crtc,
33
static void radeon_overscan_setup(struct drm_crtc *crtc,
Line 270... Line 270...
270
	unsigned int vcoFreq;
270
	unsigned int vcoFreq;
Line 271... Line 271...
271
 
271
 
272
	if (!ref_div)
272
	if (!ref_div)
Line 273... Line 273...
273
		return 1;
273
		return 1;
Line 274... Line 274...
274
 
274
 
275
	vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
275
	vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
276
 
276
 
277
	/*
277
	/*
Line 312... Line 312...
312
			RADEON_CRTC_VSYNC_DIS |
312
			RADEON_CRTC_VSYNC_DIS |
313
			RADEON_CRTC_HSYNC_DIS);
313
			RADEON_CRTC_HSYNC_DIS);
Line 314... Line 314...
314
 
314
 
315
	switch (mode) {
315
	switch (mode) {
-
 
316
	case DRM_MODE_DPMS_ON:
-
 
317
		radeon_crtc->enabled = true;
-
 
318
		/* adjust pm to dpms changes BEFORE enabling crtcs */
316
	case DRM_MODE_DPMS_ON:
319
		radeon_pm_compute_clocks(rdev);
317
		if (radeon_crtc->crtc_id)
320
		if (radeon_crtc->crtc_id)
318
			WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
321
			WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
319
		else {
322
		else {
320
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
323
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
Line 333... Line 336...
333
		else {
336
		else {
334
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
337
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
335
										    RADEON_CRTC_DISP_REQ_EN_B));
338
										    RADEON_CRTC_DISP_REQ_EN_B));
336
			WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
339
			WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
337
		}
340
		}
-
 
341
		radeon_crtc->enabled = false;
-
 
342
		/* adjust pm to dpms changes AFTER disabling crtcs */
-
 
343
		radeon_pm_compute_clocks(rdev);
338
		break;
344
		break;
339
	}
345
	}
340
}
346
}
Line 341... Line 347...
341
 
347
 
342
int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
348
int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
343
			 struct drm_framebuffer *old_fb)
349
			 struct drm_framebuffer *old_fb)
-
 
350
{
-
 
351
	return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
-
 
352
}
-
 
353
 
-
 
354
int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
-
 
355
				struct drm_framebuffer *fb,
-
 
356
				int x, int y, enum mode_set_atomic state)
-
 
357
{
-
 
358
	return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
-
 
359
}
-
 
360
 
-
 
361
int radeon_crtc_do_set_base(struct drm_crtc *crtc,
-
 
362
			 struct drm_framebuffer *fb,
-
 
363
			 int x, int y, int atomic)
344
{
364
{
345
	struct drm_device *dev = crtc->dev;
365
	struct drm_device *dev = crtc->dev;
346
	struct radeon_device *rdev = dev->dev_private;
366
	struct radeon_device *rdev = dev->dev_private;
347
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
367
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-
 
368
	struct radeon_framebuffer *radeon_fb;
348
	struct radeon_framebuffer *radeon_fb;
369
	struct drm_framebuffer *target_fb;
349
	struct drm_gem_object *obj;
370
	struct drm_gem_object *obj;
350
	struct radeon_bo *rbo;
371
	struct radeon_bo *rbo;
351
	uint64_t base;
372
	uint64_t base;
352
	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
373
	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
353
	uint32_t crtc_pitch, pitch_pixels;
374
	uint32_t crtc_pitch, pitch_pixels;
354
	uint32_t tiling_flags;
375
	uint32_t tiling_flags;
355
	int format;
376
	int format;
356
	uint32_t gen_cntl_reg, gen_cntl_val;
377
	uint32_t gen_cntl_reg, gen_cntl_val;
Line 357... Line 378...
357
	int r;
378
	int r;
358
 
379
 
359
	DRM_DEBUG("\n");
380
	DRM_DEBUG_KMS("\n");
360
	/* no fb bound */
381
	/* no fb bound */
361
	if (!crtc->fb) {
382
	if (!atomic && !crtc->fb) {
362
		DRM_DEBUG("No FB bound\n");
383
		DRM_DEBUG_KMS("No FB bound\n");
Line -... Line 384...
-
 
384
		return 0;
-
 
385
	}
-
 
386
 
-
 
387
	if (atomic) {
-
 
388
		radeon_fb = to_radeon_framebuffer(fb);
363
		return 0;
389
		target_fb = fb;
-
 
390
	}
-
 
391
	else {
Line 364... Line 392...
364
	}
392
	radeon_fb = to_radeon_framebuffer(crtc->fb);
365
 
393
		target_fb = crtc->fb;
366
	radeon_fb = to_radeon_framebuffer(crtc->fb);
394
	}
367
 
395
 
368
	switch (crtc->fb->bits_per_pixel) {
396
	switch (target_fb->bits_per_pixel) {
369
	case 8:
397
	case 8:
Line 385... Line 413...
385
		return false;
413
		return false;
386
	}
414
	}
Line 387... Line 415...
387
 
415
 
388
	/* Pin framebuffer & get tilling informations */
416
	/* Pin framebuffer & get tilling informations */
389
	obj = radeon_fb->obj;
417
	obj = radeon_fb->obj;
390
	rbo = obj->driver_private;
418
	rbo = gem_to_radeon_bo(obj);
391
	r = radeon_bo_reserve(rbo, false);
419
	r = radeon_bo_reserve(rbo, false);
392
	if (unlikely(r != 0))
420
	if (unlikely(r != 0))
393
		return r;
421
		return r;
394
	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
422
	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
Line 407... Line 435...
407
 
435
 
Line 408... Line 436...
408
	base -= radeon_crtc->legacy_display_base_addr;
436
	base -= radeon_crtc->legacy_display_base_addr;
Line 409... Line 437...
409
 
437
 
410
	crtc_offset_cntl = 0;
438
	crtc_offset_cntl = 0;
411
 
439
 
412
	pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
440
	pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
413
	crtc_pitch  = (((pitch_pixels * crtc->fb->bits_per_pixel) +
441
	crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
Line 414... Line -...
414
			((crtc->fb->bits_per_pixel * 8) - 1)) /
-
 
-
 
442
			((target_fb->bits_per_pixel * 8) - 1)) /
415
		       (crtc->fb->bits_per_pixel * 8));
443
		       (target_fb->bits_per_pixel * 8));
416
	crtc_pitch |= crtc_pitch << 16;
444
	crtc_pitch |= crtc_pitch << 16;
417
 
445
 
418
 
446
	crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
419
	if (tiling_flags & RADEON_TILING_MACRO) {
447
	if (tiling_flags & RADEON_TILING_MACRO) {
Line 435... Line 463...
435
	if (tiling_flags & RADEON_TILING_MACRO) {
463
	if (tiling_flags & RADEON_TILING_MACRO) {
436
		if (ASIC_IS_R300(rdev)) {
464
		if (ASIC_IS_R300(rdev)) {
437
			crtc_tile_x0_y0 = x | (y << 16);
465
			crtc_tile_x0_y0 = x | (y << 16);
438
			base &= ~0x7ff;
466
			base &= ~0x7ff;
439
		} else {
467
		} else {
440
			int byteshift = crtc->fb->bits_per_pixel >> 4;
468
			int byteshift = target_fb->bits_per_pixel >> 4;
441
			int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
469
			int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
442
			base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
470
			base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
443
			crtc_offset_cntl |= (y % 16);
471
			crtc_offset_cntl |= (y % 16);
444
		}
472
		}
445
	} else {
473
	} else {
446
		int offset = y * pitch_pixels + x;
474
		int offset = y * pitch_pixels + x;
447
		switch (crtc->fb->bits_per_pixel) {
475
		switch (target_fb->bits_per_pixel) {
448
		case 8:
476
		case 8:
449
			offset *= 1;
477
			offset *= 1;
450
			break;
478
			break;
451
		case 15:
479
		case 15:
452
		case 16:
480
		case 16:
Line 472... Line 500...
472
		gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
500
		gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
Line 473... Line 501...
473
 
501
 
474
	gen_cntl_val = RREG32(gen_cntl_reg);
502
	gen_cntl_val = RREG32(gen_cntl_reg);
475
	gen_cntl_val &= ~(0xf << 8);
503
	gen_cntl_val &= ~(0xf << 8);
-
 
504
	gen_cntl_val |= (format << 8);
476
	gen_cntl_val |= (format << 8);
505
	gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
Line 477... Line 506...
477
	WREG32(gen_cntl_reg, gen_cntl_val);
506
	WREG32(gen_cntl_reg, gen_cntl_val);
Line 478... Line 507...
478
 
507
 
Line 488... Line 517...
488
	}
517
	}
489
	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
518
	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
490
	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
519
	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
491
	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
520
	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
Line 492... Line 521...
492
 
521
 
493
	if (old_fb && old_fb != crtc->fb) {
522
	if (!atomic && fb && fb != crtc->fb) {
494
		radeon_fb = to_radeon_framebuffer(old_fb);
523
		radeon_fb = to_radeon_framebuffer(fb);
495
		rbo = radeon_fb->obj->driver_private;
524
		rbo = gem_to_radeon_bo(radeon_fb->obj);
496
		r = radeon_bo_reserve(rbo, false);
525
		r = radeon_bo_reserve(rbo, false);
497
		if (unlikely(r != 0))
526
		if (unlikely(r != 0))
498
			return r;
527
			return r;
499
		radeon_bo_unpin(rbo);
528
		radeon_bo_unpin(rbo);
Line 520... Line 549...
520
	uint32_t crtc_h_sync_strt_wid;
549
	uint32_t crtc_h_sync_strt_wid;
521
	uint32_t crtc_v_total_disp;
550
	uint32_t crtc_v_total_disp;
522
	uint32_t crtc_v_sync_strt_wid;
551
	uint32_t crtc_v_sync_strt_wid;
523
	bool is_tv = false;
552
	bool is_tv = false;
Line 524... Line 553...
524
 
553
 
525
	DRM_DEBUG("\n");
554
	DRM_DEBUG_KMS("\n");
526
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
555
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
527
		if (encoder->crtc == crtc) {
556
		if (encoder->crtc == crtc) {
528
			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
557
			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
529
			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
558
			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
Line 601... Line 630...
601
				      : 0)
630
				      : 0)
602
				   | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
631
				   | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
603
				      ? RADEON_CRTC2_INTERLACE_EN
632
				      ? RADEON_CRTC2_INTERLACE_EN
604
				      : 0));
633
				      : 0));
Line -... Line 634...
-
 
634
 
-
 
635
		/* rs4xx chips seem to like to have the crtc enabled when the timing is set */
-
 
636
		if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
-
 
637
			crtc2_gen_cntl |= RADEON_CRTC2_EN;
605
 
638
 
606
		disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
639
		disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
Line 607... Line 640...
607
		disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
640
		disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
608
 
641
 
Line 628... Line 661...
628
				    : 0)
661
				    : 0)
629
				 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
662
				 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
630
				    ? RADEON_CRTC_INTERLACE_EN
663
				    ? RADEON_CRTC_INTERLACE_EN
631
				    : 0));
664
				    : 0));
Line -... Line 665...
-
 
665
 
-
 
666
		/* rs4xx chips seem to like to have the crtc enabled when the timing is set */
-
 
667
		if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
-
 
668
			crtc_gen_cntl |= RADEON_CRTC_EN;
632
 
669
 
633
		crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
670
		crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
634
		crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
671
		crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
635
				  RADEON_CRTC_VSYNC_DIS |
672
				  RADEON_CRTC_VSYNC_DIS |
636
				  RADEON_CRTC_HSYNC_DIS |
673
				  RADEON_CRTC_HSYNC_DIS |
Line 701... Line 738...
701
		pll = &rdev->clock.p2pll;
738
		pll = &rdev->clock.p2pll;
702
	else
739
	else
703
		pll = &rdev->clock.p1pll;
740
		pll = &rdev->clock.p1pll;
Line 704... Line 741...
704
 
741
 
705
	pll->flags = RADEON_PLL_LEGACY;
-
 
706
	if (radeon_new_pll == 1)
-
 
707
		pll->algo = PLL_ALGO_NEW;
-
 
708
	else
-
 
Line 709... Line 742...
709
		pll->algo = PLL_ALGO_LEGACY;
742
	pll->flags = RADEON_PLL_LEGACY;
710
 
743
 
711
	if (mode->clock > 200000) /* range limits??? */
744
	if (mode->clock > 200000) /* range limits??? */
712
		pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
745
		pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
Line 741... Line 774...
741
				pll->flags |= RADEON_PLL_USE_REF_DIV;
774
				pll->flags |= RADEON_PLL_USE_REF_DIV;
742
			}
775
			}
743
		}
776
		}
744
	}
777
	}
Line 745... Line 778...
745
 
778
 
Line 746... Line 779...
746
	DRM_DEBUG("\n");
779
	DRM_DEBUG_KMS("\n");
747
 
780
 
748
	if (!use_bios_divs) {
781
	if (!use_bios_divs) {
749
		radeon_compute_pll(pll, mode->clock,
782
		radeon_compute_pll_legacy(pll, mode->clock,
Line 750... Line 783...
750
				   &freq, &feedback_div, &frac_fb_div,
783
				   &freq, &feedback_div, &frac_fb_div,
751
				   &reference_div, &post_divider);
784
				   &reference_div, &post_divider);
Line 756... Line 789...
756
		}
789
		}
Line 757... Line 790...
757
 
790
 
758
		if (!post_div->divider)
791
		if (!post_div->divider)
Line 759... Line 792...
759
			post_div = &post_divs[0];
792
			post_div = &post_divs[0];
760
 
793
 
761
		DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
794
		DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
762
			  (unsigned)freq,
795
			  (unsigned)freq,
763
			  feedback_div,
796
			  feedback_div,
Line 825... Line 858...
825
			     0,
858
			     0,
826
			     ~(RADEON_P2PLL_RESET
859
			     ~(RADEON_P2PLL_RESET
827
			       | RADEON_P2PLL_SLEEP
860
			       | RADEON_P2PLL_SLEEP
828
			       | RADEON_P2PLL_ATOMIC_UPDATE_EN));
861
			       | RADEON_P2PLL_ATOMIC_UPDATE_EN));
Line 829... Line 862...
829
 
862
 
830
		DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
863
		DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
831
			  (unsigned)pll_ref_div,
864
			  (unsigned)pll_ref_div,
832
			  (unsigned)pll_fb_post_div,
865
			  (unsigned)pll_fb_post_div,
833
			  (unsigned)htotal_cntl,
866
			  (unsigned)htotal_cntl,
834
			  RREG32_PLL(RADEON_P2PLL_CNTL));
867
			  RREG32_PLL(RADEON_P2PLL_CNTL));
835
		DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
868
		DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
836
			  (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
869
			  (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
837
			  (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
870
			  (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
838
			  (unsigned)((pll_fb_post_div &
871
			  (unsigned)((pll_fb_post_div &
Line 854... Line 887...
854
			radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
887
			radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
855
						     &pll_fb_post_div, &pixclks_cntl);
888
						     &pll_fb_post_div, &pixclks_cntl);
856
		}
889
		}
Line 857... Line 890...
857
 
890
 
858
		if (rdev->flags & RADEON_IS_MOBILITY) {
891
		if (rdev->flags & RADEON_IS_MOBILITY) {
859
			/* A temporal workaround for the occational blanking on certain laptop panels.
892
			/* A temporal workaround for the occasional blanking on certain laptop panels.
860
			   This appears to related to the PLL divider registers (fail to lock?).
893
			   This appears to related to the PLL divider registers (fail to lock?).
861
			   It occurs even when all dividers are the same with their old settings.
894
			   It occurs even when all dividers are the same with their old settings.
862
			   In this case we really don't need to fiddle with PLL registers.
895
			   In this case we really don't need to fiddle with PLL registers.
863
			   By doing this we can avoid the blanking problem with some panels.
896
			   By doing this we can avoid the blanking problem with some panels.
Line 931... Line 964...
931
			     ~(RADEON_PPLL_RESET
964
			     ~(RADEON_PPLL_RESET
932
			       | RADEON_PPLL_SLEEP
965
			       | RADEON_PPLL_SLEEP
933
			       | RADEON_PPLL_ATOMIC_UPDATE_EN
966
			       | RADEON_PPLL_ATOMIC_UPDATE_EN
934
			       | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
967
			       | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
Line 935... Line 968...
935
 
968
 
936
		DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
969
		DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
937
			  pll_ref_div,
970
			  pll_ref_div,
938
			  pll_fb_post_div,
971
			  pll_fb_post_div,
939
			  (unsigned)htotal_cntl,
972
			  (unsigned)htotal_cntl,
940
			  RREG32_PLL(RADEON_PPLL_CNTL));
973
			  RREG32_PLL(RADEON_PPLL_CNTL));
941
		DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
974
		DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
942
			  pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
975
			  pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
943
			  pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
976
			  pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
Line 944... Line 977...
944
			  (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
977
			  (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
Line 956... Line 989...
956
 
989
 
957
static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
990
static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
958
				   struct drm_display_mode *mode,
991
				   struct drm_display_mode *mode,
959
				   struct drm_display_mode *adjusted_mode)
992
				   struct drm_display_mode *adjusted_mode)
-
 
993
{
-
 
994
	struct drm_device *dev = crtc->dev;
-
 
995
	struct radeon_device *rdev = dev->dev_private;
-
 
996
 
-
 
997
	/* adjust pm to upcoming mode change */
-
 
998
	radeon_pm_compute_clocks(rdev);
960
{
999
 
961
	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1000
	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
962
		return false;
1001
		return false;
963
	return true;
1002
	return true;
Line 1018... Line 1057...
1018
static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1057
static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1019
	.dpms = radeon_crtc_dpms,
1058
	.dpms = radeon_crtc_dpms,
1020
	.mode_fixup = radeon_crtc_mode_fixup,
1059
	.mode_fixup = radeon_crtc_mode_fixup,
1021
	.mode_set = radeon_crtc_mode_set,
1060
	.mode_set = radeon_crtc_mode_set,
1022
	.mode_set_base = radeon_crtc_set_base,
1061
	.mode_set_base = radeon_crtc_set_base,
-
 
1062
	.mode_set_base_atomic = radeon_crtc_set_base_atomic,
1023
	.prepare = radeon_crtc_prepare,
1063
	.prepare = radeon_crtc_prepare,
1024
	.commit = radeon_crtc_commit,
1064
	.commit = radeon_crtc_commit,
1025
	.load_lut = radeon_crtc_load_lut,
1065
	.load_lut = radeon_crtc_load_lut,
1026
};
1066
};