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Rev 1404 Rev 1430
Line 319... Line 319...
319 
		else {
 319 
		else {
320 
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 320 
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
321 
									 RADEON_CRTC_DISP_REQ_EN_B));
 321 
									 RADEON_CRTC_DISP_REQ_EN_B));
322 
			WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 322 
			WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
323 
		}
 323 
		}
- 
 
 324 
		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
324 
		radeon_crtc_load_lut(crtc);
 325 
		radeon_crtc_load_lut(crtc);
325 
		break;
 326 
		break;
326 
	case DRM_MODE_DPMS_STANDBY:
 327 
	case DRM_MODE_DPMS_STANDBY:
327 
	case DRM_MODE_DPMS_SUSPEND:
 328 
	case DRM_MODE_DPMS_SUSPEND:
328 
	case DRM_MODE_DPMS_OFF:
 329 
	case DRM_MODE_DPMS_OFF:
- 
 
 330 
		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
329 
		if (radeon_crtc->crtc_id)
 331 
		if (radeon_crtc->crtc_id)
330 
			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 332 
			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
331 
		else {
 333 
		else {
332 
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 334 
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
333 
										    RADEON_CRTC_DISP_REQ_EN_B));
 335 
										    RADEON_CRTC_DISP_REQ_EN_B));
Line 399... Line 401...
399 
	if (tiling_flags & RADEON_TILING_MICRO)
 401 
	if (tiling_flags & RADEON_TILING_MICRO)
400 
		DRM_ERROR("trying to scanout microtiled buffer\n");
 402 
		DRM_ERROR("trying to scanout microtiled buffer\n");
Line 401... Line 403...
401 
 
 403 
 
402 
	/* if scanout was in GTT this really wouldn't work */
 404 
	/* if scanout was in GTT this really wouldn't work */
403 
	/* crtc offset is from display base addr not FB location */
 405 
	/* crtc offset is from display base addr not FB location */
Line 404... Line 406...
404 
	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
 406 
	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
Line 405... Line 407...
405 
 
 407 
 
Line 578... Line 580...
578 
				| ((vsync_wid & 0x1f) << 16)
 580 
				| ((vsync_wid & 0x1f) << 16)
579 
				| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 581 
				| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
580 
				   ? RADEON_CRTC_V_SYNC_POL
 582 
				   ? RADEON_CRTC_V_SYNC_POL
581 
				   : 0));
 583 
				   : 0));
Line 582... Line -...
582 
 
 - 
 
583 
	/* TODO -> Dell Server */
 - 
 
584 
	if (0) {
 - 
 
585 
		uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 - 
 
586 
		uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 - 
 
587 
		uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 - 
 
588 
		uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 - 
 
589 
 
 - 
 
590 
		dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
 - 
 
591 
		dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 - 
 
592 
 
 - 
 
593 
		/* For CRT on DAC2, don't turn it on if BIOS didn't
 - 
 
594 
		   enable it, even it's detected.
 - 
 
595 
		*/
 - 
 
596 
		disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 - 
 
597 
		tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
 - 
 
598 
		tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 - 
 
599 
 
 - 
 
600 
		WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 - 
 
601 
		WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 - 
 
602 
		WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 - 
 
603 
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 - 
 
604 
	}
 - 
 
605 
 
 584 
 
606 
	if (radeon_crtc->crtc_id) {
 585 
	if (radeon_crtc->crtc_id) {
607 
		uint32_t crtc2_gen_cntl;
 586 
		uint32_t crtc2_gen_cntl;
Line 608... Line 587...
608 
		uint32_t disp2_merge_cntl;
 587 
		uint32_t disp2_merge_cntl;
Line 722... Line 701...
722 
		pll = &rdev->clock.p2pll;
 701 
		pll = &rdev->clock.p2pll;
723 
	else
 702 
	else
724 
		pll = &rdev->clock.p1pll;
 703 
		pll = &rdev->clock.p1pll;
Line 725... Line 704...
725 
 
 704 
 
- 
 
 705 
	pll->flags = RADEON_PLL_LEGACY;
- 
 
 706 
	if (radeon_new_pll == 1)
- 
 
 707 
		pll->algo = PLL_ALGO_NEW;
- 
 
 708 
	else
Line 726... Line 709...
726 
	pll->flags = RADEON_PLL_LEGACY;
 709 
		pll->algo = PLL_ALGO_LEGACY;
727 
 
 710 
 
728 
	if (mode->clock > 200000) /* range limits??? */
 711 
	if (mode->clock > 200000) /* range limits??? */
729 
		pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 712 
		pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;