WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_legacy_crtc.c


/*
 * Copyright 2007-8 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 */
#include 
#include 
#include 
#include "radeon_fixed.h"
#include "radeon.h"
#include "atom.h"
 
static void radeon_overscan_setup(struct drm_crtc *crtc,
				  struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
	WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
	WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
	WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
}
 
static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
				       struct drm_display_mode *mode,
				       struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	int xres = mode->hdisplay;
	int yres = mode->vdisplay;
	bool hscale = true, vscale = true;
	int hsync_wid;
	int vsync_wid;
	int hsync_start;
	int blank_width;
	u32 scale, inc, crtc_more_cntl;
	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
	struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
 
	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
		(RADEON_VERT_STRETCH_RESERVED |
		 RADEON_VERT_AUTO_RATIO_INC);
	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
		(RADEON_HORZ_FP_LOOP_STRETCH |
		 RADEON_HORZ_AUTO_RATIO_INC);
 
	crtc_more_cntl = 0;
	if ((rdev->family == CHIP_RS100) ||
	    (rdev->family == CHIP_RS200)) {
		/* This is to workaround the asic bug for RMX, some versions
		   of BIOS dosen't have this register initialized correctly. */
		crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
	}
 
 
	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
				| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 
	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
	if (!hsync_wid)
		hsync_wid = 1;
	hsync_start = mode->crtc_hsync_start - 8;
 
	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
			      | ((hsync_wid & 0x3f) << 16)
			      | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
				 ? RADEON_CRTC_H_SYNC_POL
				 : 0));
 
	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
				| ((mode->crtc_vdisplay - 1) << 16));
 
	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
	if (!vsync_wid)
		vsync_wid = 1;
 
	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
			      | ((vsync_wid & 0x1f) << 16)
			      | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
				 ? RADEON_CRTC_V_SYNC_POL
				 : 0));
 
	fp_horz_vert_active = 0;
 
	if (native_mode->hdisplay == 0 ||
	    native_mode->vdisplay == 0) {
		hscale = false;
		vscale = false;
	} else {
		if (xres > native_mode->hdisplay)
			xres = native_mode->hdisplay;
		if (yres > native_mode->vdisplay)
			yres = native_mode->vdisplay;
 
		if (xres == native_mode->hdisplay)
			hscale = false;
		if (yres == native_mode->vdisplay)
			vscale = false;
	}
 
	switch (radeon_crtc->rmx_type) {
	case RMX_FULL:
	case RMX_ASPECT:
		if (!hscale)
			fp_horz_stretch |= ((xres/8-1) << 16);
		else {
			inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
			scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
				/ native_mode->hdisplay + 1;
			fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
					RADEON_HORZ_STRETCH_BLEND |
					RADEON_HORZ_STRETCH_ENABLE |
					((native_mode->hdisplay/8-1) << 16));
		}
 
		if (!vscale)
			fp_vert_stretch |= ((yres-1) << 12);
		else {
			inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
			scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
				/ native_mode->vdisplay + 1;
			fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
					RADEON_VERT_STRETCH_ENABLE |
					RADEON_VERT_STRETCH_BLEND |
					((native_mode->vdisplay-1) << 12));
		}
		break;
	case RMX_CENTER:
		fp_horz_stretch |= ((xres/8-1) << 16);
		fp_vert_stretch |= ((yres-1) << 12);
 
		crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
				RADEON_CRTC_AUTO_VERT_CENTER_EN);
 
		blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
		if (blank_width > 110)
			blank_width = 110;
 
		fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
				| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 
		hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
		if (!hsync_wid)
			hsync_wid = 1;
 
		fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
				| ((hsync_wid & 0x3f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
					? RADEON_CRTC_H_SYNC_POL
					: 0));
 
		fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
				| ((mode->crtc_vdisplay - 1) << 16));
 
		vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
		if (!vsync_wid)
			vsync_wid = 1;
 
		fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
					| ((vsync_wid & 0x1f) << 16)
					| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
						? RADEON_CRTC_V_SYNC_POL
						: 0)));
 
		fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
				(((native_mode->hdisplay / 8) & 0x1ff) << 16));
		break;
	case RMX_OFF:
	default:
		fp_horz_stretch |= ((xres/8-1) << 16);
		fp_vert_stretch |= ((yres-1) << 12);
		break;
	}
 
	WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
	WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
	WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
	WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
	WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
	WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
}
 
void radeon_restore_common_regs(struct drm_device *dev)
{
	/* don't need this yet */
}
 
static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	int i = 0;
 
	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
	   the cause yet, but this workaround will mask the problem for now.
	   Other chips usually will pass at the very first test, so the
	   workaround shouldn't have any effect on them. */
	for (i = 0;
	     (i < 10000 &&
	      RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
	     i++);
}
 
static void radeon_pll_write_update(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
 
	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 
	WREG32_PLL_P(RADEON_PPLL_REF_DIV,
			   RADEON_PPLL_ATOMIC_UPDATE_W,
			   ~(RADEON_PPLL_ATOMIC_UPDATE_W));
}
 
static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	int i = 0;
 
 
	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
	   the cause yet, but this workaround will mask the problem for now.
	   Other chips usually will pass at the very first test, so the
	   workaround shouldn't have any effect on them. */
	for (i = 0;
	     (i < 10000 &&
	      RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
	     i++);
}
 
static void radeon_pll2_write_update(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
 
	while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 
	WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
			   RADEON_P2PLL_ATOMIC_UPDATE_W,
			   ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
}
 
static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
				       uint16_t fb_div)
{
	unsigned int vcoFreq;
 
	if (!ref_div)
		return 1;
 
	vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
 
	/*
	 * This is horribly crude: the VCO frequency range is divided into
	 * 3 parts, each part having a fixed PLL gain value.
	 */
	if (vcoFreq >= 30000)
		/*
		 * [300..max] MHz : 7
		 */
		return 7;
	else if (vcoFreq >= 18000)
		/*
		 * [180..300) MHz : 4
		 */
		return 4;
	else
		/*
		 * [0..180) MHz : 1
		 */
		return 1;
}
 
void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t mask;
 
	if (radeon_crtc->crtc_id)
		mask = (RADEON_CRTC2_DISP_DIS |
 
			RADEON_CRTC2_VSYNC_DIS |
			RADEON_CRTC2_HSYNC_DIS |
			RADEON_CRTC2_DISP_REQ_EN_B);
	else
		mask = (RADEON_CRTC_DISPLAY_DIS |
			RADEON_CRTC_VSYNC_DIS |
			RADEON_CRTC_HSYNC_DIS);
 
	switch (mode) {
	case DRM_MODE_DPMS_ON:
		if (radeon_crtc->crtc_id)
			WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
		else {
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
									 RADEON_CRTC_DISP_REQ_EN_B));
			WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
		}
//       drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
		radeon_crtc_load_lut(crtc);
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
//       drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
		if (radeon_crtc->crtc_id)
			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
		else {
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
										    RADEON_CRTC_DISP_REQ_EN_B));
			WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
		}
		break;
	}
}
 
/* properly set crtc bpp when using atombios */
void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	int format;
	uint32_t crtc_gen_cntl;
	uint32_t disp_merge_cntl;
	uint32_t crtc_pitch;
 
	switch (crtc->fb->bits_per_pixel) {
	case 8:
		format = 2;
		break;
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return;
	}
 
	crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
			((crtc->fb->bits_per_pixel * 8) - 1)) /
		       (crtc->fb->bits_per_pixel * 8));
	crtc_pitch |= crtc_pitch << 16;
 
	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 
	switch (radeon_crtc->crtc_id) {
	case 0:
		disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 
		crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
		crtc_gen_cntl |= (format << 8);
		crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
		WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
		break;
	case 1:
		disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
		WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
 
		crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
		crtc_gen_cntl |= (format << 8);
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
		WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
		WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
		break;
	}
}
 
int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
			 struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct radeon_framebuffer *radeon_fb;
	struct drm_gem_object *obj;
	struct radeon_bo *rbo;
	uint64_t base;
	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
	uint32_t crtc_pitch, pitch_pixels;
	uint32_t tiling_flags;
	int format;
	uint32_t gen_cntl_reg, gen_cntl_val;
	int r;
 
	DRM_DEBUG("\n");
	/* no fb bound */
	if (!crtc->fb) {
		DRM_DEBUG("No FB bound\n");
		return 0;
	}
 
	radeon_fb = to_radeon_framebuffer(crtc->fb);
 
	switch (crtc->fb->bits_per_pixel) {
	case 8:
		format = 2;
		break;
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return false;
	}
 
	/* Pin framebuffer & get tilling informations */
	obj = radeon_fb->obj;
	rbo = obj->driver_private;
	r = radeon_bo_reserve(rbo, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
	if (unlikely(r != 0)) {
		radeon_bo_unreserve(rbo);
		return -EINVAL;
	}
	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
	radeon_bo_unreserve(rbo);
	if (tiling_flags & RADEON_TILING_MICRO)
		DRM_ERROR("trying to scanout microtiled buffer\n");
 
	/* if scanout was in GTT this really wouldn't work */
	/* crtc offset is from display base addr not FB location */
	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
 
	base -= radeon_crtc->legacy_display_base_addr;
 
	crtc_offset_cntl = 0;
 
	pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
	crtc_pitch  = (((pitch_pixels * crtc->fb->bits_per_pixel) +
			((crtc->fb->bits_per_pixel * 8) - 1)) /
		       (crtc->fb->bits_per_pixel * 8));
	crtc_pitch |= crtc_pitch << 16;
 
 
 
 
 
 
 
 
	if (tiling_flags & RADEON_TILING_MACRO) {
		if (ASIC_IS_R300(rdev))
			crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
					     R300_CRTC_MICRO_TILE_BUFFER_DIS |
					     R300_CRTC_MACRO_TILE_EN);
		else
			crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
	} else {
		if (ASIC_IS_R300(rdev))
			crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
					      R300_CRTC_MICRO_TILE_BUFFER_DIS |
					      R300_CRTC_MACRO_TILE_EN);
		else
			crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
	}
 
	if (tiling_flags & RADEON_TILING_MACRO) {
		if (ASIC_IS_R300(rdev)) {
			crtc_tile_x0_y0 = x | (y << 16);
			base &= ~0x7ff;
		} else {
			int byteshift = crtc->fb->bits_per_pixel >> 4;
			int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
			base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
			crtc_offset_cntl |= (y % 16);
		}
	} else {
		int offset = y * pitch_pixels + x;
		switch (crtc->fb->bits_per_pixel) {
		case 8:
			offset *= 1;
			break;
		case 15:
		case 16:
			offset *= 2;
			break;
		case 24:
			offset *= 3;
			break;
		case 32:
			offset *= 4;
			break;
		default:
			return false;
		}
		base += offset;
	}
 
	base &= ~7;
 
	if (radeon_crtc->crtc_id == 1)
		gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
	else
		gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 
	gen_cntl_val = RREG32(gen_cntl_reg);
	gen_cntl_val &= ~(0xf << 8);
	gen_cntl_val |= (format << 8);
	WREG32(gen_cntl_reg, gen_cntl_val);
 
	crtc_offset = (u32)base;
 
	WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 
	if (ASIC_IS_R300(rdev)) {
		if (radeon_crtc->crtc_id)
			WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
		else
			WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
	}
	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 
	if (old_fb && old_fb != crtc->fb) {
		radeon_fb = to_radeon_framebuffer(old_fb);
		rbo = radeon_fb->obj->driver_private;
		r = radeon_bo_reserve(rbo, false);
		if (unlikely(r != 0))
			return r;
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
	}
 
	/* Bytes per pixel may have changed */
	radeon_bandwidth_update(rdev);
 
	return 0;
}
 
static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_encoder *encoder;
	int format;
	int hsync_start;
	int hsync_wid;
	int vsync_wid;
	uint32_t crtc_h_total_disp;
	uint32_t crtc_h_sync_strt_wid;
	uint32_t crtc_v_total_disp;
	uint32_t crtc_v_sync_strt_wid;
	bool is_tv = false;
 
	DRM_DEBUG("\n");
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
				is_tv = true;
				DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
				break;
			}
		}
	}
 
	switch (crtc->fb->bits_per_pixel) {
	case 8:
		format = 2;
		break;
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return false;
	}
 
	crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
			     | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 
	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
	if (!hsync_wid)
		hsync_wid = 1;
	hsync_start = mode->crtc_hsync_start - 8;
 
	crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
				| ((hsync_wid & 0x3f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
				   ? RADEON_CRTC_H_SYNC_POL
				   : 0));
 
	/* This works for double scan mode. */
	crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
			     | ((mode->crtc_vdisplay - 1) << 16));
 
	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
	if (!vsync_wid)
		vsync_wid = 1;
 
	crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
				| ((vsync_wid & 0x1f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
				   ? RADEON_CRTC_V_SYNC_POL
				   : 0));
 
	/* TODO -> Dell Server */
	if (0) {
		uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 
		dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
		dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 
		/* For CRT on DAC2, don't turn it on if BIOS didn't
		   enable it, even it's detected.
		*/
		disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
		tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
		tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 
		WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
	}
 
	if (radeon_crtc->crtc_id) {
		uint32_t crtc2_gen_cntl;
		uint32_t disp2_merge_cntl;
 
 
		/* if TV DAC is enabled for another crtc and keep it enabled */
 
 
 
		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
		crtc2_gen_cntl |= ((format << 8)
				   | RADEON_CRTC2_VSYNC_DIS
				   | RADEON_CRTC2_HSYNC_DIS
				   | RADEON_CRTC2_DISP_DIS
				   | RADEON_CRTC2_DISP_REQ_EN_B
				   | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
				      ? RADEON_CRTC2_DBL_SCAN_EN
				      : 0)
				   | ((mode->flags & DRM_MODE_FLAG_CSYNC)
				      ? RADEON_CRTC2_CSYNC_EN
				      : 0)
				   | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
				      ? RADEON_CRTC2_INTERLACE_EN
				      : 0));
 
		disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
		disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 
		WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 
		WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
		WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
	} else {
		uint32_t crtc_gen_cntl;
		uint32_t crtc_ext_cntl;
		uint32_t disp_merge_cntl;
 
		crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
		crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
				 | (format << 8)
				 | RADEON_CRTC_DISP_REQ_EN_B
				 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
				    ? RADEON_CRTC_DBL_SCAN_EN
				    : 0)
				 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
				    ? RADEON_CRTC_CSYNC_EN
				    : 0)
				 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
				    ? RADEON_CRTC_INTERLACE_EN
				    : 0));
 
		crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
				  RADEON_CRTC_VSYNC_DIS |
				  RADEON_CRTC_HSYNC_DIS |
				  RADEON_CRTC_DISPLAY_DIS);
 
		disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 
		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
		WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
		WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
	}
 
	if (is_tv)
		radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
						 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
						 &crtc_v_sync_strt_wid);
 
	WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
	WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
	WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
	WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 
	return true;
}
 
static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_encoder *encoder;
	uint32_t feedback_div = 0;
	uint32_t frac_fb_div = 0;
	uint32_t reference_div = 0;
	uint32_t post_divider = 0;
	uint32_t freq = 0;
	uint8_t pll_gain;
	int pll_flags = RADEON_PLL_LEGACY;
	bool use_bios_divs = false;
	/* PLL registers */
	uint32_t pll_ref_div = 0;
	uint32_t pll_fb_post_div = 0;
	uint32_t htotal_cntl = 0;
	bool is_tv = false;
	struct radeon_pll *pll;
 
	struct {
		int divider;
		int bitvalue;
	} *post_div, post_divs[]   = {
		/* From RAGE 128 VR/RAGE 128 GL Register
		 * Reference Manual (Technical Reference
		 * Manual P/N RRG-G04100-C Rev. 0.04), page
		 * 3-17 (PLL_DIV_[3:0]).
		 */
		{  1, 0 },              /* VCLK_SRC                 */
		{  2, 1 },              /* VCLK_SRC/2               */
		{  4, 2 },              /* VCLK_SRC/4               */
		{  8, 3 },              /* VCLK_SRC/8               */
		{  3, 4 },              /* VCLK_SRC/3               */
		{ 16, 5 },              /* VCLK_SRC/16              */
		{  6, 6 },              /* VCLK_SRC/6               */
		{ 12, 7 },              /* VCLK_SRC/12              */
		{  0, 0 }
	};
 
	if (radeon_crtc->crtc_id)
		pll = &rdev->clock.p2pll;
	else
		pll = &rdev->clock.p1pll;
 
	if (mode->clock > 200000) /* range limits??? */
		pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
	else
		pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 
			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
				is_tv = true;
				break;
			}
 
			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
				pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
			if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
				if (!rdev->is_atom_bios) {
				struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
				struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
				if (lvds) {
					if (lvds->use_bios_dividers) {
						pll_ref_div = lvds->panel_ref_divider;
						pll_fb_post_div   = (lvds->panel_fb_divider |
								     (lvds->panel_post_divider << 16));
						htotal_cntl  = 0;
						use_bios_divs = true;
					}
				}
				}
				pll_flags |= RADEON_PLL_USE_REF_DIV;
			}
		}
	}
 
	DRM_DEBUG("\n");
 
	if (!use_bios_divs) {
		radeon_compute_pll(pll, mode->clock,
				   &freq, &feedback_div, &frac_fb_div,
				   &reference_div, &post_divider,
				   pll_flags);
 
		for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
			if (post_div->divider == post_divider)
				break;
		}
 
		if (!post_div->divider)
			post_div = &post_divs[0];
 
		DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
			  (unsigned)freq,
			  feedback_div,
			  reference_div,
			  post_divider);
 
		pll_ref_div   = reference_div;
#if defined(__powerpc__) && (0) /* TODO */
		/* apparently programming this otherwise causes a hang??? */
		if (info->MacModel == RADEON_MAC_IBOOK)
			pll_fb_post_div = 0x000600ad;
		else
#endif
			pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 
		htotal_cntl    = mode->htotal & 0x7;
 
	}
 
	pll_gain = radeon_compute_pll_gain(pll->reference_freq,
					   pll_ref_div & 0x3ff,
					   pll_fb_post_div & 0x7ff);
 
	if (radeon_crtc->crtc_id) {
		uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
					  ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
					 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 
		if (is_tv) {
			radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
						     &pll_ref_div, &pll_fb_post_div,
						     &pixclks_cntl);
		}
 
		WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
			     RADEON_PIX2CLK_SRC_SEL_CPUCLK,
			     ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 
		WREG32_PLL_P(RADEON_P2PLL_CNTL,
			     RADEON_P2PLL_RESET
			     | RADEON_P2PLL_ATOMIC_UPDATE_EN
			     | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
			     ~(RADEON_P2PLL_RESET
			       | RADEON_P2PLL_ATOMIC_UPDATE_EN
			       | RADEON_P2PLL_PVG_MASK));
 
		WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
			     pll_ref_div,
			     ~RADEON_P2PLL_REF_DIV_MASK);
 
		WREG32_PLL_P(RADEON_P2PLL_DIV_0,
			     pll_fb_post_div,
			     ~RADEON_P2PLL_FB0_DIV_MASK);
 
		WREG32_PLL_P(RADEON_P2PLL_DIV_0,
			     pll_fb_post_div,
			     ~RADEON_P2PLL_POST0_DIV_MASK);
 
		radeon_pll2_write_update(dev);
		radeon_pll2_wait_for_read_update_complete(dev);
 
		WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 
		WREG32_PLL_P(RADEON_P2PLL_CNTL,
			     0,
			     ~(RADEON_P2PLL_RESET
			       | RADEON_P2PLL_SLEEP
			       | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 
		DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
			  (unsigned)pll_ref_div,
			  (unsigned)pll_fb_post_div,
			  (unsigned)htotal_cntl,
			  RREG32_PLL(RADEON_P2PLL_CNTL));
		DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
			  (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
			  (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
			  (unsigned)((pll_fb_post_div &
				      RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 
		mdelay(50); /* Let the clock to lock */
 
		WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
			     RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
			     ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 
		WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
	} else {
		uint32_t pixclks_cntl;
 
 
		if (is_tv) {
			pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
			radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
						     &pll_fb_post_div, &pixclks_cntl);
		}
 
		if (rdev->flags & RADEON_IS_MOBILITY) {
			/* A temporal workaround for the occational blanking on certain laptop panels.
			   This appears to related to the PLL divider registers (fail to lock?).
			   It occurs even when all dividers are the same with their old settings.
			   In this case we really don't need to fiddle with PLL registers.
			   By doing this we can avoid the blanking problem with some panels.
			*/
			if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
			    (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
						 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
				WREG32_P(RADEON_CLOCK_CNTL_INDEX,
					 RADEON_PLL_DIV_SEL,
					 ~(RADEON_PLL_DIV_SEL));
				r100_pll_errata_after_index(rdev);
				return;
			}
		}
 
		WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
			     RADEON_VCLK_SRC_SEL_CPUCLK,
			     ~(RADEON_VCLK_SRC_SEL_MASK));
		WREG32_PLL_P(RADEON_PPLL_CNTL,
			     RADEON_PPLL_RESET
			     | RADEON_PPLL_ATOMIC_UPDATE_EN
			     | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
			     | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
			     ~(RADEON_PPLL_RESET
			       | RADEON_PPLL_ATOMIC_UPDATE_EN
			       | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
			       | RADEON_PPLL_PVG_MASK));
 
		WREG32_P(RADEON_CLOCK_CNTL_INDEX,
			 RADEON_PLL_DIV_SEL,
			 ~(RADEON_PLL_DIV_SEL));
		r100_pll_errata_after_index(rdev);
 
		if (ASIC_IS_R300(rdev) ||
		    (rdev->family == CHIP_RS300) ||
		    (rdev->family == CHIP_RS400) ||
		    (rdev->family == CHIP_RS480)) {
			if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
				/* When restoring console mode, use saved PPLL_REF_DIV
				 * setting.
				 */
				WREG32_PLL_P(RADEON_PPLL_REF_DIV,
					     pll_ref_div,
					     0);
			} else {
				/* R300 uses ref_div_acc field as real ref divider */
				WREG32_PLL_P(RADEON_PPLL_REF_DIV,
					     (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
					     ~R300_PPLL_REF_DIV_ACC_MASK);
			}
		} else
			WREG32_PLL_P(RADEON_PPLL_REF_DIV,
				     pll_ref_div,
				     ~RADEON_PPLL_REF_DIV_MASK);
 
		WREG32_PLL_P(RADEON_PPLL_DIV_3,
			     pll_fb_post_div,
			     ~RADEON_PPLL_FB3_DIV_MASK);
 
		WREG32_PLL_P(RADEON_PPLL_DIV_3,
			     pll_fb_post_div,
			     ~RADEON_PPLL_POST3_DIV_MASK);
 
		radeon_pll_write_update(dev);
		radeon_pll_wait_for_read_update_complete(dev);
 
		WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 
		WREG32_PLL_P(RADEON_PPLL_CNTL,
			     0,
			     ~(RADEON_PPLL_RESET
			       | RADEON_PPLL_SLEEP
			       | RADEON_PPLL_ATOMIC_UPDATE_EN
			       | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 
		DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
			  pll_ref_div,
			  pll_fb_post_div,
			  (unsigned)htotal_cntl,
			  RREG32_PLL(RADEON_PPLL_CNTL));
		DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
			  pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
			  pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
			  (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 
		mdelay(50); /* Let the clock to lock */
 
		WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
			     RADEON_VCLK_SRC_SEL_PPLLCLK,
			     ~(RADEON_VCLK_SRC_SEL_MASK));
 
		if (is_tv)
			WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
	}
}
 
static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
				   struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode)
{
	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
		return false;
	return true;
}
 
static int radeon_crtc_mode_set(struct drm_crtc *crtc,
				 struct drm_display_mode *mode,
				 struct drm_display_mode *adjusted_mode,
				 int x, int y, struct drm_framebuffer *old_fb)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
	/* TODO TV */
	radeon_crtc_set_base(crtc, x, y, old_fb);
	radeon_set_crtc_timing(crtc, adjusted_mode);
	radeon_set_pll(crtc, adjusted_mode);
	radeon_overscan_setup(crtc, adjusted_mode);
	if (radeon_crtc->crtc_id == 0) {
		radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
	} else {
		if (radeon_crtc->rmx_type != RMX_OFF) {
			/* FIXME: only first crtc has rmx what should we
			 * do ?
			 */
			DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
		}
	}
	return 0;
}
 
static void radeon_crtc_prepare(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_crtc *crtci;
 
	/*
	* The hardware wedges sometimes if you reconfigure one CRTC
	* whilst another is running (see fdo bug #24611).
	*/
	list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
		radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
}
 
static void radeon_crtc_commit(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_crtc *crtci;
 
	/*
	* Reenable the CRTCs that should be running.
	*/
	list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
		if (crtci->enabled)
			radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
	}
}
 
static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
	.dpms = radeon_crtc_dpms,
	.mode_fixup = radeon_crtc_mode_fixup,
	.mode_set = radeon_crtc_mode_set,
	.mode_set_base = radeon_crtc_set_base,
	.prepare = radeon_crtc_prepare,
	.commit = radeon_crtc_commit,
	.load_lut = radeon_crtc_load_lut,
};
 
 
void radeon_legacy_init_crtc(struct drm_device *dev,
			       struct radeon_crtc *radeon_crtc)
{
	if (radeon_crtc->crtc_id == 1)
		radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
	drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
}
 
>
 
>
>
>

Rev 1275	Rev 1321
1	/*	1	/*
2	* Copyright 2007-8 Advanced Micro Devices, Inc.	2	* Copyright 2007-8 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the "Software"),	6	* copy of this software and associated documentation files (the "Software"),
7	* to deal in the Software without restriction, including without limitation	7	* to deal in the Software without restriction, including without limitation
8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9	* and/or sell copies of the Software, and to permit persons to whom the	9	* and/or sell copies of the Software, and to permit persons to whom the
10	* Software is furnished to do so, subject to the following conditions:	10	* Software is furnished to do so, subject to the following conditions:
11	*	11	*
12	* The above copyright notice and this permission notice shall be included in	12	* The above copyright notice and this permission notice shall be included in
13	* all copies or substantial portions of the Software.	13	* all copies or substantial portions of the Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21	* OTHER DEALINGS IN THE SOFTWARE.	21	* OTHER DEALINGS IN THE SOFTWARE.
22	*	22	*
23	* Authors: Dave Airlie	23	* Authors: Dave Airlie
24	* Alex Deucher	24	* Alex Deucher
25	*/	25	*/
26	#include	26	#include
27	#include	27	#include
28	#include	28	#include
29	#include "radeon_fixed.h"	29	#include "radeon_fixed.h"
30	#include "radeon.h"	30	#include "radeon.h"
31	#include "atom.h"	31	#include "atom.h"
-		32
-		33	static void radeon_overscan_setup(struct drm_crtc *crtc,
-		34	struct drm_display_mode *mode)
-		35	{
-		36	struct drm_device *dev = crtc->dev;
-		37	struct radeon_device *rdev = dev->dev_private;
-		38	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-		39
-		40	WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
-		41	WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
-		42	WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
-		43	}
32		44
33	static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,	45	static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
34	struct drm_display_mode *mode,	46	struct drm_display_mode *mode,
35	struct drm_display_mode *adjusted_mode)	47	struct drm_display_mode *adjusted_mode)
36	{	48	{
37	struct drm_device *dev = crtc->dev;	49	struct drm_device *dev = crtc->dev;
38	struct radeon_device *rdev = dev->dev_private;	50	struct radeon_device *rdev = dev->dev_private;
39	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	51	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40	int xres = mode->hdisplay;	52	int xres = mode->hdisplay;
41	int yres = mode->vdisplay;	53	int yres = mode->vdisplay;
42	bool hscale = true, vscale = true;	54	bool hscale = true, vscale = true;
43	int hsync_wid;	55	int hsync_wid;
44	int vsync_wid;	56	int vsync_wid;
45	int hsync_start;	57	int hsync_start;
46	int blank_width;	58	int blank_width;
47	u32 scale, inc, crtc_more_cntl;	59	u32 scale, inc, crtc_more_cntl;
48	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;	60	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
49	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;	61	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
50	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;	62	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
51	struct drm_display_mode *native_mode = &radeon_crtc->native_mode;	63	struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
52		64
53	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &	65	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
54	(RADEON_VERT_STRETCH_RESERVED \|	66	(RADEON_VERT_STRETCH_RESERVED \|
55	RADEON_VERT_AUTO_RATIO_INC);	67	RADEON_VERT_AUTO_RATIO_INC);
56	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &	68	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
57	(RADEON_HORZ_FP_LOOP_STRETCH \|	69	(RADEON_HORZ_FP_LOOP_STRETCH \|
58	RADEON_HORZ_AUTO_RATIO_INC);	70	RADEON_HORZ_AUTO_RATIO_INC);
59		71
60	crtc_more_cntl = 0;	72	crtc_more_cntl = 0;
61	if ((rdev->family == CHIP_RS100) \|\|	73	if ((rdev->family == CHIP_RS100) \|\|
62	(rdev->family == CHIP_RS200)) {	74	(rdev->family == CHIP_RS200)) {
63	/* This is to workaround the asic bug for RMX, some versions	75	/* This is to workaround the asic bug for RMX, some versions
64	of BIOS dosen't have this register initialized correctly. */	76	of BIOS dosen't have this register initialized correctly. */
65	crtc_more_cntl \|= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;	77	crtc_more_cntl \|= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
66	}	78	}
67		79
68		80
69	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)	81	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
70	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));	82	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
71		83
72	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;	84	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
73	if (!hsync_wid)	85	if (!hsync_wid)
74	hsync_wid = 1;	86	hsync_wid = 1;
75	hsync_start = mode->crtc_hsync_start - 8;	87	hsync_start = mode->crtc_hsync_start - 8;
76		88
77	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)	89	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
78	\| ((hsync_wid & 0x3f) << 16)	90	\| ((hsync_wid & 0x3f) << 16)
79	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)	91	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
80	? RADEON_CRTC_H_SYNC_POL	92	? RADEON_CRTC_H_SYNC_POL
81	: 0));	93	: 0));
82		94
83	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)	95	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
84	\| ((mode->crtc_vdisplay - 1) << 16));	96	\| ((mode->crtc_vdisplay - 1) << 16));
85		97
86	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;	98	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
87	if (!vsync_wid)	99	if (!vsync_wid)
88	vsync_wid = 1;	100	vsync_wid = 1;
89		101
90	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)	102	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
91	\| ((vsync_wid & 0x1f) << 16)	103	\| ((vsync_wid & 0x1f) << 16)
92	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)	104	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
93	? RADEON_CRTC_V_SYNC_POL	105	? RADEON_CRTC_V_SYNC_POL
94	: 0));	106	: 0));
95		107
96	fp_horz_vert_active = 0;	108	fp_horz_vert_active = 0;
97		109
98	if (native_mode->hdisplay == 0 \|\|	110	if (native_mode->hdisplay == 0 \|\|
99	native_mode->vdisplay == 0) {	111	native_mode->vdisplay == 0) {
100	hscale = false;	112	hscale = false;
101	vscale = false;	113	vscale = false;
102	} else {	114	} else {
103	if (xres > native_mode->hdisplay)	115	if (xres > native_mode->hdisplay)
104	xres = native_mode->hdisplay;	116	xres = native_mode->hdisplay;
105	if (yres > native_mode->vdisplay)	117	if (yres > native_mode->vdisplay)
106	yres = native_mode->vdisplay;	118	yres = native_mode->vdisplay;
107		119
108	if (xres == native_mode->hdisplay)	120	if (xres == native_mode->hdisplay)
109	hscale = false;	121	hscale = false;
110	if (yres == native_mode->vdisplay)	122	if (yres == native_mode->vdisplay)
111	vscale = false;	123	vscale = false;
112	}	124	}
113		125
114	switch (radeon_crtc->rmx_type) {	126	switch (radeon_crtc->rmx_type) {
115	case RMX_FULL:	127	case RMX_FULL:
116	case RMX_ASPECT:	128	case RMX_ASPECT:
117	if (!hscale)	129	if (!hscale)
118	fp_horz_stretch \|= ((xres/8-1) << 16);	130	fp_horz_stretch \|= ((xres/8-1) << 16);
119	else {	131	else {
120	inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;	132	inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
121	scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)	133	scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
122	/ native_mode->hdisplay + 1;	134	/ native_mode->hdisplay + 1;
123	fp_horz_stretch \|= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) \|	135	fp_horz_stretch \|= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) \|
124	RADEON_HORZ_STRETCH_BLEND \|	136	RADEON_HORZ_STRETCH_BLEND \|
125	RADEON_HORZ_STRETCH_ENABLE \|	137	RADEON_HORZ_STRETCH_ENABLE \|
126	((native_mode->hdisplay/8-1) << 16));	138	((native_mode->hdisplay/8-1) << 16));
127	}	139	}
128		140
129	if (!vscale)	141	if (!vscale)
130	fp_vert_stretch \|= ((yres-1) << 12);	142	fp_vert_stretch \|= ((yres-1) << 12);
131	else {	143	else {
132	inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;	144	inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
133	scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)	145	scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
134	/ native_mode->vdisplay + 1;	146	/ native_mode->vdisplay + 1;
135	fp_vert_stretch \|= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) \|	147	fp_vert_stretch \|= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) \|
136	RADEON_VERT_STRETCH_ENABLE \|	148	RADEON_VERT_STRETCH_ENABLE \|
137	RADEON_VERT_STRETCH_BLEND \|	149	RADEON_VERT_STRETCH_BLEND \|
138	((native_mode->vdisplay-1) << 12));	150	((native_mode->vdisplay-1) << 12));
139	}	151	}
140	break;	152	break;
141	case RMX_CENTER:	153	case RMX_CENTER:
142	fp_horz_stretch \|= ((xres/8-1) << 16);	154	fp_horz_stretch \|= ((xres/8-1) << 16);
143	fp_vert_stretch \|= ((yres-1) << 12);	155	fp_vert_stretch \|= ((yres-1) << 12);
144		156
145	crtc_more_cntl \|= (RADEON_CRTC_AUTO_HORZ_CENTER_EN \|	157	crtc_more_cntl \|= (RADEON_CRTC_AUTO_HORZ_CENTER_EN \|
146	RADEON_CRTC_AUTO_VERT_CENTER_EN);	158	RADEON_CRTC_AUTO_VERT_CENTER_EN);
147		159
148	blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;	160	blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
149	if (blank_width > 110)	161	if (blank_width > 110)
150	blank_width = 110;	162	blank_width = 110;
151		163
152	fp_crtc_h_total_disp = (((blank_width) & 0x3ff)	164	fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
153	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));	165	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
154		166
155	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;	167	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
156	if (!hsync_wid)	168	if (!hsync_wid)
157	hsync_wid = 1;	169	hsync_wid = 1;
158		170
159	fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)	171	fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
160	\| ((hsync_wid & 0x3f) << 16)	172	\| ((hsync_wid & 0x3f) << 16)
161	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)	173	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
162	? RADEON_CRTC_H_SYNC_POL	174	? RADEON_CRTC_H_SYNC_POL
163	: 0));	175	: 0));
164		176
165	fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)	177	fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
166	\| ((mode->crtc_vdisplay - 1) << 16));	178	\| ((mode->crtc_vdisplay - 1) << 16));
167		179
168	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;	180	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
169	if (!vsync_wid)	181	if (!vsync_wid)
170	vsync_wid = 1;	182	vsync_wid = 1;
171		183
172	fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)	184	fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
173	\| ((vsync_wid & 0x1f) << 16)	185	\| ((vsync_wid & 0x1f) << 16)
174	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)	186	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
175	? RADEON_CRTC_V_SYNC_POL	187	? RADEON_CRTC_V_SYNC_POL
176	: 0)));	188	: 0)));
177		189
178	fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) \|	190	fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) \|
179	(((native_mode->hdisplay / 8) & 0x1ff) << 16));	191	(((native_mode->hdisplay / 8) & 0x1ff) << 16));
180	break;	192	break;
181	case RMX_OFF:	193	case RMX_OFF:
182	default:	194	default:
183	fp_horz_stretch \|= ((xres/8-1) << 16);	195	fp_horz_stretch \|= ((xres/8-1) << 16);
184	fp_vert_stretch \|= ((yres-1) << 12);	196	fp_vert_stretch \|= ((yres-1) << 12);
185	break;	197	break;
186	}	198	}
187		199
188	WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);	200	WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
189	WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);	201	WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
190	WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);	202	WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
191	WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);	203	WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
192	WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);	204	WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
193	WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);	205	WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
194	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);	206	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
195	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);	207	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
196	}	208	}
197		209
198	void radeon_restore_common_regs(struct drm_device *dev)	210	void radeon_restore_common_regs(struct drm_device *dev)
199	{	211	{
200	/* don't need this yet */	212	/* don't need this yet */
201	}	213	}
202		214
203	static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)	215	static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
204	{	216	{
205	struct radeon_device *rdev = dev->dev_private;	217	struct radeon_device *rdev = dev->dev_private;
206	int i = 0;	218	int i = 0;
207		219
208	/* FIXME: Certain revisions of R300 can't recover here. Not sure of	220	/* FIXME: Certain revisions of R300 can't recover here. Not sure of
209	the cause yet, but this workaround will mask the problem for now.	221	the cause yet, but this workaround will mask the problem for now.
210	Other chips usually will pass at the very first test, so the	222	Other chips usually will pass at the very first test, so the
211	workaround shouldn't have any effect on them. */	223	workaround shouldn't have any effect on them. */
212	for (i = 0;	224	for (i = 0;
213	(i < 10000 &&	225	(i < 10000 &&
214	RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);	226	RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
215	i++);	227	i++);
216	}	228	}
217		229
218	static void radeon_pll_write_update(struct drm_device *dev)	230	static void radeon_pll_write_update(struct drm_device *dev)
219	{	231	{
220	struct radeon_device *rdev = dev->dev_private;	232	struct radeon_device *rdev = dev->dev_private;
221		233
222	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);	234	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
223		235
224	WREG32_PLL_P(RADEON_PPLL_REF_DIV,	236	WREG32_PLL_P(RADEON_PPLL_REF_DIV,
225	RADEON_PPLL_ATOMIC_UPDATE_W,	237	RADEON_PPLL_ATOMIC_UPDATE_W,
226	~(RADEON_PPLL_ATOMIC_UPDATE_W));	238	~(RADEON_PPLL_ATOMIC_UPDATE_W));
227	}	239	}
228		240
229	static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)	241	static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
230	{	242	{
231	struct radeon_device *rdev = dev->dev_private;	243	struct radeon_device *rdev = dev->dev_private;
232	int i = 0;	244	int i = 0;
233		245
234		246
235	/* FIXME: Certain revisions of R300 can't recover here. Not sure of	247	/* FIXME: Certain revisions of R300 can't recover here. Not sure of
236	the cause yet, but this workaround will mask the problem for now.	248	the cause yet, but this workaround will mask the problem for now.
237	Other chips usually will pass at the very first test, so the	249	Other chips usually will pass at the very first test, so the
238	workaround shouldn't have any effect on them. */	250	workaround shouldn't have any effect on them. */
239	for (i = 0;	251	for (i = 0;
240	(i < 10000 &&	252	(i < 10000 &&
241	RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);	253	RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
242	i++);	254	i++);
243	}	255	}
244		256
245	static void radeon_pll2_write_update(struct drm_device *dev)	257	static void radeon_pll2_write_update(struct drm_device *dev)
246	{	258	{
247	struct radeon_device *rdev = dev->dev_private;	259	struct radeon_device *rdev = dev->dev_private;
248		260
249	while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);	261	while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
250		262
251	WREG32_PLL_P(RADEON_P2PLL_REF_DIV,	263	WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
252	RADEON_P2PLL_ATOMIC_UPDATE_W,	264	RADEON_P2PLL_ATOMIC_UPDATE_W,
253	~(RADEON_P2PLL_ATOMIC_UPDATE_W));	265	~(RADEON_P2PLL_ATOMIC_UPDATE_W));
254	}	266	}
255		267
256	static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,	268	static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
257	uint16_t fb_div)	269	uint16_t fb_div)
258	{	270	{
259	unsigned int vcoFreq;	271	unsigned int vcoFreq;
260		272
261	if (!ref_div)	273	if (!ref_div)
262	return 1;	274	return 1;
263		275
264	vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;	276	vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
265		277
266	/*	278	/*
267	* This is horribly crude: the VCO frequency range is divided into	279	* This is horribly crude: the VCO frequency range is divided into
268	* 3 parts, each part having a fixed PLL gain value.	280	* 3 parts, each part having a fixed PLL gain value.
269	*/	281	*/
270	if (vcoFreq >= 30000)	282	if (vcoFreq >= 30000)
271	/*	283	/*
272	* [300..max] MHz : 7	284	* [300..max] MHz : 7
273	*/	285	*/
274	return 7;	286	return 7;
275	else if (vcoFreq >= 18000)	287	else if (vcoFreq >= 18000)
276	/*	288	/*
277	* [180..300) MHz : 4	289	* [180..300) MHz : 4
278	*/	290	*/
279	return 4;	291	return 4;
280	else	292	else
281	/*	293	/*
282	* [0..180) MHz : 1	294	* [0..180) MHz : 1
283	*/	295	*/
284	return 1;	296	return 1;
285	}	297	}
286		298
287	void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)	299	void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
288	{	300	{
289	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	301	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
290	struct drm_device *dev = crtc->dev;	302	struct drm_device *dev = crtc->dev;
291	struct radeon_device *rdev = dev->dev_private;	303	struct radeon_device *rdev = dev->dev_private;
292	uint32_t mask;	304	uint32_t mask;
293		305
294	if (radeon_crtc->crtc_id)	306	if (radeon_crtc->crtc_id)
295	mask = (RADEON_CRTC2_EN \|	307	mask = (RADEON_CRTC2_DISP_DIS \|
296	RADEON_CRTC2_DISP_DIS \|	-
297	RADEON_CRTC2_VSYNC_DIS \|	308	RADEON_CRTC2_VSYNC_DIS \|
298	RADEON_CRTC2_HSYNC_DIS \|	309	RADEON_CRTC2_HSYNC_DIS \|
299	RADEON_CRTC2_DISP_REQ_EN_B);	310	RADEON_CRTC2_DISP_REQ_EN_B);
300	else	311	else
301	mask = (RADEON_CRTC_DISPLAY_DIS \|	312	mask = (RADEON_CRTC_DISPLAY_DIS \|
302	RADEON_CRTC_VSYNC_DIS \|	313	RADEON_CRTC_VSYNC_DIS \|
303	RADEON_CRTC_HSYNC_DIS);	314	RADEON_CRTC_HSYNC_DIS);
304		315
305	switch (mode) {	316	switch (mode) {
306	case DRM_MODE_DPMS_ON:	317	case DRM_MODE_DPMS_ON:
307	if (radeon_crtc->crtc_id)	318	if (radeon_crtc->crtc_id)
308	WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);	319	WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN \| mask));
309	else {	320	else {
310	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN \|	321	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN \|
311	RADEON_CRTC_DISP_REQ_EN_B));	322	RADEON_CRTC_DISP_REQ_EN_B));
312	WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);	323	WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
313	}	324	}
314	// drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);	325	// drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
315	radeon_crtc_load_lut(crtc);	326	radeon_crtc_load_lut(crtc);
316	break;	327	break;
317	case DRM_MODE_DPMS_STANDBY:	328	case DRM_MODE_DPMS_STANDBY:
318	case DRM_MODE_DPMS_SUSPEND:	329	case DRM_MODE_DPMS_SUSPEND:
319	case DRM_MODE_DPMS_OFF:	330	case DRM_MODE_DPMS_OFF:
320	// drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);	331	// drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
321	if (radeon_crtc->crtc_id)	332	if (radeon_crtc->crtc_id)
322	WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);	333	WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN \| mask));
323	else {	334	else {
324	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN \|	335	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN \|
325	RADEON_CRTC_DISP_REQ_EN_B));	336	RADEON_CRTC_DISP_REQ_EN_B));
326	WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);	337	WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
327	}	338	}
328	break;	339	break;
329	}	340	}
330	}	341	}
331		342
332	/* properly set crtc bpp when using atombios */	343	/* properly set crtc bpp when using atombios */
333	void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)	344	void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
334	{	345	{
335	struct drm_device *dev = crtc->dev;	346	struct drm_device *dev = crtc->dev;
336	struct radeon_device *rdev = dev->dev_private;	347	struct radeon_device *rdev = dev->dev_private;
337	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	348	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
338	int format;	349	int format;
339	uint32_t crtc_gen_cntl;	350	uint32_t crtc_gen_cntl;
340	uint32_t disp_merge_cntl;	351	uint32_t disp_merge_cntl;
341	uint32_t crtc_pitch;	352	uint32_t crtc_pitch;
342		353
343	switch (crtc->fb->bits_per_pixel) {	354	switch (crtc->fb->bits_per_pixel) {
344	case 8:	355	case 8:
345	format = 2;	356	format = 2;
346	break;	357	break;
347	case 15: /* 555 */	358	case 15: /* 555 */
348	format = 3;	359	format = 3;
349	break;	360	break;
350	case 16: /* 565 */	361	case 16: /* 565 */
351	format = 4;	362	format = 4;
352	break;	363	break;
353	case 24: /* RGB */	364	case 24: /* RGB */
354	format = 5;	365	format = 5;
355	break;	366	break;
356	case 32: /* xRGB */	367	case 32: /* xRGB */
357	format = 6;	368	format = 6;
358	break;	369	break;
359	default:	370	default:
360	return;	371	return;
361	}	372	}
362		373
363	crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +	374	crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
364	((crtc->fb->bits_per_pixel * 8) - 1)) /	375	((crtc->fb->bits_per_pixel * 8) - 1)) /
365	(crtc->fb->bits_per_pixel * 8));	376	(crtc->fb->bits_per_pixel * 8));
366	crtc_pitch \|= crtc_pitch << 16;	377	crtc_pitch \|= crtc_pitch << 16;
367		378
368	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);	379	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
369		380
370	switch (radeon_crtc->crtc_id) {	381	switch (radeon_crtc->crtc_id) {
371	case 0:	382	case 0:
372	disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);	383	disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
373	disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;	384	disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
374	WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);	385	WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
375		386
376	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;	387	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
377	crtc_gen_cntl \|= (format << 8);	388	crtc_gen_cntl \|= (format << 8);
378	crtc_gen_cntl \|= RADEON_CRTC_EXT_DISP_EN;	389	crtc_gen_cntl \|= RADEON_CRTC_EXT_DISP_EN;
379	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);	390	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
380	break;	391	break;
381	case 1:	392	case 1:
382	disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);	393	disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
383	disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;	394	disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
384	WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);	395	WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
385		396
386	crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;	397	crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
387	crtc_gen_cntl \|= (format << 8);	398	crtc_gen_cntl \|= (format << 8);
388	WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);	399	WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
389	WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));	400	WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
390	WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));	401	WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
391	break;	402	break;
392	}	403	}
393	}	404	}
394		405
395	int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,	406	int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
396	struct drm_framebuffer *old_fb)	407	struct drm_framebuffer *old_fb)
397	{	408	{
398	struct drm_device *dev = crtc->dev;	409	struct drm_device *dev = crtc->dev;
399	struct radeon_device *rdev = dev->dev_private;	410	struct radeon_device *rdev = dev->dev_private;
400	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	411	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
401	struct radeon_framebuffer *radeon_fb;	412	struct radeon_framebuffer *radeon_fb;
402	struct drm_gem_object *obj;	413	struct drm_gem_object *obj;
-		414	struct radeon_bo *rbo;
403	uint64_t base;	415	uint64_t base;
404	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;	416	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
405	uint32_t crtc_pitch, pitch_pixels;	417	uint32_t crtc_pitch, pitch_pixels;
406	uint32_t tiling_flags;	418	uint32_t tiling_flags;
407	int format;	419	int format;
408	uint32_t gen_cntl_reg, gen_cntl_val;	420	uint32_t gen_cntl_reg, gen_cntl_val;
-		421	int r;
409		422
-		423	DRM_DEBUG("\n");
-		424	/* no fb bound */
-		425	if (!crtc->fb) {
-		426	DRM_DEBUG("No FB bound\n");
-		427	return 0;
410	DRM_DEBUG("\n");	428	}
411		429
412	radeon_fb = to_radeon_framebuffer(crtc->fb);	430	radeon_fb = to_radeon_framebuffer(crtc->fb);
413		431
414	switch (crtc->fb->bits_per_pixel) {	432	switch (crtc->fb->bits_per_pixel) {
415	case 8:	433	case 8:
416	format = 2;	434	format = 2;
417	break;	435	break;
418	case 15: /* 555 */	436	case 15: /* 555 */
419	format = 3;	437	format = 3;
420	break;	438	break;
421	case 16: /* 565 */	439	case 16: /* 565 */
422	format = 4;	440	format = 4;
423	break;	441	break;
424	case 24: /* RGB */	442	case 24: /* RGB */
425	format = 5;	443	format = 5;
426	break;	444	break;
427	case 32: /* xRGB */	445	case 32: /* xRGB */
428	format = 6;	446	format = 6;
429	break;	447	break;
430	default:	448	default:
431	return false;	449	return false;
432	}	450	}
-		451
433		452	/* Pin framebuffer & get tilling informations */
-		453	obj = radeon_fb->obj;
-		454	rbo = obj->driver_private;
-		455	r = radeon_bo_reserve(rbo, false);
-		456	if (unlikely(r != 0))
434	obj = radeon_fb->obj;	457	return r;
-		458	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
-		459	if (unlikely(r != 0)) {
435	// if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {	460	radeon_bo_unreserve(rbo);
436	// return -EINVAL;	461	return -EINVAL;
-		462	}
437	// }	463	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
-		464	radeon_bo_unreserve(rbo);
-		465	if (tiling_flags & RADEON_TILING_MICRO)
438	base = rdev->mc.vram_location;	466	DRM_ERROR("trying to scanout microtiled buffer\n");
439		467
440	/* if scanout was in GTT this really wouldn't work */	468	/* if scanout was in GTT this really wouldn't work */
441	/* crtc offset is from display base addr not FB location */	469	/* crtc offset is from display base addr not FB location */
442	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;	470	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
443		471
444	base -= radeon_crtc->legacy_display_base_addr;	472	base -= radeon_crtc->legacy_display_base_addr;
445		473
446	crtc_offset_cntl = 0;	474	crtc_offset_cntl = 0;
447		475
448	pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);	476	pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
449	crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +	477	crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
450	((crtc->fb->bits_per_pixel * 8) - 1)) /	478	((crtc->fb->bits_per_pixel * 8) - 1)) /
451	(crtc->fb->bits_per_pixel * 8));	479	(crtc->fb->bits_per_pixel * 8));
452	crtc_pitch \|= crtc_pitch << 16;	480	crtc_pitch \|= crtc_pitch << 16;
453		-
454	// radeon_object_get_tiling_flags(obj->driver_private,	-
455	// &tiling_flags, NULL);	-
456	tiling_flags = 0;	-
457		-
458	if (tiling_flags & RADEON_TILING_MICRO)	-
459	DRM_ERROR("trying to scanout microtiled buffer\n");	481
460		482
461	if (tiling_flags & RADEON_TILING_MACRO) {	483	if (tiling_flags & RADEON_TILING_MACRO) {
462	if (ASIC_IS_R300(rdev))	484	if (ASIC_IS_R300(rdev))
463	crtc_offset_cntl \|= (R300_CRTC_X_Y_MODE_EN \|	485	crtc_offset_cntl \|= (R300_CRTC_X_Y_MODE_EN \|
464	R300_CRTC_MICRO_TILE_BUFFER_DIS \|	486	R300_CRTC_MICRO_TILE_BUFFER_DIS \|
465	R300_CRTC_MACRO_TILE_EN);	487	R300_CRTC_MACRO_TILE_EN);
466	else	488	else
467	crtc_offset_cntl \|= RADEON_CRTC_TILE_EN;	489	crtc_offset_cntl \|= RADEON_CRTC_TILE_EN;
468	} else {	490	} else {
469	if (ASIC_IS_R300(rdev))	491	if (ASIC_IS_R300(rdev))
470	crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN \|	492	crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN \|
471	R300_CRTC_MICRO_TILE_BUFFER_DIS \|	493	R300_CRTC_MICRO_TILE_BUFFER_DIS \|

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_legacy_crtc.c – Rev 1275 → 1321